HomeSort by: relevance | last modified time | path
    Searched refs:x250 (Results 1 - 25 of 61) sorted by relevancy

1 2 3

  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
vt8500.dtsi 76 enable-reg = <0x250>;
84 enable-reg = <0x250>;
92 enable-reg = <0x250>;
100 enable-reg = <0x250>;
wm8505.dtsi 148 enable-reg = <0x250>;
156 enable-reg = <0x250>;
164 enable-reg = <0x250>;
172 enable-reg = <0x250>;
180 enable-reg = <0x250>;
188 enable-reg = <0x250>;
wm8750.dtsi 207 enable-reg = <0x250>;
217 enable-reg = <0x250>;
226 enable-reg = <0x250>;
235 enable-reg = <0x250>;
wm8650.dtsi 152 enable-reg = <0x250>;
160 enable-reg = <0x250>;
wm8850.dtsi 202 enable-reg = <0x250>;
212 enable-reg = <0x250>;
keystone-k2hk.dtsi 125 reg = <0x250 0x4>;
128 gpio,syscon-dev = <&devctrl 0x250>;
imx25-pinfunc.h 75 #define MX25_PAD_A24__A24 0x038 0x250 0x000 0x00 0x000
76 #define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x05 0x000
77 #define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x06 0x000
78 #define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x07 0x000
imx35-pinfunc.h 635 #define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 0x250 0x6b4 0x000 0x0 0x0
636 #define MX35_PAD_SD2_DATA0__UART3_RXD_MUX 0x250 0x6b4 0x9a0 0x1 0x1
637 #define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 0x250 0x6b4 0x80c 0x2 0x0
638 #define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 0x250 0x6b4 0x940 0x3 0x1
639 #define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 0x250 0x6b4 0x9e4 0x4 0x0
640 #define MX35_PAD_SD2_DATA0__GPIO2_2 0x250 0x6b4 0x8c0 0x5 0x1
641 #define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK 0x250 0x6b4 0x994 0x6 0x3
imx6dl-pinfunc.h 811 #define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1
812 #define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0
813 #define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
814 #define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0
815 #define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1
816 #define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0
817 #define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3
imx6q-pinfunc.h 727 #define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
728 #define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
729 #define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
730 #define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
731 #define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
732 #define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
733 #define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
imx6sl-pinfunc.h 930 #define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0
931 #define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0
932 #define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2
933 #define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3
934 #define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0
935 #define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5
936 #define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
gk20a.h 81 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 37 reg = <0x00140000 0x250>;
343 0x250 MODE_NITRO /* usb3h_vbus_ppc */
  /src/sys/arch/amiga/dev/
wdc_buddha.c 153 if (bus_space_map(wdr->ctl_iot, 0x250+ch*0x80, 2, 0,
  /src/sbin/newfs_udf/
newfs_udf.c 170 context.max_udf = 0x250;
  /src/sys/arch/sparc64/dev/
ffbreg.h 170 #define FFB_FBC_FBRAMITC 0x250
  /src/sys/dev/pci/
voodoofbreg.h 144 #define SST_3D_LEFTOVERLAYBUF SST_3D_OFFSET+0x250
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
ppsmc.h 192 #define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
  /src/sys/dev/isa/
essreg.h 166 #define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250)
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 209 TEGRA_PIN("ph6", 0x250, "rsvd0", "rsvd1", "rsvd2", "rsvd3"),
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mm-pinfunc.h 639 #define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
640 #define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
641 #define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
642 #define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
643 #define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
644 #define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
645 #define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
imx8mq-pinfunc.h 607 #define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
608 #define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
609 #define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
610 #define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
611 #define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
612 #define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
613 #define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
imx8mn-pinfunc.h 641 #define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
642 #define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
643 #define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
644 #define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
645 #define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1
646 #define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
  /src/usr.sbin/makefs/
udf.c 151 context.max_udf = 0x250; /* 0x260 is not ready */
281 if (context.min_udf > 0x250)
289 if (context.max_udf > 0x250)
  /src/sys/arch/m68k/060sp/dist/
fplsp.doc 215 0x250: _060LSP__fabsx_

Completed in 58 milliseconds

1 2 3