Searched refs:GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (Results 1 - 14 of 14) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_reg.h140 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
H A Di965_video.c1540 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
H A Di965_render.c2687 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h113 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_reg.h140 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
H A Di965_video.c1541 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
H A Di965_render.c2687 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h113 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen6_render.h107 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
395 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
H A Dgen5_render.h139 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
H A Dgen6_render.c728 (kernels[1] ? GEN6_3DSTATE_WM_16_DISPATCH_ENABLE : 0) |
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen6_render.h107 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
395 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
H A Dgen5_render.h139 # define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) macro
H A Dgen6_render.c694 (kernels[1] ? GEN6_3DSTATE_WM_16_DISPATCH_ENABLE : 0) |

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