Searched refs:L2 (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/libX11/dist/src/xcms/
H A DHVC.c471 XcmsFloat theta, L2, u, v, nThetaLow, nThetaHigh;
549 L2 = (pColor->spec.CIEuvY.Y < 0.008856)
554 HVC_return.C = L2 * CHROMA_SCALE_FACTOR * XCMS_SQRT((double) ((u * u) + (v * v)));
558 HVC_return.V = L2;
466 XcmsFloat theta, L2, u, v, nThetaLow, nThetaHigh; local in function:XcmsCIEuvYToTekHVC
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.0.4.rst55 - radv: Invalidate L2 for TRANSFER_WRITE barriers
H A D17.0.3.rst51 - cherry-ignore: add the Invalidate L2 for TRANSFER_WRITE barriers fix
H A D19.2.1.rst122 - radeonsi/gfx10: fix L2 cache rinse programming
H A D13.0.5.rst173 - radeonsi: always set the TCL1_ACTION_ENA when invalidating L2
H A D12.0.2.rst323 - radeonsi: flush TC L2 cache for indirect draw data
H A D21.1.0.rst3277 - radeonsi: add a specialized function for CP DMA L2 prefetch
3421 - ac/gpu_info: conceal L2 cache sizes
3546 - radeonsi: set the clear/copy cache policy based on L2 cache size
3557 - radeonsi: don't do an L2 flush in compute_do_clear_or_copy if we're not syncing
3603 - radeonsi: don't cache FMASK transactions from CB in L2
5035 - radv: do not invalidate the L2 metadata cache on compute queues
5037 - radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9
5042 - radv: flush L2 for images affected by the pipe misaligned issue on GFX10+
H A D21.0.0.rst542 - radv: Use L2 for CP DMA on GFX9+.
543 - radv: Use L2 coherency on GFX9+.
3089 - radv: do not invalidate the L2 metadata cache on compute queues
3090 - radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9
3092 - radv: flush L2 for images affected by the pipe misaligned issue on GFX10+
H A D21.3.0.rst570 - radv: Try to do a better job of dealing with L2 coherent images.
573 - radv: Disable coherent L2 optimization on cards with noncoherent L2.
H A D19.3.0.rst2392 - radeonsi/gfx10: fix L2 cache rinse programming
3278 - radv: Fix L2 cache rinse programming.
H A D20.1.0.rst3045 - radeonsi/gfx10: cache metadata in L2 on small chips
3906 - radv/gfx10: cache metadata in L2 on small chips
H A D20.2.0.rst3238 - radeonsi: disable the L2 cache for most CPU mappings of textures
3239 - radeonsi: disable the L2 cache for CPU read mappings of buffers
H A D21.2.0.rst3471 - radeonsi: always use the L2 LRU cache policy for faster clears and copies
3472 - radeonsi: don't disable L2 caching for staging textures
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ddc/
H A Dedid.h116 #define L2 _L2(GET_ARRAY(V_MANUFACTURER)) macro
H A Dinterpret_edid.c346 r->name[1] = L2;
/xsrc/external/mit/xorg-server/dist/hw/xfree86/ddc/
H A Dedid.h115 #define L2 _L2(GET_ARRAY(V_MANUFACTURER)) macro
H A Dinterpret_edid.c444 r->name[1] = L2;
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json[all...]

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