Searched refs:OUTREG (Results 1 - 25 of 101) sorted by relevance

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/xsrc/external/mit/xf86-video-savage/dist/src/
H A Dsavage_streams.c64 OUTREG(COL_CHROMA_KEY_CONTROL_REG, 0x37000000 | (colorkey & 0xFF));
65 OUTREG(CHROMA_KEY_UPPER_BOUND_REG, 0x00000000 | (colorkey & 0xFF));
66 OUTREG(BLEND_CONTROL_REG, 0x05000000 );
67 OUTREG(SSTREAM_CONTROL_REG, SSTREAMS_MODE(DEPTH_BPP(DEPTH_2ND(pScrn)))
69 OUTREG(SSTREAM_STRETCH_REG, 1 << 15);
70 OUTREG(SSTREAM_VSCALE_REG, 1 << 15);
71 OUTREG(SSTREAM_LINES_REG, pScrn->virtualY );
72 OUTREG(SSTREAM_VINITIAL_REG, 0 );
73 OUTREG(SSTREAM_FBADDR0_REG, offset & 0x1ffffff & ~BASE_PAD);
74 OUTREG(SSTREAM_FBADDR1_RE
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H A Dsavage_video.c321 OUTREG(SEC_STREAM2_WINDOW_SZ, 0);
323 OUTREG(SEC_STREAM_WINDOW_SZ, 0);
325 OUTREG(SEC_STREAM_WINDOW_SZ, 0);
327 OUTREG(SEC_STREAM2_WINDOW_SZ, 0);
331 OUTREG(SEC_STREAM_WINDOW_SZ, 0);
333 OUTREG( SSTREAM_WINDOW_SIZE_REG, 1);
334 OUTREG( SSTREAM_WINDOW_START_REG, 0x03ff03ff);
424 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 );
425 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 );
426 OUTREG( BLEND_CONTROL_RE
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/xsrc/external/mit/xf86-video-i740/dist/src/
H A Di740_accel.c235 OUTREG(LP_FIFO, 0x6000000A);
236 OUTREG(LP_FIFO, pI740->bltcmd.BR00);
237 OUTREG(LP_FIFO, pI740->bltcmd.BR01);
238 OUTREG(LP_FIFO, 0x00000000);
239 OUTREG(LP_FIFO, 0x00000000);
240 OUTREG(LP_FIFO, pI740->bltcmd.BR04);
241 OUTREG(LP_FIFO, 0x00000000);
242 OUTREG(LP_FIFO, 0x00000000);
243 OUTREG(LP_FIFO, (y * pScrn->displayWidth + x) * pI740->cpp);
244 OUTREG(LP_FIF
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/xsrc/external/mit/xf86-video-neomagic/dist/src/
H A Dneo_2090.c232 OUTREG(NEOREG_BLTCNTL, nAcl->tmpBltCntlFlags);
247 OUTREG(NEOREG_BLTCNTL, nAcl->tmpBltCntlFlags);
248 OUTREG(NEOREG_SRCSTARTOFF, (srcY<<16) | (srcX & 0xffff));
249 OUTREG(NEOREG_DSTSTARTOFF, (dstY<<16) | (dstX & 0xffff));
250 OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
255 OUTREG(NEOREG_BLTCNTL, (nAcl->tmpBltCntlFlags | NEO_BC0_X_DEC
258 OUTREG(NEOREG_SRCSTARTOFF, ((srcY+h-1)<<16) | ((srcX+w-1) & 0xffff));
259 OUTREG(NEOREG_DSTSTARTOFF, ((dstY+h-1)<<16) | ((dstX+w-1) & 0xffff));
260 OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
275 OUTREG(NEOREG_BLTCNT
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H A Dneo_2200.c287 OUTREG(NEOREG_BLTSTAT, nAcl->BltModeFlags << 16);
288 OUTREG(NEOREG_BLTCNTL, nAcl->tmpBltCntlFlags);
289 OUTREG(NEOREG_PITCH, (nAcl->Pitch<<16)
307 OUTREG(NEOREG_BLTCNTL, nAcl->tmpBltCntlFlags);
309 OUTREG(NEOREG_SRCSTARTOFF,
311 OUTREG(NEOREG_DSTSTARTOFF,
313 OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
319 OUTREG(NEOREG_BLTCNTL, (nAcl->tmpBltCntlFlags
324 OUTREG(NEOREG_SRCSTARTOFF,
327 OUTREG(NEOREG_DSTSTARTOF
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H A Dneo_2070.c191 OUTREG(NEO2070_BLTCNTL, nAcl->tmpBltCntlFlags);
192 OUTREG(NEO2070_PLANEMASK, planemask |= (planemask << nAcl->ColorShiftAmt));
193 OUTREG(NEO2070_SRCPITCH, nAcl->Pitch);
194 OUTREG(NEO2070_DSTPITCH, nAcl->Pitch);
195 OUTREG(NEO2070_SRCBITOFF, 0);
196 OUTREG(NEO2070_DSTBITOFF, 0);
211 OUTREG(NEO2070_BLTCNTL, nAcl->tmpBltCntlFlags);
212 OUTREG(NEO2070_XYEXT, ((h-1)<<16) | ((w-1) & 0xffff));
213 OUTREG(NEO2070_SRCSTART,
215 OUTREG(NEO2070_DSTSTAR
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H A Dneo_2097.c294 OUTREG(NEOREG_BLTCNTL, nAcl->tmpBltCntlFlags);
295 OUTREG(NEOREG_SRCSTARTOFF, (srcY<<16) | (srcX & 0xffff));
296 OUTREG(NEOREG_DSTSTARTOFF, (dstY<<16) | (dstX & 0xffff));
297 OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
302 OUTREG(NEOREG_BLTCNTL, (nAcl->tmpBltCntlFlags | NEO_BC0_X_DEC
305 OUTREG(NEOREG_SRCSTARTOFF, ((srcY+h-1)<<16) | ((srcX+w-1) & 0xffff));
306 OUTREG(NEOREG_DSTSTARTOFF, ((dstY+h-1)<<16) | ((dstX+w-1) & 0xffff));
307 OUTREG(NEOREG_XYEXT, (h<<16) | (w & 0xffff));
322 OUTREG(NEOREG_BLTCNTL, nAcl->BltCntlFlags |
329 OUTREG(NEOREG_FGCOLO
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/xsrc/external/mit/xf86-video-mga/dist/src/
H A Dmga_storm.c44 OUTREG(MGAREG_FCOL,(rep_c)); \
50 OUTREG(MGAREG_BCOL,(rep_c)); \
332 OUTREG(MGAREG_TMR0, (1 << 20) / tex_padw); /* sx inc */
333 OUTREG(MGAREG_TMR1, 0); /* sy inc */
334 OUTREG(MGAREG_TMR2, 0); /* tx inc */
335 OUTREG(MGAREG_TMR3, (1 << 20) / tex_padh); /* ty inc */
336 OUTREG(MGAREG_TMR4, 0x00000000);
337 OUTREG(MGAREG_TMR5, 0x00000000);
338 OUTREG(MGAREG_TMR8, 0x00010000);
339 OUTREG(MGAREG_TEXOR
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H A Dmga_exa.c153 OUTREG(MGAREG_MACCESS, mgaGetMACCESS(pixmap, pict));
155 OUTREG(MGAREG_CXBNDRY, 0xffff0000);
156 OUTREG(MGAREG_YTOP, 0x00000000);
157 OUTREG(MGAREG_YBOT, 0x007fffff);
197 OUTREG(MGAREG_PITCH, mgaGetPixmapPitch(pPixmap));
198 OUTREG(MGAREG_DSTORG, exaGetPixmapOffset(pPixmap));
199 OUTREG(MGAREG_FCOL, fg);
200 OUTREG(MGAREG_PLNWT, planemask);
201 OUTREG(MGAREG_DWGCTL, dwgctl);
212 OUTREG(MGAREG_FXBNDR
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/xsrc/external/mit/xf86-video-imstt/dist/src/
H A Dimstt_accel.c89 OUTREG(IMSTT_DSA, x + y);
90 OUTREG(IMSTT_CNT, (h << 16) | w);
91 OUTREG(IMSTT_DP_OCTL, iptr->ll);
92 OUTREG(IMSTT_SP, iptr->ll);
93 OUTREG(IMSTT_BI, 0xffffffff);
94 OUTREG(IMSTT_MBC, 0xffffffff);
95 OUTREG(IMSTT_CLR, iptr->color);
98 OUTREG(IMSTT_BLTCTL, 0x200000);
100 OUTREG(IMSTT_BLTCTL, 0x840);
174 OUTREG(IMSTT_S1S
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/xsrc/external/mit/xf86-video-ati/dist/src/
H A Datombios_output.c1037 OUTREG(0x659C + radeon_crtc->crtc_offset, 0x0);
1038 OUTREG(0x6594 + radeon_crtc->crtc_offset, 0x705);
1039 OUTREG(0x65A4 + radeon_crtc->crtc_offset, 0x10001);
1040 OUTREG(0x65D8 + radeon_crtc->crtc_offset, 0x0);
1041 OUTREG(0x65B0 + radeon_crtc->crtc_offset, 0x0);
1042 OUTREG(0x65C0 + radeon_crtc->crtc_offset, 0x0);
1043 OUTREG(0x65D4 + radeon_crtc->crtc_offset, 0x0);
1044 OUTREG(index_reg,0x0);
1045 OUTREG(data_reg,0x841880A8);
1046 OUTREG(index_re
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H A Dradeon_vip.c62 OUTREG(RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK);
84 OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
122 OUTREG(RADEON_VIPH_REG_ADDR, address | 0x2000);
134 OUTREG(RADEON_VIPH_TIMEOUT_STAT, INREG(RADEON_VIPH_TIMEOUT_STAT) & (0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
150 OUTREG(RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
169 OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
188 OUTREG(VIPH_REG_ADDR, address | 0x3000);
201 OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
219 OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
240 OUTREG(VIPH_TIMEOUT_STA
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H A Dradeon_cursor.c77 OUTREG(RADEON_SURFACE_CNTL, \
85 OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); \
106 OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
112 OUTREG(R700_D2CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf);
114 OUTREG(R700_D1CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf);
116 OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
118 OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
138 OUTREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, tmp);
152 OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
157 OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS_HIG
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H A Dlegacy_output.c260 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
264 OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
266 OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
270 OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl);
272 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
275 OUTREG(RADEON_DAC_MACRO_CNTL, restore->dac_macro_cntl);
279 OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
291 OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl);
292 OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl);
293 OUTREG(RADEON_FP_GEN_CNT
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H A Datombios_crtc.c607 OUTREG(EVERGREEN_P1PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
611 OUTREG(EVERGREEN_P2PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
617 OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
620 OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
761 OUTREG(AVIVO_D1VGA_CONTROL, 0);
764 OUTREG(AVIVO_D2VGA_CONTROL, 0);
767 OUTREG(EVERGREEN_D3VGA_CONTROL, 0);
770 OUTREG(EVERGREEN_D4VGA_CONTROL, 0);
773 OUTREG(EVERGREEN_D5VGA_CONTROL, 0);
776 OUTREG(EVERGREEN_D6VGA_CONTRO
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H A Dradeon_driver.c297 OUTREG(RADEON_MEM_CNTL, 0);
300 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
334 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL);
341 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE);
353 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
608 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
610 OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
638 OUTREG(RADEON_CLOCK_CNTL_DATA, data);
651 OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
654 OUTREG(RS600_MC_INDE
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H A Dradeon_tv.c224 OUTREG(RADEON_TEST_DEBUG_MUX, (INREG(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
244 OUTREG(RADEON_TEST_DEBUG_MUX, INREG(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
257 OUTREG(RADEON_TV_HOST_WRITE_DATA, value);
259 OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr);
260 OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
271 OUTREG(RADEON_TV_HOST_RD_WT_CNTL, 0);
283 OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr);
284 OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
295 OUTREG(RADEON_TV_HOST_RD_WT_CNTL, 0);
360 OUTREG(RADEON_TV_UV_AD
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/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_accel.c141 OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
143 OUTREG(R128_GEN_RESET_CNTL,
148 OUTREG(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
149 OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl);
317 OUTREG(R128_DP_GUI_MASTER_CNTL, (info->dp_gui_master_cntl
321 OUTREG(R128_DP_BRUSH_FRGD_CLR, color);
322 OUTREG(R128_DP_WRITE_MASK, planemask);
323 OUTREG(R128_DP_CNTL, (R128_DST_X_LEFT_TO_RIGHT
338 OUTREG(R128_DST_Y_X, (y << 16) | x);
339 OUTREG(R128_DST_WIDTH_HEIGH
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H A Dr128_video.c168 OUTREG(R128_OV0_SCALE_CNTL, 0x80000000);
169 OUTREG(R128_OV0_EXCLUSIVE_HORZ, 0);
170 OUTREG(R128_OV0_AUTO_FLIP_CNTL, 0); /* maybe */
171 OUTREG(R128_OV0_FILTER_CNTL, 0x0000000f);
172 OUTREG(R128_OV0_COLOUR_CNTL, (pPriv->brightness & 0x7f) |
175 OUTREG(R128_OV0_GRAPHICS_KEY_MSK, (1 << pScrn->depth) - 1);
176 OUTREG(R128_OV0_GRAPHICS_KEY_CLR, pPriv->colorKey);
177 OUTREG(R128_OV0_KEY_CNTL, R128_GRAPHIC_KEY_FN_NE);
178 OUTREG(R128_OV0_TEST, 0);
272 OUTREG(R128_OV0_SCALE_CNT
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H A Dr128_cursor.c115 OUTREG(R128_CUR_CLR0, bg);
116 OUTREG(R128_CUR_CLR1, fg);
119 OUTREG(R128_CUR2_CLR0, bg);
120 OUTREG(R128_CUR2_CLR1, fg);
149 OUTREG(R128_CUR_HORZ_VERT_OFF, (R128_CUR_LOCK | (xorigin << 16) | yorigin));
150 OUTREG(R128_CUR_HORZ_VERT_POSN, (R128_CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
151 OUTREG(R128_CUR_OFFSET, r128_crtc->cursor_offset + pScrn->fbOffset + yorigin * 16);
153 OUTREG(R128_CUR2_HORZ_VERT_OFF, (R128_CUR2_LOCK | (xorigin << 16) | yorigin));
154 OUTREG(R128_CUR2_HORZ_VERT_POSN, (R128_CUR2_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
155 OUTREG(R128_CUR2_OFFSE
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/xsrc/external/mit/xf86-video-s3virge/dist/src/
H A Ds3v_accel.c274 OUTREG(CMD_SET, CMD_NOP);
353 OUTREG(DEST_SRC_STR, ps3v->Bpl << 16 | ps3v->Bpl);
421 OUTREG(DEST_SRC_STR, ps3v->Bpl << 16 | ps3v->Bpl);
437 OUTREG(FIFO_CONTROL_REG, fifo_control);
438 OUTREG(MIU_CONTROL_REG, miu_control);
439 OUTREG(STREAMS_TIMEOUT_REG, streams_timeout);
440 OUTREG(MISC_TIMEOUT_REG, misc_timeout);
446 OUTREG(SRC_BASE, 0);
447 OUTREG(DEST_BASE, 0);
450 OUTREG(CLIP_L_
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/xsrc/external/mit/xf86-video-intel-old/dist/src/reg_dumper/
H A Dhotplug.c94 OUTREG(SDVOB, (0x0 << 10));
95 OUTREG(SDVOC, (0x0 << 10));
97 OUTREG(PORT_HOTPLUG_EN,
109 OUTREG(PORT_HOTPLUG_STAT,
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_tv.c787 OUTREG(TV_CTL, INREG(TV_CTL) | TV_ENC_ENABLE);
792 OUTREG(TV_CTL, INREG(TV_CTL) & ~TV_ENC_ENABLE);
862 OUTREG(TV_H_CTL_1, dev_priv->save_TV_H_CTL_1);
863 OUTREG(TV_H_CTL_2, dev_priv->save_TV_H_CTL_2);
864 OUTREG(TV_H_CTL_3, dev_priv->save_TV_H_CTL_3);
865 OUTREG(TV_V_CTL_1, dev_priv->save_TV_V_CTL_1);
866 OUTREG(TV_V_CTL_2, dev_priv->save_TV_V_CTL_2);
867 OUTREG(TV_V_CTL_3, dev_priv->save_TV_V_CTL_3);
868 OUTREG(TV_V_CTL_4, dev_priv->save_TV_V_CTL_4);
869 OUTREG(TV_V_CTL_
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H A Di830_cursor.c69 OUTREG(cursor_base, intel_crtc->cursor_argb_addr);
71 OUTREG(cursor_base, intel_crtc->cursor_addr);
85 OUTREG(CURSOR_SIZE, (I810_CURSOR_Y << 12) | I810_CURSOR_X);
107 OUTREG(cursor_control, temp);
163 OUTREG(CURSOR_A_POSITION, temp);
166 OUTREG(CURSOR_B_POSITION, temp);
208 OUTREG(cursor_control, temp);
234 OUTREG(cursor_control, temp);
247 OUTREG(pal0 + 0, bg & 0x00ffffff);
248 OUTREG(pal
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H A Di830_driver.c711 OUTREG(RENCLK_GATE_D1, 0);
712 OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
715 OUTREG(RAMCLK_GATE_D, 0);
721 OUTREG(DSPCLK_GATE_D, dspclk_gate);
723 OUTREG(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
724 OUTREG(RENCLK_GATE_D2, 0);
725 OUTREG(DSPCLK_GATE_D, 0);
726 OUTREG(RAMCLK_GATE_D, 0);
729 OUTREG(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
734 OUTREG(RENCLK_GATE_D
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