Searched refs:PIOBase (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/xf86-video-chips/dist/src/
H A Dct_Blitter.h70 {HW_DEBUG(0x4+2); while(inw(cPtr->PIOBase+DR(0x4)+2)&0x10){};}
73 {HW_DEBUG(0x4); outl(cPtr->PIOBase+DR(0x4),(op));}
76 {HW_DEBUG(0x5); outl(cPtr->PIOBase+DR(0x5),((srcAddr)&0x1FFFFFL));}
79 {HW_DEBUG(0x6); outl(cPtr->PIOBase+DR(0x6),((dstAddr)&0x1FFFFFL));}
82 {HW_DEBUG(0x0); outl(cPtr->PIOBase+DR(0x0),(((dstPitch)<<16)|(srcPitch)));}
86 {HW_DEBUG(0x7); outl(cPtr->PIOBase+DR(0x7),(((Height)<<16)|(Width)));}
89 {HW_DEBUG(0x1); outl(cPtr->PIOBase+DR(0x1),((srcAddr)&0x1FFFFFL));}
98 outl(cPtr->PIOBase+DR(0x2),((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \
107 outl(cPtr->PIOBase+DR(0x2),((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \
116 outl(cPtr->PIOBase
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H A Dct_bank.c71 outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x10));
90 outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x11));
109 outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x10));
110 outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x11));
128 outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x10));
146 outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x11));
164 outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x10));
165 outw(cPtr->PIOBase + 0x3D6, ((((bank << 5) & 0xFF) << 8) | 0x11));
184 outw(cPtr->PIOBase + 0x3D6, ((((bank << 3) & 0xFF) << 8) | 0x10));
185 outb(cPtr->PIOBase
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H A Dct_regs.c115 outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
116 outb(cPtr->PIOBase + CHIPS_XR_DATA, value);
122 outb(cPtr->PIOBase + CHIPS_XR_INDEX, index);
123 return inb(cPtr->PIOBase + CHIPS_XR_DATA);
129 outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
130 outb(cPtr->PIOBase + CHIPS_FR_DATA, value);
136 outb(cPtr->PIOBase + CHIPS_FR_INDEX, index);
137 return inb(cPtr->PIOBase + CHIPS_FR_DATA);
143 outb(cPtr->PIOBase + CHIPS_MR_INDEX, index);
144 outb(cPtr->PIOBase
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H A Dct_cursor.c107 outw(cPtr->PIOBase+DR(0x8), 0x21);
146 outw(cPtr->PIOBase+DR(0x8), 0x20);
197 outl(cPtr->PIOBase+DR(0xB), xy);
287 outl(cPtr->PIOBase+DR(0xA), (bg & 0xFFFFFF));
288 outl(cPtr->PIOBase+DR(0x9), (fg & 0xFFFFFF));
297 outl(cPtr->PIOBase+DR(0x9), packedcolfg);
327 outl(cPtr->PIOBase+DR(0x8),0x20);
329 outl(cPtr->PIOBase+DR(0xC),*(CARD32 *)tmp);
427 outl(cPtr->PIOBase+DR(0xC), cAcl->CursorAddress);
H A Dct_driver.h285 unsigned long PIOBase; member in struct:_CHIPSRec
H A Dct_driver.c1390 cPtr->PIOBase = hwp->PIOOffset;
1392 cPtr->PIOBase = 0;
6557 VgaReg->MiscOutReg = inb(cPtr->PIOBase + 0x3CC);
7244 outl(cPtr->PIOBase + DR(0x8), cPtr->HWCursorContents);
7266 cPtr->HWCursorContents = inl(cPtr->PIOBase + DR(0x8));
7267 outw(cPtr->PIOBase + DR(0x8), cPtr->HWCursorContents & 0xFFFE);
/xsrc/external/mit/xf86-video-tdfx/dist/src/
H A Dtdfx_io.c50 outb(pTDFX->PIOBase[0]+addr, index);
51 outb(pTDFX->PIOBase[0]+addr+1, val);
55 outb(pTDFX->PIOBase[0]+addr, index);
56 return inb(pTDFX->PIOBase[0]+addr+1);
60 outl(pTDFX->PIOBase[chip]+addr, val);
64 return inl(pTDFX->PIOBase[chip]+addr);
76 if (!pTDFX->PIOBase[0])
77 ErrorF("Can not set PIO Access before PIOBase[0]\n");
H A Dtdfx.h213 unsigned long PIOBase[MAXCHIPS]; member in struct:_TDFXRec
H A Dtdfx_driver.c402 pTDFX->PIOBase[0] = dev->regions[2].base_addr;
404 "PIO base = 0x%lx\n", pTDFX->PIOBase[0]);
486 if (pTDFX->PIOBase[0]) {
615 pTDFX->PIOBase[pTDFX->numChips] =
1025 (unsigned long)pTDFX->PIOBase[0]);
2256 /* hwp->PIOOffset = pTDFX->PIOBase[0] - 0x300;*/
/xsrc/external/mit/xf86-video-siliconmotion/dist/src/
H A Dregsmi.h67 outb(pSmi->PIOBase + indexPort, index);
68 return(inb(pSmi->PIOBase + dataPort));
79 outb(pSmi->PIOBase + indexPort, index);
80 outb(pSmi->PIOBase + dataPort, data);
90 return(inb(pSmi->PIOBase + port));
100 outb(pSmi->PIOBase + port, data);
H A Dsmi_driver.c445 pSmi->PIOBase = hwp->PIOOffset;
447 pSmi->PIOBase = 0;
2029 outb(pSmi->PIOBase + VGA_SEQ_INDEX, 0x18);
2030 tmp = inb(pSmi->PIOBase + VGA_SEQ_DATA);
2032 outb(pSmi->PIOBase + VGA_SEQ_DATA, tmp | 0x11);
2035 outb(pSmi->PIOBase + VGA_SEQ_INDEX, 0x21);
2036 tmp = inb(pSmi->PIOBase + VGA_SEQ_DATA);
2038 outb(pSmi->PIOBase + VGA_SEQ_DATA, tmp & ~0x03);
2059 outb(pSmi->PIOBase + VGA_SEQ_INDEX, 0x21);
2060 outb(pSmi->PIOBase
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H A Dsmi.h240 unsigned int PIOBase; /* Base of I/O ports */ member in struct:__anon910553c20208
H A Dsmilynx_crtc.c622 outb(pSmi->PIOBase + VGA_SEQ_INDEX, 0x18);
623 tmp = inb(pSmi->PIOBase + VGA_SEQ_DATA);
624 outb(pSmi->PIOBase + VGA_SEQ_DATA, tmp | 0x01);
H A Dsmilynx_hw.c370 outb(pSmi->PIOBase + VGA_SEQ_INDEX, 0x18);
371 tmp = inb(pSmi->PIOBase + VGA_SEQ_DATA);
372 outb(pSmi->PIOBase + VGA_SEQ_DATA, tmp | 0x01);
/xsrc/external/mit/xf86-video-trident/dist/src/
H A Dtrident_regs.h307 outb(pTrident->PIOBase + (addr), data); \
315 outw(pTrident->PIOBase + (addr), data); \
322 inb(pTrident->PIOBase + (addr)) \
H A Dtrident_driver.c512 unsigned long vgaIOBase = pTrident->PIOBase + VGAHWPTR(pScrn)->IOBase;
525 outb(pTrident->PIOBase + 0x3C4, 0x0B);
526 inb(pTrident->PIOBase + 0x3C5);
530 outb(pTrident->PIOBase + 0x3C4, Protection);
531 protect = inb(pTrident->PIOBase + 0x3C5);
532 outb(pTrident->PIOBase + 0x3C5, 0x92);
534 outb(pTrident->PIOBase + 0x3C4, NewMode1);
535 temp = inb(pTrident->PIOBase + 0x3C5);
536 outb(pTrident->PIOBase + 0x3C5, 0x80);
587 outb(pTrident->PIOBase
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H A Dtrident.h113 unsigned long PIOBase; member in struct:__anon52c1ffc60208

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