| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/ |
| H A D | test_insert_nops.cpp | 30 bld.mubuf(aco_opcode::buffer_load_dword, Definition(PhysReg(256), v1), Operand(PhysReg(0), s4), 31 Operand(PhysReg(256), v1), Operand::zero(), offset, true); 38 mimg->definitions[0] = Definition(PhysReg(256), v1); 39 mimg->operands[0] = Operand(PhysReg(0), s8); 40 mimg->operands[1] = Operand(PhysReg(0), s4); 43 mimg->operands[3 + i] = Operand(PhysReg(256 + (nsa ? i * 2 : i)), v1); 126 bld.writelane(Definition(PhysReg(511), v1), Operand::zero(), Operand::zero(), 127 Operand(PhysReg(511), v1)); 135 bld.writelane(Definition(PhysReg(51 [all...] |
| H A D | test_hard_clause.cpp | 32 desc_op.setFixed(PhysReg(0)); 33 bld.mubuf(aco_opcode::buffer_load_dword, Definition(PhysReg(256), v1), desc_op, 34 Operand(PhysReg(256), v1), Operand::zero(), 0, false) 41 bld.mubuf(aco_opcode::buffer_store_dword, Operand(PhysReg(0), s4), Operand(PhysReg(256), v1), 42 Operand(PhysReg(256), v1), Operand::zero(), 0, false); 48 desc_op.setFixed(PhysReg(0)); 49 bld.mtbuf(aco_opcode::tbuffer_load_format_x, Definition(PhysReg(256), v1), desc_op, 50 Operand(PhysReg(256), v1), Operand::zero(), V_008F0C_BUF_DATA_FORMAT_32, 58 bld.flat(aco_opcode::flat_load_dword, Definition(PhysReg(25 [all...] |
| H A D | test_assembler.cpp | 37 bld.smem(aco_opcode::s_memtime, bld.def(s2)).def(0).setFixed(PhysReg{0}); 50 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1); 73 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2); 104 bld.sopp(aco_opcode::s_cbranch_scc0, Definition(PhysReg(0), s2), 2); 141 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 0); 170 bld.sopp(aco_opcode::s_cbranch_execnz, Definition(PhysReg(0), s2), 0); 189 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1); 193 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2); 212 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2); 223 bld.sop1(aco_opcode::p_constaddr_getpc, Definition(PhysReg( [all...] |
| H A D | test_regalloc.cpp | 94 op.setFixed(PhysReg(2)); 108 op.setFixed(PhysReg(1)); 125 op.setFixed(PhysReg(2)); 142 op.setFixed(PhysReg(2)); 193 PhysReg reg_v0{256}; 194 PhysReg reg_v1{257}; 216 PhysReg reg_v1{257}; 220 Temp scc_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(s1, scc), Definition(s0_tmp.id(), PhysReg{0}, s1)); 247 PhysReg reg_v2{258}; 248 PhysReg reg_v [all...] |
| H A D | test_to_hw_instr.cpp | 29 PhysReg v0_lo{256}; 30 PhysReg v0_hi{256}; 31 PhysReg v0_b1{256}; 32 PhysReg v0_b3{256}; 33 PhysReg v1_lo{257}; 34 PhysReg v1_hi{257}; 35 PhysReg v1_b1{257}; 36 PhysReg v1_b3{257}; 37 PhysReg v2_lo{258}; 38 PhysReg v3_l [all...] |
| H A D | test_optimizer_postRA.cpp | 30 PhysReg reg_v0(256); 31 PhysReg reg_s0(0); 32 PhysReg reg_s2(2); 33 PhysReg reg_s4(4); 136 PhysReg reg_s0{0}; 137 PhysReg reg_s1{1}; 138 PhysReg reg_s2{2}; 139 PhysReg reg_s3{3}; 140 PhysReg reg_s4{4}; 141 PhysReg reg_s [all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_lower_to_hw_instr.cpp | 199 emit_int64_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, 200 PhysReg vtmp_reg, ReduceOp op, unsigned dpp_ctrl, unsigned row_mask, 204 Definition dst[] = {Definition(dst_reg, v1), Definition(PhysReg{dst_reg + 1}, v1)}; 205 Definition vtmp_def[] = {Definition(vtmp_reg, v1), Definition(PhysReg{vtmp_reg + 1}, v1)}; 206 Operand src0[] = {Operand(src0_reg, v1), Operand(PhysReg{src0_reg + 1}, v1)}; 207 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}; 209 Operand vtmp_op[] = {Operand(vtmp_reg, v1), Operand(PhysReg{vtmp_reg + 1}, v1)}; 299 emit_int64_op(lower_context* ctx, PhysReg dst_re [all...] |
| H A D | aco_ir.h | 428 * PhysReg 432 struct PhysReg { struct in namespace:aco 433 constexpr PhysReg() = default; 434 explicit constexpr PhysReg(unsigned r) : reg_b(r << 2) {} function in struct:aco::PhysReg 438 constexpr bool operator==(PhysReg other) const { return reg_b == other.reg_b; } 439 constexpr bool operator!=(PhysReg other) const { return reg_b != other.reg_b; } 440 constexpr bool operator<(PhysReg other) const { return reg_b < other.reg_b; } 441 constexpr PhysReg advance(int bytes) const 443 PhysReg res = *this; 452 static constexpr PhysReg m [all...] |
| H A D | aco_register_allocation.cpp | 46 void add_subdword_definition(Program* program, aco_ptr<Instruction>& instr, PhysReg reg); 49 PhysReg reg; 54 assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {} 102 PhysReg reg; 104 PhysReg operator*() const { return reg; } 127 PhysReg lo_; 131 PhysReg lo() const { return lo_; } 134 PhysReg hi() const { return PhysReg{lo() + size}; } 138 lo_ = PhysReg{lo [all...] |
| H A D | aco_insert_waitcnt.cpp | 191 std::map<PhysReg, wait_entry> gpr_map; 221 using iterator = std::map<PhysReg, wait_entry>::iterator; 239 void wait_and_remove_from_entry(PhysReg reg, wait_entry& entry, counter_type counter) 254 PhysReg reg{op.physReg() + j}; 255 std::map<PhysReg, wait_entry>::iterator it = ctx.gpr_map.find(reg); 266 PhysReg reg{def.physReg() + j}; 268 std::map<PhysReg, wait_entry>::iterator it = ctx.gpr_map.find(reg); 439 std::map<PhysReg, wait_entry>::iterator it = ctx.gpr_map.begin(); 524 for (std::pair<const PhysReg, wait_entry>& e : ctx.gpr_map) { 559 for (std::pair<PhysReg, wait_entr [all...] |
| H A D | aco_insert_NOPs.cpp | 201 regs_intersect(PhysReg a_reg, unsigned a_size, PhysReg b_reg, unsigned b_size) 208 handle_raw_hazard_instr(aco_ptr<Instruction>& pred, PhysReg reg, int* nops_needed, uint32_t* mask) 237 handle_raw_hazard_internal(State& state, Block* block, int nops_needed, PhysReg reg, uint32_t mask, 548 PhysReg wrdata = instr->operands[consider_flat ? 2 : 3].physReg();
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| H A D | aco_validate.cpp | 682 PhysReg reg; 956 PhysReg reg = assignments.at(tmp.id()).reg; 974 PhysReg reg = assignments.at(tmp.id()).reg; 1004 PhysReg reg = assignments.at(tmp.id()).reg; 1015 PhysReg reg = assignments.at(tmp.id()).reg; 1037 PhysReg reg = assignments.at(tmp.id()).reg;
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| H A D | aco_optimizer_postRA.cpp | 109 last_writer_idx(pr_opt_ctx& ctx, PhysReg physReg, RegClass rc) 143 is_clobbered_since(pr_opt_ctx& ctx, PhysReg reg, RegClass rc, const Idx& idx)
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| H A D | aco_assembler.cpp | 89 instr->operands[1].setFixed(PhysReg(255)); 675 instr->operands[0] = Operand(PhysReg{250}, v1); 696 instr->operands[0] = Operand(PhysReg{249}, v1); 899 instr->operands[1].setFixed(PhysReg{255}); /* this operand has to be a literal */
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| H A D | aco_instruction_selection.cpp | 11249 startpgm->definitions[arg].setFixed(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256}); 11267 def.setFixed(PhysReg(256 + ctx->args->ac.args[idx].offset)); 11789 bld.smem(aco_opcode::s_load_dwordx4, Definition(PhysReg{ttmp4}, s4), Operand(PhysReg{tma}, s2), 11793 bld.smem(aco_opcode::s_buffer_store_dwordx2, Operand(PhysReg{ttmp4}, s4), Operand::zero(), 11794 Operand(PhysReg{ttmp0}, s2), memory_sync_info(), true); 11806 bld.sopk(aco_opcode::s_getreg_b32, Definition(PhysReg{ttmp8}, s1), 11809 bld.smem(aco_opcode::s_buffer_store_dword, Operand(PhysReg{ttmp4}, s4), 11810 Operand::c32(8u + i * 4), Operand(PhysReg{ttmp8}, s1), memory_sync_info(), true); 11831 return Operand(PhysReg(fil [all...] |
| H A D | aco_print_ir.cpp | 104 print_physReg(PhysReg reg, unsigned bytes, FILE* output, unsigned flags)
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.1.0.rst | 1195 - aco: add comparison operators for PhysReg 3548 - aco: make PhysReg in units of bytes
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| H A D | 21.1.0.rst | 5441 - aco/ra: Use PhysReg for member functions of PhysRegInterval 5442 - aco/ra: Use PhysReg when indexing into RegisterFile's containers
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| H A D | 19.3.0.rst | 3300 - aco: Clean up usages of PhysReg::reg from aco_assembler.
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| H A D | 21.2.0.rst | 5005 - aco: Add Operand(Temp, PhysReg) constructor.
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