| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 168 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
189 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
219 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
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| H A D | r200_state_init.c | 65 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
507 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
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| H A D | r200_sanity.c | 68 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 155 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
179 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
209 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
|
| H A D | r200_state_init.c | 65 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
507 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
|
| H A D | r200_sanity.c | 68 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_ioctl.c | 102 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
113 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
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| H A D | radeon_blit.c | 135 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
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| H A D | radeon_sanity.c | 64 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
173 { RADEON_PP_CNTL, "RADEON_PP_CNTL" },
|
| H A D | radeon_state_init.c | 60 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
389 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_ioctl.c | 101 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
112 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
|
| H A D | radeon_blit.c | 126 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
|
| H A D | radeon_sanity.c | 64 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
173 { RADEON_PP_CNTL, "RADEON_PP_CNTL" },
|
| H A D | radeon_state_init.c | 59 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
388 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
|
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| H A D | radeon_render.c | 534 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
582 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
875 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
924 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
|
| H A D | radeon_textured_videofuncs.c | 222 OUT_ACCEL_REG(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE |
310 OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
723 OUT_ACCEL_REG(RADEON_PP_CNTL,
881 OUT_ACCEL_REG(RADEON_PP_CNTL,
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| H A D | radeon_exa_render.c | 691 OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl);
1065 OUT_ACCEL_REG(RADEON_PP_CNTL, pp_cntl);
|
| H A D | radeon_reg.h | 1738 #define RADEON_PP_CNTL 0x1c38 macro
|
| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| H A D | radeon_textured_videofuncs.c | 144 OUT_RING_REG(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE |
232 OUT_RING_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
550 OUT_RING_REG(RADEON_PP_CNTL,
708 OUT_RING_REG(RADEON_PP_CNTL,
|
| H A D | radeon_exa_render.c | 642 OUT_RING_REG(RADEON_PP_CNTL, pp_cntl);
1005 OUT_RING_REG(RADEON_PP_CNTL, pp_cntl);
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| H A D | radeon_reg.h | 1738 #define RADEON_PP_CNTL 0x1c38 macro
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/server/ |
| H A D | radeon_reg.h | 1141 #define RADEON_PP_CNTL 0x1c38 macro
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/server/ |
| H A D | radeon_reg.h | 1141 #define RADEON_PP_CNTL 0x1c38 macro
|