Searched refs:RADEON_PP_TEX_SIZE_0 (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c151 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) |
H A Dradeon_sanity.c136 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
245 { RADEON_PP_TEX_SIZE_0, "RADEON_PP_TEX_SIZE_0" },
248 { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" },
H A Dradeon_state_init.c135 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c142 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) |
H A Dradeon_sanity.c136 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
245 { RADEON_PP_TEX_SIZE_0, "RADEON_PP_TEX_SIZE_0" },
248 { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" },
H A Dradeon_state_init.c134 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_render.c482 OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, tex_size);
H A Dradeon_textured_videofuncs.c249 OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
333 OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
H A Dradeon_exa_render.c470 OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0,
H A Dradeon_reg.h1948 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
H A Dr200_sanity.c140 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
H A Dr200_state_init.c140 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/
H A Dr200_sanity.c140 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
H A Dr200_state_init.c140 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h1356 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/server/
H A Dradeon_reg.h1356 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dradeon_textured_videofuncs.c171 OUT_RING_REG(RADEON_PP_TEX_SIZE_0,
255 OUT_RING_REG(RADEON_PP_TEX_SIZE_0,
H A Dradeon_exa_render.c434 OUT_RING_REG(RADEON_PP_TEX_SIZE_0,
H A Dradeon_reg.h1948 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ macro

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