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    Searched refs:SavedReg (Results 1 - 25 of 79) sorted by relevancy

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  /xsrc/external/mit/xf86-video-intel-old/dist/src/sil164/
sil164.c 63 SIL164SaveRec SavedReg;
235 if (!sil164ReadByte(sil, SIL164_REG8, &sil->SavedReg.reg8))
238 if (!sil164ReadByte(sil, SIL164_REG9, &sil->SavedReg.reg9))
241 if (!sil164ReadByte(sil, SIL164_REGC, &sil->SavedReg.regc))
253 sil164WriteByte(sil, SIL164_REG8, sil->SavedReg.reg8 & ~0x1);
255 sil164WriteByte(sil, SIL164_REG9, sil->SavedReg.reg9);
256 sil164WriteByte(sil, SIL164_REGC, sil->SavedReg.regc);
257 sil164WriteByte(sil, SIL164_REG8, sil->SavedReg.reg8);
  /xsrc/external/mit/xf86-video-intel-old/dist/src/tfp410/
tfp410.c 62 TFP410SaveRec SavedReg;
264 if (!tfp410ReadByte(tfp, TFP410_CTL_1, &tfp->SavedReg.ctl1))
267 if (!tfp410ReadByte(tfp, TFP410_CTL_2, &tfp->SavedReg.ctl2))
277 tfp410WriteByte(tfp, TFP410_CTL_1, tfp->SavedReg.ctl1 & ~0x1);
279 tfp410WriteByte(tfp, TFP410_CTL_2, tfp->SavedReg.ctl2);
280 tfp410WriteByte(tfp, TFP410_CTL_1, tfp->SavedReg.ctl1);
  /xsrc/external/mit/xf86-video-cirrus/dist/src/
alp.h 57 AlpRegRec SavedReg;
lg.h 95 LgRegRec SavedReg;
lg_driver.c 1041 vgaHWSave(pScrn, &VGAHWPTR(pScrn)->SavedReg, VGA_SR_ALL);
1044 pCir->chip.lg->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1046 pCir->chip.lg->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1048 pCir->chip.lg->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1050 pCir->chip.lg->SavedReg.ExtVga[CR1E] = hwp->readCrtc(hwp, 0x1E);
1052 pCir->chip.lg->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1054 pCir->chip.lg->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1056 pCir->chip.lg->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1059 pCir->chip.lg->SavedReg.FORMAT = memrw(0xC0);
1062 pCir->chip.lg->SavedReg.VSC = memrl(0x3FC)
    [all...]
alp_driver.c 1133 vgaHWSave(pScrn, &VGAHWPTR(pScrn)->SavedReg, VGA_SR_ALL);
1135 pCir->chip.alp->ModeReg.ExtVga[CR1A] = pCir->chip.alp->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1136 pCir->chip.alp->ModeReg.ExtVga[CR1B] = pCir->chip.alp->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1137 pCir->chip.alp->ModeReg.ExtVga[CR1D] = pCir->chip.alp->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1138 pCir->chip.alp->ModeReg.ExtVga[SR07] = pCir->chip.alp->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1139 pCir->chip.alp->ModeReg.ExtVga[SR0E] = pCir->chip.alp->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1140 pCir->chip.alp->ModeReg.ExtVga[SR12] = pCir->chip.alp->SavedReg.ExtVga[SR12] = hwp->readSeq(hwp, 0x12);
1141 pCir->chip.alp->ModeReg.ExtVga[SR13] = pCir->chip.alp->SavedReg.ExtVga[SR13] = hwp->readSeq(hwp, 0x13);
1142 pCir->chip.alp->ModeReg.ExtVga[SR17] = pCir->chip.alp->SavedReg.ExtVga[SR17] = hwp->readSeq(hwp, 0x17);
1143 pCir->chip.alp->ModeReg.ExtVga[SR1E] = pCir->chip.alp->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E)
    [all...]
  /xsrc/external/mit/xf86-video-ati/dist/src/
legacy_crtc.c 724 save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1;
725 save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2;
726 save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1;
727 save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1;
903 /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/
926 save->disp_merge_cntl = info->SavedReg->disp_merge_cntl;
962 save->dac2_cntl = info->SavedReg->dac2_cntl;
963 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl;
964 save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl;
965 save->disp_hw_debug = info->SavedReg->disp_hw_debug
    [all...]
legacy_output.c 1118 uint32_t tmp = info->SavedReg->tmds_pll_cntl & 0xfffff;
1141 save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000;
1146 save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl &
1154 save->fp_gen_cntl = info->SavedReg->fp_gen_cntl |
1192 save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl &
1196 save->fp_2nd_gen_cntl = info->SavedReg->fp_2nd_gen_cntl;
1225 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl |
1228 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
1281 save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl |
1284 save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl
    [all...]
  /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ramdac/
xf86RamDac.h 25 RamDacRegRec SavedReg;
  /xsrc/external/mit/xf86-video-i740/dist/src/
i740.h 114 I740RegRec SavedReg;
  /xsrc/external/mit/xf86-video-chips/dist/src/
ct_driver.h 325 CHIPSRegRec SavedReg;
524 chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, \
525 &cPtr->SavedReg, TRUE); \
538 chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,\
  /xsrc/external/mit/xf86-video-nv/dist/src/
riva_type.h 53 RIVA_HW_STATE SavedReg;
nv_type.h 76 RIVA_HW_STATE SavedReg;
  /xsrc/external/mit/xf86-video-tseng/dist/src/
tseng.h 124 TsengRegRec SavedReg; /* saved Tseng registers at server start */
tseng_driver.c 252 pTseng->SavedReg.RAMDAC = NULL;
269 if (pTseng->SavedReg.RAMDAC)
270 free(pTseng->SavedReg.RAMDAC);
1520 TsengRestore(pScrn, &(VGAHWPTR(pScrn)->SavedReg),
1521 &pTseng->SavedReg,VGA_SR_ALL);
1536 TsengRestore(pScrn, &(VGAHWPTR(pScrn)->SavedReg),
1537 &(pTseng->SavedReg),VGA_SR_ALL);
  /xsrc/external/mit/xf86-video-r128/dist/src/
r128_output.c 130 R128InitRMXRegisters(&info->SavedReg, &info->ModeReg, output, adjusted_mode);
133 R128InitFPRegisters(&info->SavedReg, &info->ModeReg, output);
135 R128InitLVDSRegisters(&info->SavedReg, &info->ModeReg, output);
137 R128InitDACRegisters(&info->SavedReg, &info->ModeReg, output);
r128_crtc.c 908 info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
909 info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
910 info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
911 info->ModeReg.dda_config = info->SavedReg.dda_config;
912 info->ModeReg.dda_on_off = info->SavedReg.dda_on_off;
  /xsrc/external/mit/xf86-video-apm/dist/src/
apm_driver.c 1166 ApmRegPtr ApmReg = &pApm->SavedReg;
1176 if (!(hwp->SavedReg.Attribute[0x10] & 1)) {
1194 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_CMAP);
1223 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL);
1406 memcpy(ApmReg, &pApm->SavedReg, sizeof pApm->SavedReg);
1987 ApmRestore(pScrn, &hwp->SavedReg, &pApm->SavedReg);
2020 ApmRestore(pScrn, &hwp->SavedReg, &pApm->SavedReg);
    [all...]
apm.h 116 ApmRegStr ModeReg, SavedReg;
  /xsrc/external/mit/xf86-video-ast/dist/src/
ast_2dtool.c 293 if (pAST->SavedReg.REGA4 & 0x01) /* 2D enabled */
296 *(ULONG *) (pAST->MMIOVirtualAddr + 0x8044) = pAST->SavedReg.ENG8044;
  /xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
i810.h 204 I810RegRec SavedReg;
  /xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
i810.h 204 I810RegRec SavedReg;
  /xsrc/external/mit/xf86-video-intel-old/dist/src/
i810.h 218 I810RegRec SavedReg;
  /xsrc/external/mit/xf86-video-s3virge/dist/src/
s3v.h 182 S3VRegRec SavedReg;
  /xsrc/external/mit/xf86-video-tga/dist/src/
tga.h 77 TGARegRec SavedReg;

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