Searched refs:TC (Results 1 - 25 of 26) sorted by relevance

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/xsrc/external/mit/mesa-demos/dist/src/tests/
H A Dtexcmp.c26 GLenum TC; member in struct:__anona6e4c3ee0108
37 static const char *TextureName (GLenum TC) argument
39 switch (TC) {
128 PrintString(TextureName(Tx->TC));
155 static void ReInit( GLenum TC, TEXTURE *Tx ) argument
159 if ((Tx->TC == TC) && (Tx->cData != NULL)) {
171 TC, /* internal format */
182 printf("Requested internal format = 0x%x, actual = 0x%x\n", TC, v);
197 Tx->TC
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/xsrc/external/mit/libXTrap/dist/src/
H A DXEConTxt.c52 static XETC TC; variable in typeref:typename:XETC
63 register XETC *tc = &TC;
67 /* If this is the first time here, then initialize the default TC */
71 /* The first Trap Context is the Template (default) TC */
84 { /* No memory to build TC, XtMalloc has already reported the error */
88 /* Use the original TC as the template to start from */
89 (void)memcpy(tc,&TC,sizeof(TC));
110 { /* No memory to build TC, XtMalloc has already reported the error */
111 (void)XtFree((XtPointer)tc); /* free the allocated TC */
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/xsrc/external/mit/fontconfig/dist/conf.d/
H A D65-nonlatin.conf38 <family>Songti TC</family> <!-- han (zh-tw) - macOS -->
113 <family>PingFang TC</family> <!-- han (zh-tw) - macOS -->
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D13.0.3.rst108 - radeonsi: apply a TC L1 write corruption workaround for SI
H A D18.1.3.rst126 - radv: update the ZRANGE_PRECISION value for the TC-compat bug
H A D18.2.7.rst121 - radv: rework the TC-compat HTILE hardware bug with COND_EXEC
H A D20.3.3.rst127 - radv: disable TC-compat HTILE in GENERAL for Detroit: Become Human
H A D21.1.6.rst144 - radv: only init the TC-compat ZRANGE metadata for the depth aspect
H A D17.1.6.rst75 - radv/ac: port SI TC L1 write corruption fix.
H A D21.1.1.rst200 - radv: fix missing ITERATE_256 for D/S MSAA images that are TC-compat HTILE
H A D21.1.0.rst3608 - radeonsi: parallelize Z/S conversion into TC-compatible with fast color clears
3611 - radeonsi: indent the code for TC-compatibility HTILE transition
3614 - radeonsi: when transitioning to TC-compat HTILE, try to do a proper clear
5039 - radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+
5040 - radv: enable TC-compat HTILE for D16S8 on GFX9+
5073 - radv: enable TC-compat HTILE for mipmaps on GFX10+
5074 - radv: re-disable TC-compat HTILE for D32S8 on all generations
5146 - radv: fix RGP barrier layout transition for TC-compatible CMASK images
5148 - radv: cleanup enabling TC-compat HTILE for depth surfaces
5149 - radv: remove useless check about mips+layers for TC
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H A D12.0.2.rst323 - radeonsi: flush TC L2 cache for indirect draw data
H A D21.0.0.rst3028 - radv: enable TC-compat HTILE for D32_SFLOAT+MSAA on GFX10+
3032 - radv: ignore the mutable bit for TC-compatible HTILE
3046 - radv: fix potential HTILE issues for TC-compat images on GFX8
3048 - radv: fix TC-compat HTILE images with DST_OPTIMAL on the compute queue
3051 - radv: enable TC-compat HTILE in GENERAL on GFX10+
3054 - radv: configure the texture descriptor for TC-compat CMASK on GFX10+
3055 - radv: fix enabling TC-compat HTILE in GENERAL for writes on GFX10+
3056 - radv: fix performance regression by restoring TC-compat HTILE in GENERAL
3061 - radv: disable TC-compat HTILE in GENERAL for Detroit: Become Human
H A D21.2.0.rst2484 - r600/sfn: force new CF if fetch through TC would be used in same clause
4506 - freedreno: Allow resource shadowing for TC
4516 - freedreno: last_fence optimization for TC async flushes
4539 - freedreno: Fix TC last_fence optimization
4558 - freedreno: Implement TC resource_busy
4745 - radv: enable TC-compat CMASK on GFX8-9
4748 - radv: only keep concurrent MSAA images compressed if TC-compat CMASK
4755 - radv: fix missing ITERATE_256 for D/S MSAA images that are TC-compat HTILE
4831 - radv: allow more fast clears for depth surfaces without TC-compat HTILE
4842 - radv: only init the TC
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H A D21.3.0.rst1397 - freedreno: Use TC's flag for whether get_query is in the driver thread.
2580 - gallium/noop: enable threaded_context to test TC overhead without a driver
3705 - freedreno: Disable TC syncs for get_device_reset_status()
3706 - zink: Disable TC syncs for get_device_reset_status()
3773 - radv: only init the TC-compat ZRANGE metadata for the depth aspect
H A D20.1.0.rst140 - radv: Enable TC-compat HTILE in VK_IMAGE_LAYOUT_GENERAL.
3962 - radv: only enable TC-compat HTILE for images readable by a shader
3963 - radv: allow TC-compat HTILE with GENERAL outside of render loops
H A D20.2.0.rst3210 - radeonsi: enable TC-compatible HTILE on demand for best Z/S performance
3251 - radeonsi: don't enable TC-compatible HTILE for stencil if stencil doesn't use it
3252 - radeonsi/gfx8: enable TC-compatible HTILE from the beginning as before
H A D19.0.0.rst2263 - radv: rework the TC-compat HTILE hardware bug with COND_EXEC
H A D19.3.0.rst3050 - radv: add mipmap support for the TC-compat zrange bug
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_formats.c168 F3(A, L8_SNORM, R8_SNORM, R, R, R, xx, SNORM, R8, TC),
171 F3(A, L16_UNORM, R16_UNORM, R, R, R, xx, UNORM, R16, TC),
172 F3(A, L16_SNORM, R16_SNORM, R, R, R, xx, SNORM, R16, TC),
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_formats.c168 F3(A, L8_SNORM, R8_SNORM, R, R, R, xx, SNORM, R8, TC),
171 F3(A, L16_UNORM, R16_UNORM, R, R, R, xx, UNORM, R16, TC),
172 F3(A, L16_SNORM, R16_SNORM, R, R, R, xx, SNORM, R16, TC),
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ddc/
H A Dedid.h637 Uchar TC:1; member in struct:cea_speaker_block
/xsrc/external/mit/xorg-server/dist/hw/xfree86/ddc/
H A Dedid.h646 Uchar TC:1; member in struct:cea_speaker_block
/xsrc/external/mit/MesaLib/dist/docs/
H A Denvvars.rst665 disable TC-compat CMASK for MSAA surfaces
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json319 "description": "radeonsi: fix the unaligned clear_buffer fallback with TC",
4567 "description": "d3d12: Use CPU storage in TC for buffers",
28192 "description": "radv: allow TC-compat CMASK with storage images on GFX10+",
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