Searched refs:VB0_BUFFER_INDEX_SHIFT (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_reg.h342 #define VB0_BUFFER_INDEX_SHIFT 27 macro
H A Di965_video.c1312 OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
H A Di965_render.c2202 OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) |
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h315 #define VB0_BUFFER_INDEX_SHIFT 27 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_reg.h342 #define VB0_BUFFER_INDEX_SHIFT 27 macro
H A Di965_video.c1313 OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
H A Di965_render.c2202 OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) |
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h315 #define VB0_BUFFER_INDEX_SHIFT 27 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen6_render.h140 #define VB0_BUFFER_INDEX_SHIFT 26 macro
H A Dgen4_render.h122 #define VB0_BUFFER_INDEX_SHIFT 27 macro
H A Dgen5_render.h205 #define VB0_BUFFER_INDEX_SHIFT 27 macro
H A Dgen4_render.c600 OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) | VB0_VERTEXDATA |
H A Dgen5_render.c586 OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
H A Dgen6_render.c1173 OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen6_render.h140 #define VB0_BUFFER_INDEX_SHIFT 26 macro
H A Dgen4_render.h122 #define VB0_BUFFER_INDEX_SHIFT 27 macro
H A Dgen5_render.h205 #define VB0_BUFFER_INDEX_SHIFT 27 macro
H A Dgen4_render.c563 OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) | VB0_VERTEXDATA |
H A Dgen5_render.c549 OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
H A Dgen6_render.c1139 OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_video.c1221 OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
H A Di810_reg.h2661 #define VB0_BUFFER_INDEX_SHIFT 27 macro
H A Di965_render.c1769 OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |

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