Searched refs:VE1_DESTINATION_ELEMENT_OFFSET_SHIFT (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_reg.h361 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
H A Di965_render.c1509 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1525 ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1542 ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
H A Di965_video.c1057 VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1070 VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h334 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_reg.h361 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
H A Di965_render.c1509 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1525 ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1542 ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
H A Di965_video.c1058 VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1071 VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h334 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_video.c948 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
958 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
H A Di965_render.c1366 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1383 ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1401 ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
H A Di810_reg.h2675 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen4_render.c1031 (1*4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
1068 OUT_BATCH(dw | 8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
1101 OUT_BATCH(dw | 12 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
1110 12 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
H A Dgen6_render.h154 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
H A Dgen4_render.h136 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
H A Dgen5_render.h224 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen4_render.c994 (1*4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
1031 OUT_BATCH(dw | 8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
1064 OUT_BATCH(dw | 12 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
1073 12 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
H A Dgen6_render.h154 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
H A Dgen4_render.h136 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro
H A Dgen5_render.h224 #define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 macro

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