| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a4xx/ |
| fd4_program.c | 130 VS = 0,
143 s[VS].v = fd4_emit_get_vp(emit);
155 * care about instruction group size of a3xx vs a4xx
165 /* NOTE: at least for gles2, blob partitions VS at bottom of const
170 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
173 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
176 /* if FS can fit, kick VS out to external memory: */
177 s[VS].instrlen = 0;
178 } else if (s[VS].instrlen < 64) {
179 /* otherwise if VS can fit, kick out FS: *
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/ |
| fd5_program.c | 164 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
171 s[VS].v = fd5_emit_get_vp(emit);
184 * care about instruction group size of a3xx vs a5xx
194 /* NOTE: at least for gles2, blob partitions VS at bottom of const
199 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
202 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
205 /* if FS can fit, kick VS out to external memory: */
206 s[VS].instrlen = 0;
207 } else if (s[VS].instrlen < 64) {
208 /* otherwise if VS can fit, kick out FS: *
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/ |
| fd5_program.c | 250 VS = 0,
263 s[VS].v = fd5_emit_get_vp(emit);
275 * care about instruction group size of a3xx vs a5xx
285 /* NOTE: at least for gles2, blob partitions VS at bottom of const
290 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
293 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
296 /* if FS can fit, kick VS out to external memory: */
297 s[VS].instrlen = 0;
298 } else if (s[VS].instrlen < 64) {
299 /* otherwise if VS can fit, kick out FS: *
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a4xx/ |
| fd4_program.c | 91 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
98 s[VS].v = fd4_emit_get_vp(emit);
111 * care about instruction group size of a3xx vs a4xx
121 /* NOTE: at least for gles2, blob partitions VS at bottom of const
126 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
129 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
132 /* if FS can fit, kick VS out to external memory: */
133 s[VS].instrlen = 0;
134 } else if (s[VS].instrlen < 64) {
135 /* otherwise if VS can fit, kick out FS: *
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| brw_urb.c | 39 #define VS 0
72 * For VS, the number of entries may be 8, 12, 16, or 32 (or 64 on G4X).
83 * XXX: Verify min_nr_entries, esp for VS.
92 { 16, 32, 1, 5 }, /* vs */
124 if (vsize < limits[VS].min_entry_size)
125 vsize = limits[VS].min_entry_size;
142 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
157 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
166 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
171 brw->urb.nr_vs_entries = limits[VS].min_nr_entries
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| brw_urb.c | 39 #define VS 0
72 * For VS, the number of entries may be 8, 12, 16, or 32 (or 64 on G4X).
83 * XXX: Verify min_nr_entries, esp for VS.
92 { 16, 32, 1, 5 }, /* vs */
124 if (vsize < limits[VS].min_entry_size)
125 vsize = limits[VS].min_entry_size;
142 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
157 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
166 brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
171 brw->urb.nr_vs_entries = limits[VS].min_nr_entries
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_program.c | 248 VS = 0,
264 s[VS].v = state->bs;
267 s[VS].v = state->vs;
279 * care about instruction group size of a3xx vs a5xx
322 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
323 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
324 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
325 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
361 * emitted if frag-prog is dirty vs if vert-prog is dirty.
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| aco_instruction_selection_setup.cpp | 260 * When there are no param exports in an NGG (or legacy VS) shader,
263 * before the NGG (or VS) waves finish.
272 setup_vs_output_info(ctx, nir, &ctx->program->info->vs.outinfo);
294 setup_vs_output_info(ctx, nir, &ctx->program->info->vs.outinfo);
302 setup_tcs_info(isel_context* ctx, nir_shader* nir, nir_shader* vs)
304 ctx->tcs_in_out_eq = ctx->args->shader_info->vs.tcs_in_out_eq;
305 ctx->tcs_temp_only_inputs = ctx->args->shader_info->vs.tcs_temp_only_input_mask;
403 unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[i];
827 case MESA_SHADER_VERTEX: sw_stage = sw_stage | SWStage::VS; break;
841 if (sw_stage == SWStage::VS && args->shader_info->vs.as_es && !ngg
[all...] |
| aco_ir.h | 268 uint8_t vs; member in struct:aco::wait_imm
1909 VS = 1 << 0, /* Vertex Shader */
1918 VS_GS = VS | GS,
1919 VS_TCS = VS | TCS,
1937 VS,
1938 ES, /* Export shader: pre-GS (VS or TES) on GFX6-8. Combined into GS on GFX9 (and GFX10/legacy). */
1940 NGG, /* Primitive shader, used to implement VS, TES, GS. */
1941 LS, /* Local shader: pre-TCS (VS) on GFX6-8. Combined into HS on GFX9 (and GFX10/legacy). */
1942 HS, /* Hull shader: TCS on GFX6-8. Merged VS and TCS on GFX9-10. */
1976 static constexpr Stage vertex_vs(HWStage::VS, SWStage::VS)
[all...] |
| aco_assembler.cpp | 779 if (program->stage.hw == HWStage::VS || program->stage.hw == HWStage::NGG) {
800 (program->stage.hw == HWStage::VS || program->stage.hw == HWStage::NGG);
971 if (program->stage.hw == HWStage::VS || program->stage.hw == HWStage::FS ||
|
| aco_statistics.cpp | 72 std::deque<int32_t> vs; member in class:aco::BlockCycleEstimator
88 : vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_)
94 unsigned vs; member in struct:aco::wait_counter_info
278 imm.vs = wait_info.vs ? max_vs_cnt : wait_imm::unset_counter;
301 if (imm.vs != wait_imm::unset_counter) {
302 for (int i = 0; i < (int)vs.size() - imm.vs; i++)
303 deps_available = MAX2(deps_available, vs[i]);
379 while (vs.size() > imm.vs
[all...] |
| aco_insert_waitcnt.cpp | 162 imm.vs = wait_imm::unset_counter;
295 imm.vs = std::min<uint8_t>(imm.vs, instr->sopk().imm);
344 imm.vs = 0;
391 imm.vs = 0;
412 ctx.vs_cnt = std::min(ctx.vs_cnt, imm.vs);
430 if (bar.vs != wait_imm::unset_counter && imm.vs <= bar.vs) {
431 bar.vs = wait_imm::unset_counter
[all...] |
| aco_instruction_selection.cpp | 4697 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations
4739 /* For NGG VS and TES shaders the primitive ID is exported manually after the other exports so we
4742 (ctx->stage.has(SWStage::VS) || ctx->stage.has(SWStage::TES)) &&
5003 if (ctx->shader->info.stage == MESA_SHADER_VERTEX && ctx->args->shader_info->vs.dynamic_inputs) {
5044 unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
5045 uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
5046 uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
5047 unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
5048 unsigned binding_align = ctx->options->key.vs.vertex_binding_align[attrib_binding];
5050 ctx->options->key.vs.vertex_alpha_adjust[location]
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/d3d12/ |
| d3d12_pipeline_state.cpp | 202 pso_desc.VS.BytecodeLength = shader->bytecode_length;
203 pso_desc.VS.pShaderBytecode = shader->bytecode;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| si_pipe.c | 47 { "vs", DBG(VS), "Print vertex shaders" },
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_pipe.c | 53 {"vs", DBG(VS), "Print vertex shaders"},
743 * This also enables jumping over the VS prolog for HS-only waves.
752 /* This enables jumping over the VS prolog for GS-only waves. */
|
| /xsrc/external/mit/MesaLib/src/intel/genxml/ |
| gen10_pack.h | 5562 #define VS 0
|
| gen11_pack.h | 6123 #define VS 0
|
| gen9_pack.h | 5520 #define VS 0
|
| gen125_pack.h | 6450 #define VS 0
|
| gen12_pack.h | 6405 #define VS 0
|
| /xsrc/external/mit/MesaLib.old/src/intel/genxml/ |
| gen10_pack.h | 5562 #define VS 0
|
| gen11_pack.h | 5677 #define VS 0
|
| gen9_pack.h | 5504 #define VS 0
|
