| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| ac_rgp.h | 57 uint64_t base_address; member in struct:rgp_shader_data
86 uint64_t base_address; member in struct:rgp_loader_events_record
|
| ac_sqtt.c | 128 uint64_t base_address)
139 record->base_address = base_address & 0xffffffffffff;
|
| ac_rgp_elf_object_pack.c | 199 uint64_t base_address = -1; local
211 if (base_address > record->shader_data[i].base_address) {
213 base_address = record->shader_data[i].base_address;
238 uint32_t code_offset = rgp_shader_data->base_address -
239 prev_rgp_shader_data->base_address;
|
| ac_sqtt.h | 494 uint64_t base_address);
|
| ac_rgp.c | 647 uint64_t base_address; member in struct:sqtt_code_object_loader_events_record
|
| /xsrc/external/mit/xf86-video-intel/dist/xvmc/ |
| i915_xvmc.c | 410 buffer_info->dest_y.dw2.base_address = intel_surf->bo->offset >> 2; /* starting DWORD address */
427 buffer_info->dest_u.dw2.base_address =
445 buffer_info->dest_v.dw2.base_address =
515 buffer_info->corr.dw2.base_address = pI915XvMC->corrdata_bo->offset >> 2; /* starting DWORD address */
558 map_state->y_forward.tm0.base_address = privPast->bo->offset >> 2;
578 map_state->y_backward.tm0.base_address = privFuture->bo->offset >> 2;
605 map_state->u_forward.tm0.base_address =
626 map_state->u_backward.tm0.base_address =
654 map_state->v_forward.tm0.base_address =
675 map_state->v_backward.tm0.base_address
[all...] |
| i915_structs.h | 246 unsigned base_address:27; member in struct:i915_3dstate_buffer_info::__anon7842
376 unsigned base_address:27; member in struct:texture_map::__anon7848
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/ |
| i915_xvmc.c | 410 buffer_info->dest_y.dw2.base_address = intel_surf->bo->offset >> 2; /* starting DWORD address */
427 buffer_info->dest_u.dw2.base_address =
445 buffer_info->dest_v.dw2.base_address =
515 buffer_info->corr.dw2.base_address = pI915XvMC->corrdata_bo->offset >> 2; /* starting DWORD address */
558 map_state->y_forward.tm0.base_address = privPast->bo->offset >> 2;
578 map_state->y_backward.tm0.base_address = privFuture->bo->offset >> 2;
605 map_state->u_forward.tm0.base_address =
626 map_state->u_backward.tm0.base_address =
654 map_state->v_forward.tm0.base_address =
675 map_state->v_backward.tm0.base_address
[all...] |
| i915_structs.h | 246 unsigned base_address:27; member in struct:i915_3dstate_buffer_info::__anon8691
376 unsigned base_address:27; member in struct:texture_map::__anon8697
|
| /xsrc/external/mit/MesaLib/dist/src/intel/common/ |
| intel_decoder.h | 236 uint64_t base_address);
|
| intel_batch_decoder.c | 114 uint64_t base_address,
121 size = ctx->get_state_size(ctx->user_data, address, base_address);
|
| /xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/ |
| i915_xvmc.c | 524 buffer_info->corr.dw2.base_address = (pI915XvMC->corrdata.offset >> 2); /* starting DWORD address */
537 buffer_info->dest_y.dw2.base_address = (YOFFSET(pI915Surface) >> 2); /* starting DWORD address */
539 buffer_info->dest_u.dw2.base_address = (UOFFSET(pI915Surface) >> 2); /* starting DWORD address */
541 buffer_info->dest_v.dw2.base_address = (VOFFSET(pI915Surface) >> 2); /* starting DWORD address */
696 map_state->y_forward.tm0.base_address = (YOFFSET(privPast) >> 2);
698 map_state->y_backward.tm0.base_address = (YOFFSET(privFuture) >> 2);
700 map_state->u_forward.tm0.base_address = (UOFFSET(privPast) >> 2);
702 map_state->u_backward.tm0.base_address = (UOFFSET(privFuture) >> 2);
704 map_state->v_forward.tm0.base_address = (VOFFSET(privPast) >> 2);
706 map_state->v_backward.tm0.base_address = (VOFFSET(privFuture) >> 2)
[all...] |
| i915_structs.h | 274 unsigned base_address : 27; member in struct:i915_3dstate_buffer_info::__anon8936
408 unsigned base_address : 27; member in struct:texture_map::__anon8942
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_sqtt.c | 1014 record->shader_data[gl_shader_stage].base_address = va & 0xffffffffffff;
1034 si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute)
1044 result = ac_sqtt_add_code_object_loader_event(thread_trace_data, pipeline_hash, base_address);
|
| si_state_draw.cpp | 285 uint64_t base_address = ~0; local
294 base_address = MIN2(base_address,
301 si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address, false);
|
| si_compute.c | 316 uint64_t base_address = program->shader.bo->gpu_address; local
320 si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address, true);
|
| si_pipe.h | 1556 bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute);
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/ |
| crocus_batch.c | 149 uint64_t base_address)
162 _mesa_hash_table_u64_search(batch->state_sizes, address - base_address);
|
| /xsrc/external/mit/libXmu/dist/src/ |
| EditresCom.c | 124 unsigned long base_address; member in struct:_Globals
503 globals.base_address = (unsigned long)w & 0xFFFFFFFF00000000;
1963 info->ids[i] |= globals.base_address;
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| brw_batch.c | 115 decode_get_state_size(void *v_brw, uint64_t address, uint64_t base_address)
121 address - base_address);
|
| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| anv_allocator.c | 834 uint64_t base_address,
842 base_address + start_offset,
|
| genX_cmd_buffer.c | 507 uint64_t base_address = local
568 uint64_t address = base_address + offset;
|
| anv_private.h | 729 uint64_t base_address,
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/ |
| iris_batch.c | 152 UNUSED uint64_t base_address)
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/layers/ |
| radv_sqtt_layer.c | 888 record->shader_data[i].base_address = va & 0xffffffffffff;
|
