Searched refs:bits (Results 1 - 25 of 1378) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/registers/
H A D	registers-manually-defined.json	51 {"bits": [0, 11], "name": "MAX_WAVE_ID"} array in object:register_types.SPI_PS_MAX_WAVE_ID.fields.0 56 {"bits": [1, 1], "name": "UVD_RQ_PENDING"}, array in object:register_types.SRBM_STATUS.fields.0 57 {"bits": [2, 2], "name": "SAMMSP_RQ_PENDING"}, array in object:register_types.SRBM_STATUS.fields.1 58 {"bits": [3, 3], "name": "ACP_RQ_PENDING"}, array in object:register_types.SRBM_STATUS.fields.2 59 {"bits": [4, 4], "name": "SMU_RQ_PENDING"}, array in object:register_types.SRBM_STATUS.fields.3 60 {"bits": [5, 5], "name": "GRBM_RQ_PENDING"}, array in object:register_types.SRBM_STATUS.fields.4 61 {"bits": [6, 6], "name": "HI_RQ_PENDING"}, array in object:register_types.SRBM_STATUS.fields.5 62 {"bits": [8, 8], "name": "VMC_BUSY"}, array in object:register_types.SRBM_STATUS.fields.6 63 {"bits": [9, 9], "name": "MCB_BUSY"}, array in object:register_types.SRBM_STATUS.fields.7 64 {"bits" array in object:register_types.SRBM_STATUS.fields.8 65 {"bits": [11, 11], "name": "MCC_BUSY"}, array in object:register_types.SRBM_STATUS.fields.9 66 {"bits": [12, 12], "name": "MCD_BUSY"}, array in object:register_types.SRBM_STATUS.fields.10 67 {"bits": [13, 13], "name": "VMC1_BUSY"}, array in object:register_types.SRBM_STATUS.fields.11 68 {"bits": [14, 14], "name": "SEM_BUSY"}, array in object:register_types.SRBM_STATUS.fields.12 69 {"bits": [16, 16], "name": "ACP_BUSY"}, array in object:register_types.SRBM_STATUS.fields.13 70 {"bits": [17, 17], "name": "IH_BUSY"}, array in object:register_types.SRBM_STATUS.fields.14 71 {"bits": [19, 19], "name": "UVD_BUSY"}, array in object:register_types.SRBM_STATUS.fields.15 72 {"bits": [20, 20], "name": "SAMMSP_BUSY"}, array in object:register_types.SRBM_STATUS.fields.16 73 {"bits": [21, 21], "name": "GCATCL2_BUSY"}, array in object:register_types.SRBM_STATUS.fields.17 74 {"bits": [22, 22], "name": "OSATCL2_BUSY"}, array in object:register_types.SRBM_STATUS.fields.18 75 {"bits": [29, 29], "name": "BIF_BUSY"} array in object:register_types.SRBM_STATUS.fields.19 80 {"bits": [0, 0], "name": "IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.0 81 {"bits": [1, 1], "name": "REG_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.1 82 {"bits": [2, 2], "name": "RB_EMPTY"}, array in object:register_types.SDMA0_STATUS_REG.fields.2 83 {"bits": [3, 3], "name": "RB_FULL"}, array in object:register_types.SDMA0_STATUS_REG.fields.3 84 {"bits": [4, 4], "name": "RB_CMD_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.4 85 {"bits": [5, 5], "name": "RB_CMD_FULL"}, array in object:register_types.SDMA0_STATUS_REG.fields.5 86 {"bits": [6, 6], "name": "IB_CMD_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.6 87 {"bits": [7, 7], "name": "IB_CMD_FULL"}, array in object:register_types.SDMA0_STATUS_REG.fields.7 88 {"bits": [8, 8], "name": "BLOCK_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.8 89 {"bits": [9, 9], "name": "INSIDE_IB"}, array in object:register_types.SDMA0_STATUS_REG.fields.9 90 {"bits": [10, 10], "name": "EX_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.10 91 {"bits": [11, 11], "name": "EX_IDLE_POLL_TIMER_EXPIRE"}, array in object:register_types.SDMA0_STATUS_REG.fields.11 92 {"bits": [12, 12], "name": "PACKET_READY"}, array in object:register_types.SDMA0_STATUS_REG.fields.12 93 {"bits": [13, 13], "name": "MC_WR_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.13 94 {"bits": [14, 14], "name": "SRBM_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.14 95 {"bits": [15, 15], "name": "CONTEXT_EMPTY"}, array in object:register_types.SDMA0_STATUS_REG.fields.15 96 {"bits": [16, 16], "name": "DELTA_RPTR_FULL"}, array in object:register_types.SDMA0_STATUS_REG.fields.16 97 {"bits": [17, 17], "name": "RB_MC_RREQ_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.17 98 {"bits": [18, 18], "name": "IB_MC_RREQ_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.18 99 {"bits": [19, 19], "name": "MC_RD_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.19 100 {"bits": [20, 20], "name": "DELTA_RPTR_EMPTY"}, array in object:register_types.SDMA0_STATUS_REG.fields.20 101 {"bits": [21, 21], "name": "MC_RD_RET_STALL"}, array in object:register_types.SDMA0_STATUS_REG.fields.21 102 {"bits": [22, 22], "name": "MC_RD_NO_POLL_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.22 103 {"bits": [25, 25], "name": "PREV_CMD_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.23 104 {"bits": [26, 26], "name": "SEM_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.24 105 {"bits": [27, 27], "name": "SEM_REQ_STALL"}, array in object:register_types.SDMA0_STATUS_REG.fields.25 106 {"bits": [28, 29], "name": "SEM_RESP_STATE"}, array in object:register_types.SDMA0_STATUS_REG.fields.26 107 {"bits": [30, 30], "name": "INT_IDLE"}, array in object:register_types.SDMA0_STATUS_REG.fields.27 108 {"bits": [31, 31], "name": "INT_REQ_STALL"} array in object:register_types.SDMA0_STATUS_REG.fields.28 113 {"bits": [0, 0], "name": "SDMA_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.0 114 {"bits": [1, 1], "name": "TST_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.1 115 {"bits": [2, 2], "name": "SDMA1_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.2 116 {"bits": [3, 3], "name": "VCE0_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.3 117 {"bits": [4, 4], "name": "VP8_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.4 118 {"bits": [5, 5], "name": "SDMA_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.5 119 {"bits": [6, 6], "name": "SDMA1_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.6 120 {"bits": [7, 7], "name": "VCE0_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.7 121 {"bits": [8, 8], "name": "XDMA_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.8 122 {"bits": [9, 9], "name": "CHUB_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.9 123 {"bits": [10, 10], "name": "SDMA2_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.10 124 {"bits": [11, 11], "name": "SDMA3_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.11 125 {"bits": [12, 12], "name": "SAMSCP_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.12 126 {"bits": [13, 13], "name": "ISP_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.13 127 {"bits": [14, 14], "name": "VCE1_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.14 128 {"bits": [15, 15], "name": "ODE_BUSY"}, array in object:register_types.SRBM_STATUS2.fields.15 129 {"bits": [16, 16], "name": "SDMA2_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.16 130 {"bits": [17, 17], "name": "SDMA3_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.17 131 {"bits": [18, 18], "name": "SAMSCP_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.18 132 {"bits": [19, 19], "name": "ISP_RQ_PENDING"}, array in object:register_types.SRBM_STATUS2.fields.19 133 {"bits": [20, 20], "name": "VCE1_RQ_PENDING"} array in object:register_types.SRBM_STATUS2.fields.20 138 {"bits": [0, 0], "name": "MCC0_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.0 139 {"bits": [1, 1], "name": "MCC1_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.1 140 {"bits": [2, 2], "name": "MCC2_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.2 141 {"bits": [3, 3], "name": "MCC3_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.3 142 {"bits": [4, 4], "name": "MCC4_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.4 143 {"bits": [5, 5], "name": "MCC5_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.5 144 {"bits": [6, 6], "name": "MCC6_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.6 145 {"bits": [7, 7], "name": "MCC7_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.7 146 {"bits": [8, 8], "name": "MCD0_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.8 147 {"bits": [9, 9], "name": "MCD1_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.9 148 {"bits": [10, 10], "name": "MCD2_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.10 149 {"bits": [11, 11], "name": "MCD3_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.11 150 {"bits": [12, 12], "name": "MCD4_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.12 151 {"bits": [13, 13], "name": "MCD5_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.13 152 {"bits": [14, 14], "name": "MCD6_BUSY"}, array in object:register_types.SRBM_STATUS3.fields.14 153 {"bits": [15, 15], "name": "MCD7_BUSY"} array in object:register_types.SRBM_STATUS3.fields.15 158 {"bits": [0, 1], "name": "RATE_X"}, array in object:register_types.GE_VRS_RATE.fields.0 159 {"bits": [4, 5], "name": "RATE_Y"} array in object:register_types.GE_VRS_RATE.fields.1 [all...]
H A D	gfx10-rsrc.json	323 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.0 324 {"bits": [16, 29], "name": "STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.1 325 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.2 326 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} array in object:register_types.SQ_BUF_RSRC_WORD1.fields.3 331 {"bits": [0, 2], "name": "DST_SEL_X"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.0 332 {"bits": [3, 5], "name": "DST_SEL_Y"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.1 333 {"bits": [6, 8], "name": "DST_SEL_Z"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.2 334 {"bits": [9, 11], "name": "DST_SEL_W"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.3 335 {"bits": [12, 18], "enum_ref": "GFX10_FORMAT", "name": "FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.4 336 {"bits" array in object:register_types.SQ_BUF_RSRC_WORD3.fields.5 337 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.6 338 {"bits": [24, 24], "comment": "must be 1", "name": "RESOURCE_LEVEL"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.7 339 {"bits": [28, 29], "enum_ref": "SQ_BUF_RSRC_WORD3__OOB_SELECT", "name": "OOB_SELECT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.8 340 {"bits": [30, 31], "comment": "must be 0", "name": "TYPE"} array in object:register_types.SQ_BUF_RSRC_WORD3.fields.9 345 {"bits": [0, 2], "name": "DST_SEL_X"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.0 346 {"bits": [3, 5], "name": "DST_SEL_Y"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.1 347 {"bits": [6, 8], "name": "DST_SEL_Z"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.2 348 {"bits": [9, 11], "name": "DST_SEL_W"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.3 349 {"bits": [12, 18], "enum_ref": "GFX10_FORMAT", "name": "FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.4 350 {"bits": [21, 22], "name": "INDEX_STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.5 351 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.6 352 {"bits": [24, 24], "comment": "must be 1", "name": "RESOURCE_LEVEL"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.7 353 {"bits": [26, 27], "name": "LLC_NOALLOC"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.8 354 {"bits": [28, 29], "enum_ref": "SQ_BUF_RSRC_WORD3__OOB_SELECT", "name": "OOB_SELECT"}, array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.9 355 {"bits": [30, 31], "comment": "must be 0", "name": "TYPE"} array in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.10 360 {"bits": [0, 3], "name": "EN"}, array in object:register_types.SQ_EXP_0.fields.0 361 {"bits": [4, 9], "enum_ref": "SQ_EXP_0__TGT", "name": "TGT"}, array in object:register_types.SQ_EXP_0.fields.1 362 {"bits": [10, 10], "name": "COMPR"}, array in object:register_types.SQ_EXP_0.fields.2 363 {"bits": [11, 11], "name": "DONE"}, array in object:register_types.SQ_EXP_0.fields.3 364 {"bits": [12, 12], "name": "VM"} array in object:register_types.SQ_EXP_0.fields.4 369 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.0 370 {"bits": [8, 19], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.1 371 {"bits": [20, 28], "enum_ref": "GFX10_FORMAT", "name": "FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.2 372 {"bits": [30, 31], "name": "WIDTH_LO"} array in object:register_types.SQ_IMG_RSRC_WORD1.fields.3 377 {"bits": [0, 11], "name": "WIDTH_HI"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.0 378 {"bits": [14, 27], "name": "HEIGHT"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.1 379 {"bits": [31, 31], "comment": "must be 1", "name": "RESOURCE_LEVEL"} array in object:register_types.SQ_IMG_RSRC_WORD2.fields.2 384 {"bits": [0, 2], "name": "DST_SEL_X"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.0 385 {"bits": [3, 5], "name": "DST_SEL_Y"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.1 386 {"bits": [6, 8], "name": "DST_SEL_Z"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.2 387 {"bits": [9, 11], "name": "DST_SEL_W"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.3 388 {"bits": [12, 15], "name": "BASE_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.4 389 {"bits": [16, 19], "name": "LAST_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.5 390 {"bits": [20, 24], "name": "SW_MODE"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.6 391 {"bits": [25, 27], "enum_ref": "SQ_IMG_RSRC_WORD3__BC_SWIZZLE", "name": "BC_SWIZZLE"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.7 392 {"bits": [28, 31], "name": "TYPE"} array in object:register_types.SQ_IMG_RSRC_WORD3.fields.8 397 {"bits": [0, 12], "name": "DEPTH"}, array in object:register_types.SQ_IMG_RSRC_WORD4.fields.0 398 {"bits": [16, 28], "name": "BASE_ARRAY"} array in object:register_types.SQ_IMG_RSRC_WORD4.fields.1 403 {"bits": [0, 12], "name": "DEPTH"}, array in object:register_types.SQ_IMG_RSRC_WORD4_gfx103.fields.0 404 {"bits": [0, 13], "comment": "only for 1D, 2D, and 2D_MSAA if pitch > width", "name": "PITC array in object:register_types.SQ_IMG_RSRC_WORD4_gfx103.fields.1 405 {"bits": [16, 28], "name": "BASE_ARRAY"} array in object:register_types.SQ_IMG_RSRC_WORD4_gfx103.fields.2 410 {"bits": [0, 3], "name": "ARRAY_PITCH"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.0 411 {"bits": [4, 7], "name": "MAX_MIP"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.1 412 {"bits": [8, 19], "name": "MIN_LOD_WARN"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.2 413 {"bits": [20, 22], "name": "PERF_MOD"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.3 414 {"bits": [23, 23], "name": "CORNER_SAMPLES"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.4 415 {"bits": [25, 25], "name": "LOD_HDW_CNT_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.5 416 {"bits": [26, 26], "name": "PRT_DEFAULT"} array in object:register_types.SQ_IMG_RSRC_WORD5.fields.6 421 {"bits": [0, 3], "name": "ARRAY_PITCH"}, array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.0 422 {"bits": [4, 7], "name": "MAX_MIP"}, array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.1 423 {"bits": [8, 19], "name": "MIN_LOD_WARN"}, array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.2 424 {"bits": [20, 22], "name": "PERF_MOD"}, array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.3 425 {"bits": [23, 23], "name": "CORNER_SAMPLES"}, array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.4 426 {"bits": [25, 25], "name": "LOD_HDW_CNT_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.5 427 {"bits": [26, 26], "name": "PRT_DEFAULT"}, array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.6 428 {"bits": [31, 31], "name": "BIG_PAGE"} array in object:register_types.SQ_IMG_RSRC_WORD5_gfx103.fields.7 433 {"bits": [0, 7], "name": "COUNTER_BANK_ID"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.0 434 {"bits": [10, 10], "name": "ITERATE_256"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.1 435 {"bits": [15, 16], "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.2 436 {"bits": [17, 18], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.3 437 {"bits": [19, 19], "name": "META_PIPE_ALIGNED"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.4 438 {"bits": [20, 20], "name": "WRITE_COMPRESS_ENABLE"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.5 439 {"bits": [21, 21], "name": "COMPRESSION_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.6 440 {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.7 441 {"bits": [23, 23], "name": "COLOR_TRANSFORM"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.8 442 {"bits": [24, 31], "name": "META_DATA_ADDRESS_LO"} array in object:register_types.SQ_IMG_RSRC_WORD6.fields.9 447 {"bits": [0, 7], "name": "COUNTER_BANK_ID"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.0 448 {"bits": [8, 9], "name": "LLC_NOALLOC"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.1 449 {"bits": [10, 10], "name": "ITERATE_256"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.2 450 {"bits": [15, 16], "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.3 451 {"bits": [17, 18], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.4 452 {"bits": [19, 19], "name": "META_PIPE_ALIGNED"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.5 453 {"bits": [20, 20], "name": "WRITE_COMPRESS_ENABLE"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.6 454 {"bits": [21, 21], "name": "COMPRESSION_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.7 455 {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.8 456 {"bits": [23, 23], "name": "COLOR_TRANSFORM"}, array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.9 457 {"bits": [24, 31], "name": "META_DATA_ADDRESS_LO"} array in object:register_types.SQ_IMG_RSRC_WORD6_gfx103.fields.10 462 {"bits": [0, 2], "name": "CLAMP_X"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.0 463 {"bits": [3, 5], "name": "CLAMP_Y"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.1 464 {"bits": [6, 8], "name": "CLAMP_Z"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.2 465 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.3 466 {"bits": [12, 14], "name": "DEPTH_COMPARE_FUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.4 467 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.5 468 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.6 469 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.7 470 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.8 471 {"bits": [21, 26], "name": "ANISO_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.9 472 {"bits": [27, 27], "name": "TRUNC_COORD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.10 473 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.11 474 {"bits": [29, 30], "name": "FILTER_MODE"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.12 475 {"bits": [31, 31], "name": "SKIP_DEGAMMA"} array in object:register_types.SQ_IMG_SAMP_WORD0.fields.13 480 {"bits": [0, 11], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.0 481 {"bits": [12, 23], "name": "MAX_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.1 482 {"bits": [24, 27], "name": "PERF_MIP"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.2 483 {"bits": [28, 31], "name": "PERF_Z"} array in object:register_types.SQ_IMG_SAMP_WORD1.fields.3 488 {"bits": [0, 13], "name": "LOD_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.0 489 {"bits": [0, 11], "comment": "if DERIV_ADJUST_EN == 1", "name": "BORDER_COLOR_PTR"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.1 490 {"bits": [12, 13], "comment": "if DERIV_ADJUST_EN == 1", "name": "BORDER_COLOR_TYPE"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.2 491 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.3 492 {"bits": [20, 21], "name": "XY_MAG_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.4 493 {"bits": [22, 23], "name": "XY_MIN_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.5 494 {"bits": [24, 25], "name": "Z_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.6 495 {"bits": [26, 27], "name": "MIP_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.7 496 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.8 497 {"bits": [29, 29], "name": "ANISO_OVERRIDE"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.9 498 {"bits": [30, 30], "name": "BLEND_ZERO_PRT"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.10 499 {"bits": [31, 31], "name": "DERIV_ADJUST_EN"} array in object:register_types.SQ_IMG_SAMP_WORD2.fields.11 504 {"bits": [0, 11], "comment": "if DERIV_ADJUST_EN == 0", "name": "BORDER_COLOR_PTR"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.0 505 {"bits": [30, 31], "comment": "if DERIV_ADJUST_EN == 0", "name": "BORDER_COLOR_TYPE"} array in object:register_types.SQ_IMG_SAMP_WORD3.fields.1 [all...]
H A D	pkt3.json	265 {"bits": [0, 20], "name": "BYTE_COUNT"}, array in object:register_types.COMMAND.fields.0 266 {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"}, array in object:register_types.COMMAND.fields.1 267 {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"}, array in object:register_types.COMMAND.fields.2 268 {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"}, array in object:register_types.COMMAND.fields.3 269 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"}, array in object:register_types.COMMAND.fields.4 270 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"}, array in object:register_types.COMMAND.fields.5 271 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"}, array in object:register_types.COMMAND.fields.6 272 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"}, array in object:register_types.COMMAND.fields.7 273 {"bits": [30, 30], "name": "RAW_WAIT"} array in object:register_types.COMMAND.fields.8 278 {"bits" array in object:register_types.COMMAND_gfx9.fields.0 279 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"}, array in object:register_types.COMMAND_gfx9.fields.1 280 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"}, array in object:register_types.COMMAND_gfx9.fields.2 281 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"}, array in object:register_types.COMMAND_gfx9.fields.3 282 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"}, array in object:register_types.COMMAND_gfx9.fields.4 283 {"bits": [30, 30], "name": "RAW_WAIT"}, array in object:register_types.COMMAND_gfx9.fields.5 284 {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"} array in object:register_types.COMMAND_gfx9.fields.6 289 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"}, array in object:register_types.CONTROL.fields.0 290 {"bits": [16, 16], "name": "WR_ONE_ADDR"}, array in object:register_types.CONTROL.fields.1 291 {"bits": [20, 20], "name": "WR_CONFIRM"}, array in object:register_types.CONTROL.fields.2 292 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"} array in object:register_types.CONTROL.fields.3 297 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"}, array in object:register_types.CONTROL_cik.fields.0 298 {"bits": [16, 16], "name": "WR_ONE_ADDR"}, array in object:register_types.CONTROL_cik.fields.1 299 {"bits": [20, 20], "name": "WR_CONFIRM"}, array in object:register_types.CONTROL_cik.fields.2 300 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"} array in object:register_types.CONTROL_cik.fields.3 305 {"bits": [0, 31], "name": "SRC_ADDR_LO"} array in object:register_types.CP_DMA_WORD0.fields.0 310 {"bits": [0, 15], "name": "SRC_ADDR_HI"}, array in object:register_types.CP_DMA_WORD1.fields.0 311 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"}, array in object:register_types.CP_DMA_WORD1.fields.1 312 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array in object:register_types.CP_DMA_WORD1.fields.2 313 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"}, array in object:register_types.CP_DMA_WORD1.fields.3 314 {"bits": [31, 31], "name": "CP_SYNC"} array in object:register_types.CP_DMA_WORD1.fields.4 319 {"bits": [0, 15], "name": "SRC_ADDR_HI"}, array in object:register_types.CP_DMA_WORD1_cik.fields.0 320 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"}, array in object:register_types.CP_DMA_WORD1_cik.fields.1 321 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array in object:register_types.CP_DMA_WORD1_cik.fields.2 322 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array in object:register_types.CP_DMA_WORD1_cik.fields.3 323 {"bits": [31, 31], "name": "CP_SYNC"} array in object:register_types.CP_DMA_WORD1_cik.fields.4 328 {"bits": [0, 15], "name": "SRC_ADDR_HI"}, array in object:register_types.CP_DMA_WORD1_gfx9.fields.0 329 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"}, array in object:register_types.CP_DMA_WORD1_gfx9.fields.1 330 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array in object:register_types.CP_DMA_WORD1_gfx9.fields.2 331 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array in object:register_types.CP_DMA_WORD1_gfx9.fields.3 332 {"bits": [31, 31], "name": "CP_SYNC"} array in object:register_types.CP_DMA_WORD1_gfx9.fields.4 337 {"bits": [0, 31], "name": "DST_ADDR_LO"} array in object:register_types.CP_DMA_WORD2.fields.0 342 {"bits": [0, 15], "name": "DST_ADDR_HI"} array in object:register_types.CP_DMA_WORD3.fields.0 347 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array in object:register_types.DMA_DATA_WORD0.fields.0 348 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"}, array in object:register_types.DMA_DATA_WORD0.fields.1 349 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"}, array in object:register_types.DMA_DATA_WORD0.fields.2 350 {"bits": [31, 31], "name": "CP_SYNC"} array in object:register_types.DMA_DATA_WORD0.fields.3 355 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array in object:register_types.DMA_DATA_WORD0_cik.fields.0 356 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, array in object:register_types.DMA_DATA_WORD0_cik.fields.1 357 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"}, array in object:register_types.DMA_DATA_WORD0_cik.fields.2 358 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, array in object:register_types.DMA_DATA_WORD0_cik.fields.3 359 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array in object:register_types.DMA_DATA_WORD0_cik.fields.4 360 {"bits": [31, 31], "name": "CP_SYNC"} array in object:register_types.DMA_DATA_WORD0_cik.fields.5 365 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array in object:register_types.DMA_DATA_WORD0_gfx9.fields.0 366 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, array in object:register_types.DMA_DATA_WORD0_gfx9.fields.1 367 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"}, array in object:register_types.DMA_DATA_WORD0_gfx9.fields.2 368 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, array in object:register_types.DMA_DATA_WORD0_gfx9.fields.3 369 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array in object:register_types.DMA_DATA_WORD0_gfx9.fields.4 370 {"bits": [31, 31], "name": "CP_SYNC"} array in object:register_types.DMA_DATA_WORD0_gfx9.fields.5 375 {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"}, array in object:register_types.GCR_CNTL.fields.0 376 {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"}, array in object:register_types.GCR_CNTL.fields.1 377 {"bits": [4, 4], "name": "GLM_WB"}, array in object:register_types.GCR_CNTL.fields.2 378 {"bits": [5, 5], "name": "GLM_INV"}, array in object:register_types.GCR_CNTL.fields.3 379 {"bits": [6, 6], "name": "GLK_WB"}, array in object:register_types.GCR_CNTL.fields.4 380 {"bits": [7, 7], "name": "GLK_INV"}, array in object:register_types.GCR_CNTL.fields.5 381 {"bits": [8, 8], "name": "GLV_INV"}, array in object:register_types.GCR_CNTL.fields.6 382 {"bits": [9, 9], "name": "GL1_INV"}, array in object:register_types.GCR_CNTL.fields.7 383 {"bits": [10, 10], "name": "GL2_US"}, array in object:register_types.GCR_CNTL.fields.8 384 {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"}, array in object:register_types.GCR_CNTL.fields.9 385 {"bits": [13, 13], "name": "GL2_DISCARD"}, array in object:register_types.GCR_CNTL.fields.10 386 {"bits": [14, 14], "name": "GL2_INV"}, array in object:register_types.GCR_CNTL.fields.11 387 {"bits": [15, 15], "name": "GL2_WB"}, array in object:register_types.GCR_CNTL.fields.12 388 {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"}, array in object:register_types.GCR_CNTL.fields.13 389 {"bits": [18, 18], "name": "RANGE_IS_PA"} array in object:register_types.GCR_CNTL.fields.14 394 {"bits": [0, 19], "name": "IB_SIZE"}, array in object:register_types.IB_CONTROL.fields.0 395 {"bits": [20, 20], "name": "CHAIN"}, array in object:register_types.IB_CONTROL.fields.1 396 {"bits": [23, 23], "name": "VALID"} array in object:register_types.IB_CONTROL.fields.2 401 {"bits": [0, 5], "name": "EVENT_TYPE"}, array in object:register_types.RELEASE_MEM_OP.fields.0 402 {"bits": [8, 11], "name": "EVENT_INDEX"}, array in object:register_types.RELEASE_MEM_OP.fields.1 403 {"bits": [12, 12], "name": "GLM_WB"}, array in object:register_types.RELEASE_MEM_OP.fields.2 404 {"bits": [13, 13], "name": "GLM_INV"}, array in object:register_types.RELEASE_MEM_OP.fields.3 405 {"bits": [14, 14], "name": "GLV_INV"}, array in object:register_types.RELEASE_MEM_OP.fields.4 406 {"bits": [15, 15], "name": "GL1_INV"}, array in object:register_types.RELEASE_MEM_OP.fields.5 407 {"bits": [16, 16], "name": "GL2_US"}, array in object:register_types.RELEASE_MEM_OP.fields.6 408 {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"}, array in object:register_types.RELEASE_MEM_OP.fields.7 409 {"bits": [19, 19], "name": "GL2_DISCARD"}, array in object:register_types.RELEASE_MEM_OP.fields.8 410 {"bits": [20, 20], "name": "GL2_INV"}, array in object:register_types.RELEASE_MEM_OP.fields.9 411 {"bits": [21, 21], "name": "GL2_WB"}, array in object:register_types.RELEASE_MEM_OP.fields.10 412 {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"} array in object:register_types.RELEASE_MEM_OP.fields.11 [all...]
H A D	gfx6.json	7648 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.0 7649 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.1 7650 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.2 7651 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.3 7652 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.4 7653 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.5 7654 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.6 7655 {"bits": [30, 30], "name": "ENABLE"}, array in object:register_types.CB_BLEND0_CONTROL.fields.7 7656 {"bits": [31, 31], "name": "DISABLE_ROP3"} array in object:register_types.CB_BLEND0_CONTROL.fields.8 7661 {"bits" array in object:register_types.CB_COLOR0_ATTRIB.fields.0 7662 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.1 7663 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.2 7664 {"bits": [12, 14], "name": "NUM_SAMPLES"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.3 7665 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.4 7666 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"} array in object:register_types.CB_COLOR0_ATTRIB.fields.5 7671 {"bits": [0, 13], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_CMASK_SLICE.fields.0 7676 {"bits": [0, 21], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_FMASK_SLICE.fields.0 7681 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, array in object:register_types.CB_COLOR0_INFO.fields.0 7682 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, array in object:register_types.CB_COLOR0_INFO.fields.1 7683 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, array in object:register_types.CB_COLOR0_INFO.fields.2 7684 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.3 7685 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, array in object:register_types.CB_COLOR0_INFO.fields.4 7686 {"bits": [13, 13], "name": "FAST_CLEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.5 7687 {"bits": [14, 14], "name": "COMPRESSION"}, array in object:register_types.CB_COLOR0_INFO.fields.6 7688 {"bits": [15, 15], "name": "BLEND_CLAMP"}, array in object:register_types.CB_COLOR0_INFO.fields.7 7689 {"bits": [16, 16], "name": "BLEND_BYPASS"}, array in object:register_types.CB_COLOR0_INFO.fields.8 7690 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, array in object:register_types.CB_COLOR0_INFO.fields.9 7691 {"bits": [18, 18], "name": "ROUND_MODE"}, array in object:register_types.CB_COLOR0_INFO.fields.10 7692 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.11 7693 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, array in object:register_types.CB_COLOR0_INFO.fields.12 7694 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, array in object:register_types.CB_COLOR0_INFO.fields.13 7695 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"} array in object:register_types.CB_COLOR0_INFO.fields.14 7700 {"bits": [0, 10], "name": "TILE_MAX"}, array in object:register_types.CB_COLOR0_PITCH.fields.0 7701 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} array in object:register_types.CB_COLOR0_PITCH.fields.1 7706 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.CB_COLOR0_VIEW.fields.0 7707 {"bits": [13, 23], "name": "SLICE_MAX"} array in object:register_types.CB_COLOR0_VIEW.fields.1 7712 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, array in object:register_types.CB_COLOR_CONTROL.fields.0 7713 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, array in object:register_types.CB_COLOR_CONTROL.fields.1 7714 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} array in object:register_types.CB_COLOR_CONTROL.fields.2 7719 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.0 7720 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.1 7721 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.2 7722 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.3 7723 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.4 7724 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.5 7725 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.6 7726 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} array in object:register_types.CB_SHADER_MASK.fields.7 7731 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.0 7732 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.1 7733 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.2 7734 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.3 7735 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.4 7736 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.5 7737 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.6 7738 {"bits": [28, 31], "name": "TARGET7_ENABLE"} array in object:register_types.CB_TARGET_MASK.fields.7 7743 {"bits": [1, 2], "name": "DPFP_RATE"}, array in object:register_types.CC_GC_SHADER_ARRAY_CONFIG.fields.0 7744 {"bits": [3, 3], "name": "SQC_BALANCE_DISABLE"}, array in object:register_types.CC_GC_SHADER_ARRAY_CONFIG.fields.1 7745 {"bits": [4, 4], "name": "HALF_LDS"}, array in object:register_types.CC_GC_SHADER_ARRAY_CONFIG.fields.2 7746 {"bits": [16, 31], "name": "INACTIVE_CUS"} array in object:register_types.CC_GC_SHADER_ARRAY_CONFIG.fields.3 7751 {"bits": [16, 19], "name": "SQC0_BANK_DISABLE"}, array in object:register_types.CC_SQC_BANK_DISABLE.fields.0 7752 {"bits": [20, 23], "name": "SQC1_BANK_DISABLE"}, array in object:register_types.CC_SQC_BANK_DISABLE.fields.1 7753 {"bits": [24, 27], "name": "SQC2_BANK_DISABLE"}, array in object:register_types.CC_SQC_BANK_DISABLE.fields.2 7754 {"bits": [28, 31], "name": "SQC3_BANK_DISABLE"} array in object:register_types.CC_SQC_BANK_DISABLE.fields.3 7759 {"bits": [0, 3], "name": "ON_DELAY"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.0 7760 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.1 7761 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.2 7762 {"bits": [25, 25], "name": "PERF_ENABLE"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.3 7763 {"bits": [26, 26], "name": "DBG_ENABLE"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.4 7764 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.5 7765 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.6 7766 {"bits": [29, 29], "name": "CORE_OVERRIDE"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.7 7767 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, array in object:register_types.CGTT_IA_CLK_CTRL.fields.8 7768 {"bits": [31, 31], "name": "REG_OVERRIDE"} array in object:register_types.CGTT_IA_CLK_CTRL.fields.9 7773 {"bits": [0, 3], "name": "ON_DELAY"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.0 7774 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.1 7775 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.2 7776 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.3 7777 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.4 7778 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.5 7779 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.6 7780 {"bits": [29, 29], "name": "SU_CLK_OVERRIDE"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.7 7781 {"bits": [30, 30], "name": "CL_CLK_OVERRIDE"}, array in object:register_types.CGTT_PA_CLK_CTRL.fields.8 7782 {"bits": [31, 31], "name": "REG_CLK_OVERRIDE"} array in object:register_types.CGTT_PA_CLK_CTRL.fields.9 7787 {"bits": [0, 3], "name": "ON_DELAY"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.0 7788 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.1 7789 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.2 7790 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.3 7791 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.4 7792 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.5 7793 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.6 7794 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.7 7795 {"bits": [30, 30], "name": "SOFT_OVERRIDE1"}, array in object:register_types.CGTT_SC_CLK_CTRL.fields.8 7796 {"bits": [31, 31], "name": "SOFT_OVERRIDE0"} array in object:register_types.CGTT_SC_CLK_CTRL.fields.9 7801 {"bits": [0, 3], "name": "ON_DELAY"}, array in object:register_types.CGTT_SQ_CLK_CTRL.fields.0 7802 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, array in object:register_types.CGTT_SQ_CLK_CTRL.fields.1 7803 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, array in object:register_types.CGTT_SQ_CLK_CTRL.fields.2 7804 {"bits": [31, 31], "name": "REG_OVERRIDE"} array in object:register_types.CGTT_SQ_CLK_CTRL.fields.3 7809 {"bits": [0, 3], "name": "ON_DELAY"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.0 7810 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.1 7811 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.2 7812 {"bits": [25, 25], "name": "PERF_ENABLE"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.3 7813 {"bits": [26, 26], "name": "DBG_ENABLE"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.4 7814 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.5 7815 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.6 7816 {"bits": [29, 29], "name": "GS_OVERRIDE"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.7 7817 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, array in object:register_types.CGTT_VGT_CLK_CTRL.fields.8 7818 {"bits": [31, 31], "name": "REG_OVERRIDE"} array in object:register_types.CGTT_VGT_CLK_CTRL.fields.9 7823 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.0 7824 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.1 7825 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.2 7826 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.3 7827 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.4 7828 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.5 7829 {"bits": [6, 6], "name": "ORDER_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.6 7830 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.7 7831 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.8 7832 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.9 7833 {"bits": [12, 12], "name": "DATA_ATC"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.10 7834 {"bits": [14, 14], "name": "RESTORE"} array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.11 7839 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, array in object:register_types.COMPUTE_NUM_THREAD_X.fields.0 7840 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} array in object:register_types.COMPUTE_NUM_THREAD_X.fields.1 7845 {"bits": [0, 7], "name": "DATA"}, array in object:register_types.COMPUTE_PGM_HI.fields.0 7846 {"bits": [8, 8], "name": "INST_ATC"} array in object:register_types.COMPUTE_PGM_HI.fields.1 7851 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.0 7852 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.1 7853 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.2 7854 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.3 7855 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.4 7856 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.5 7857 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.6 7858 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.7 7859 {"bits": [24, 24], "name": "BULKY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.8 7860 {"bits": [25, 25], "name": "CDBG_USER"} array in object:register_types.COMPUTE_PGM_RSRC1.fields.9 7865 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.0 7866 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.1 7867 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.2 7868 {"bits": [7, 7], "name": "TGID_X_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.3 7869 {"bits": [8, 8], "name": "TGID_Y_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.4 7870 {"bits": [9, 9], "name": "TGID_Z_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.5 7871 {"bits": [10, 10], "name": "TG_SIZE_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.6 7872 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.7 7873 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.8 7874 {"bits": [15, 23], "name": "LDS_SIZE"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.9 7875 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.COMPUTE_PGM_RSRC2.fields.10 7880 {"bits": [0, 5], "name": "WAVES_PER_SH"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.0 7881 {"bits": [0, 5], "name": "WAVES_PER_SH_GFX6"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.1 7882 {"bits": [12, 15], "name": "TG_PER_CU"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.2 7883 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.3 7884 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.4 7885 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.5 7886 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.6 7891 {"bits": [0, 15], "name": "SH0_CU_EN"}, array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.0 7892 {"bits": [16, 31], "name": "SH1_CU_EN"} array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.1 7897 {"bits": [0, 7], "name": "DATA"} array in object:register_types.COMPUTE_TBA_HI.fields.0 7902 {"bits": [0, 11], "name": "WAVES"}, array in object:register_types.COMPUTE_TMPRING_SIZE.fields.0 7903 {"bits": [12, 24], "name": "WAVESIZE"} array in object:register_types.COMPUTE_TMPRING_SIZE.fields.1 7908 {"bits": [0, 3], "name": "DATA"} array in object:register_types.COMPUTE_VMID.fields.0 7913 {"bits": [0, 7], "name": "MEM_ADDR_HI"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.0 7914 {"bits": [16, 17], "name": "CS_PS_SEL"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.1 7915 {"bits": [29, 31], "name": "COMMAND"} array in object:register_types.CP_APPEND_ADDR_HI.fields.2 7920 {"bits": [2, 31], "name": "MEM_ADDR_LO"} array in object:register_types.CP_APPEND_ADDR_LO.fields.0 7925 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.0 7926 {"bits": [6, 6], "name": "COHER_CNT_NEQ_ZERO"}, array in object:register_types.CP_BUSY_STAT.fields.1 7927 {"bits": [7, 7], "name": "PFP_PARSING_PACKETS"}, array in object:register_types.CP_BUSY_STAT.fields.2 7928 {"bits": [8, 8], "name": "ME_PARSING_PACKETS"}, array in object:register_types.CP_BUSY_STAT.fields.3 7929 {"bits": [9, 9], "name": "RCIU_PFP_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.4 7930 {"bits": [10, 10], "name": "RCIU_ME_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.5 7931 {"bits": [12, 12], "name": "SEM_CMDFIFO_NOT_EMPTY"}, array in object:register_types.CP_BUSY_STAT.fields.6 7932 {"bits": [13, 13], "name": "SEM_FAILED_AND_HOLDING"}, array in object:register_types.CP_BUSY_STAT.fields.7 7933 {"bits": [14, 14], "name": "SEM_POLLING_FOR_PASS"}, array in object:register_types.CP_BUSY_STAT.fields.8 7934 {"bits": [15, 15], "name": "GFX_CONTEXT_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.9 7935 {"bits": [17, 17], "name": "ME_PARSER_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.10 7936 {"bits": [18, 18], "name": "EOP_DONE_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.11 7937 {"bits": [19, 19], "name": "STRM_OUT_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.12 7938 {"bits": [20, 20], "name": "PIPE_STATS_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.13 7939 {"bits": [21, 21], "name": "RCIU_CE_BUSY"}, array in object:register_types.CP_BUSY_STAT.fields.14 7940 {"bits": [22, 22], "name": "CE_PARSING_PACKETS"} array in object:register_types.CP_BUSY_STAT.fields.15 7945 {"bits": [0, 10], "name": "CEQ_CNT_RING"}, array in object:register_types.CP_CEQ1_AVAIL.fields.0 7946 {"bits": [16, 26], "name": "CEQ_CNT_IB1"} array in object:register_types.CP_CEQ1_AVAIL.fields.1 7951 {"bits": [0, 10], "name": "CEQ_CNT_IB2"} array in object:register_types.CP_CEQ2_AVAIL.fields.0 7956 {"bits": [0, 7], "name": "IB1_BASE_HI"} array in object:register_types.CP_CE_IB1_BASE_HI.fields.0 7961 {"bits": [2, 31], "name": "IB1_BASE_LO"} array in object:register_types.CP_CE_IB1_BASE_LO.fields.0 7966 {"bits": [0, 19], "name": "IB1_BUFSZ"} array in object:register_types.CP_CE_IB1_BUFSZ.fields.0 7971 {"bits": [0, 7], "name": "IB2_BASE_HI"} array in object:register_types.CP_CE_IB2_BASE_HI.fields.0 7976 {"bits": [2, 31], "name": "IB2_BASE_LO"} array in object:register_types.CP_CE_IB2_BASE_LO.fields.0 7981 {"bits": [0, 19], "name": "IB2_BUFSZ"} array in object:register_types.CP_CE_IB2_BUFSZ.fields.0 7986 {"bits": [0, 7], "name": "INIT_BASE_HI"} array in object:register_types.CP_CE_INIT_BASE_HI.fields.0 7991 {"bits": [5, 31], "name": "INIT_BASE_LO"} array in object:register_types.CP_CE_INIT_BASE_LO.fields.0 7996 {"bits": [0, 11], "name": "INIT_BUFSZ"} array in object:register_types.CP_CE_INIT_BUFSZ.fields.0 8001 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT1"}, array in object:register_types.CP_CE_ROQ_IB1_STAT.fields.0 8002 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT1"} array in object:register_types.CP_CE_ROQ_IB1_STAT.fields.1 8007 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT2"}, array in object:register_types.CP_CE_ROQ_IB2_STAT.fields.0 8008 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT2"} array in object:register_types.CP_CE_ROQ_IB2_STAT.fields.1 8013 {"bits": [0, 9], "name": "CEQ_RPTR_PRIMARY"}, array in object:register_types.CP_CE_ROQ_RB_STAT.fields.0 8014 {"bits": [16, 25], "name": "CEQ_WPTR_PRIMARY"} array in object:register_types.CP_CE_ROQ_RB_STAT.fields.1 8019 {"bits": [0, 10], "name": "CMD_INDEX"}, array in object:register_types.CP_CMD_INDEX.fields.0 8020 {"bits": [12, 13], "name": "CMD_ME_SEL"}, array in object:register_types.CP_CMD_INDEX.fields.1 8021 {"bits": [16, 17], "name": "CMD_QUEUE_SEL"} array in object:register_types.CP_CMD_INDEX.fields.2 8026 {"bits": [0, 7], "name": "ACTIVE_HP3D_CONTEXTS"}, array in object:register_types.CP_CNTX_STAT.fields.0 8027 {"bits": [8, 10], "name": "CURRENT_HP3D_CONTEXT"}, array in object:register_types.CP_CNTX_STAT.fields.1 8028 {"bits": [20, 27], "name": "ACTIVE_GFX_CONTEXTS"}, array in object:register_types.CP_CNTX_STAT.fields.2 8029 {"bits": [28, 30], "name": "CURRENT_GFX_CONTEXT"} array in object:register_types.CP_CNTX_STAT.fields.3 8034 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.0 8035 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.1 8036 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.2 8037 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.3 8038 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.4 8039 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.5 8040 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.6 8041 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.7 8042 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.8 8043 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.9 8044 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.10 8045 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.11 8046 {"bits": [16, 16], "name": "TC_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.12 8047 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.13 8048 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.14 8049 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.15 8050 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.16 8051 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.17 8052 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.18 8053 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.19 8054 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.20 8055 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.21 8056 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"} array in object:register_types.CP_COHER_CNTL.fields.22 8061 {"bits": [0, 5], "name": "START_DELAY_COUNT"} array in object:register_types.CP_COHER_START_DELAY.fields.0 8066 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, array in object:register_types.CP_COHER_STATUS.fields.0 8067 {"bits": [24, 25], "name": "MEID"}, array in object:register_types.CP_COHER_STATUS.fields.1 8068 {"bits": [30, 30], "name": "PHASE1_STATUS"}, array in object:register_types.CP_COHER_STATUS.fields.2 8069 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_COHER_STATUS.fields.3 8074 {"bits": [0, 3], "name": "FETCH_BUFFER_DEPTH"} array in object:register_types.CP_CSF_CNTL.fields.0 8079 {"bits": [0, 3], "name": "BUFFER_SLOTS_ALLOCATED"}, array in object:register_types.CP_CSF_STAT.fields.0 8080 {"bits": [8, 13], "name": "BUFFER_REQUEST_COUNT"} array in object:register_types.CP_CSF_STAT.fields.1 8085 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, array in object:register_types.CP_DMA_CNTL.fields.0 8086 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, array in object:register_types.CP_DMA_CNTL.fields.1 8087 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, array in object:register_types.CP_DMA_CNTL.fields.2 8088 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, array in object:register_types.CP_DMA_CNTL.fields.3 8089 {"bits": [30, 31], "name": "PIO_COUNT"} array in object:register_types.CP_DMA_CNTL.fields.4 8094 {"bits": [0, 20], "name": "BYTE_COUNT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.0 8095 {"bits": [21, 21], "name": "DIS_WC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.1 8096 {"bits": [22, 23], "name": "SRC_SWAP"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.2 8097 {"bits": [24, 25], "name": "DST_SWAP"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.3 8098 {"bits": [26, 26], "name": "SAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.4 8099 {"bits": [27, 27], "name": "DAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.5 8100 {"bits": [28, 28], "name": "SAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.6 8101 {"bits": [29, 29], "name": "DAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.7 8102 {"bits": [30, 30], "name": "RAW_WAIT"} array in object:register_types.CP_DMA_ME_COMMAND.fields.8 8107 {"bits": [0, 7], "name": "DST_ADDR_HI"} array in object:register_types.CP_DMA_ME_DST_ADDR_HI.fields.0 8112 {"bits": [0, 7], "name": "SRC_ADDR_HI"} array in object:register_types.CP_DMA_ME_SRC_ADDR_HI.fields.0 8117 {"bits": [0, 25], "name": "DMA_READ_TAG"}, array in object:register_types.CP_DMA_READ_TAGS.fields.0 8118 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} array in object:register_types.CP_DMA_READ_TAGS.fields.1 8123 {"bits": [0, 15], "name": "ADDR_HI"} array in object:register_types.CP_EOP_DONE_ADDR_HI.fields.0 8128 {"bits": [0, 1], "name": "ADDR_SWAP"}, array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.0 8129 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.1 8134 {"bits": [0, 5], "name": "FREE_COUNT"}, array in object:register_types.CP_GRBM_FREE_COUNT.fields.0 8135 {"bits": [8, 13], "name": "FREE_COUNT_GDS"}, array in object:register_types.CP_GRBM_FREE_COUNT.fields.1 8136 {"bits": [16, 21], "name": "FREE_COUNT_PFP"} array in object:register_types.CP_GRBM_FREE_COUNT.fields.2 8141 {"bits": [0, 19], "name": "IB1_OFFSET"} array in object:register_types.CP_IB1_OFFSET.fields.0 8146 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} array in object:register_types.CP_IB1_PREAMBLE_BEGIN.fields.0 8151 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} array in object:register_types.CP_IB1_PREAMBLE_END.fields.0 8156 {"bits": [0, 19], "name": "IB2_OFFSET"} array in object:register_types.CP_IB2_OFFSET.fields.0 8161 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} array in object:register_types.CP_IB2_PREAMBLE_BEGIN.fields.0 8166 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} array in object:register_types.CP_IB2_PREAMBLE_END.fields.0 8171 {"bits": [14, 14], "name": "CP_ECC_ERROR_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.0 8172 {"bits": [17, 17], "name": "WRM_POLL_TIMEOUT_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.1 8173 {"bits": [19, 19], "name": "CNTX_BUSY_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.2 8174 {"bits": [20, 20], "name": "CNTX_EMPTY_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.3 8175 {"bits": [22, 22], "name": "PRIV_INSTR_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.4 8176 {"bits": [23, 23], "name": "PRIV_REG_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.5 8177 {"bits": [24, 24], "name": "OPCODE_ERROR_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.6 8178 {"bits": [26, 26], "name": "TIME_STAMP_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.7 8179 {"bits": [27, 27], "name": "RESERVED_BIT_ERROR_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.8 8180 {"bits": [29, 29], "name": "GENERIC2_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.9 8181 {"bits": [30, 30], "name": "GENERIC1_INT_ASSERTED"}, array in object:register_types.CP_INT_STAT_DEBUG.fields.10 8182 {"bits": [31, 31], "name": "GENERIC0_INT_ASSERTED"} array in object:register_types.CP_INT_STAT_DEBUG.fields.11 8187 {"bits": [0, 4], "name": "PACK_DELAY_CNT"} array in object:register_types.CP_MC_PACK_DELAY_CNT.fields.0 8192 {"bits": [0, 9], "name": "MEQ_CNT"} array in object:register_types.CP_MEQ_AVAIL.fields.0 8197 {"bits": [0, 9], "name": "MEQ_RPTR"}, array in object:register_types.CP_MEQ_STAT.fields.0 8198 {"bits": [16, 25], "name": "MEQ_WPTR"} array in object:register_types.CP_MEQ_STAT.fields.1 8203 {"bits": [0, 7], "name": "MEQ1_START"}, array in object:register_types.CP_MEQ_THRESHOLDS.fields.0 8204 {"bits": [8, 15], "name": "MEQ2_START"} array in object:register_types.CP_MEQ_THRESHOLDS.fields.1 8209 {"bits": [4, 4], "name": "CE_INVALIDATE_ICACHE"}, array in object:register_types.CP_ME_CNTL.fields.0 8210 {"bits": [6, 6], "name": "PFP_INVALIDATE_ICACHE"}, array in object:register_types.CP_ME_CNTL.fields.1 8211 {"bits": [8, 8], "name": "ME_INVALIDATE_ICACHE"}, array in object:register_types.CP_ME_CNTL.fields.2 8212 {"bits": [24, 24], "name": "CE_HALT"}, array in object:register_types.CP_ME_CNTL.fields.3 8213 {"bits": [25, 25], "name": "CE_STEP"}, array in object:register_types.CP_ME_CNTL.fields.4 8214 {"bits": [26, 26], "name": "PFP_HALT"}, array in object:register_types.CP_ME_CNTL.fields.5 8215 {"bits": [27, 27], "name": "PFP_STEP"}, array in object:register_types.CP_ME_CNTL.fields.6 8216 {"bits": [28, 28], "name": "ME_HALT"}, array in object:register_types.CP_ME_CNTL.fields.7 8217 {"bits": [29, 29], "name": "ME_STEP"} array in object:register_types.CP_ME_CNTL.fields.8 8222 {"bits": [0, 7], "name": "ME_MC_RADDR_HI"} array in object:register_types.CP_ME_MC_RADDR_HI.fields.0 8227 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"}, array in object:register_types.CP_ME_MC_RADDR_LO.fields.0 8228 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} array in object:register_types.CP_ME_MC_RADDR_LO.fields.1 8233 {"bits": [0, 7], "name": "ME_MC_WADDR_HI"} array in object:register_types.CP_ME_MC_WADDR_HI.fields.0 8238 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"}, array in object:register_types.CP_ME_MC_WADDR_LO.fields.0 8239 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} array in object:register_types.CP_ME_MC_WADDR_LO.fields.1 8244 {"bits": [0, 0], "name": "ME_CNTXSW_PREEMPTION"} array in object:register_types.CP_ME_PREEMPTION.fields.0 8249 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.0 8250 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.1 8251 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, array in object:register_types.CP_PERFMON_CNTL.fields.2 8252 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.CP_PERFMON_CNTL.fields.3 8257 {"bits": [31, 31], "name": "PERFMON_ENABLE"} array in object:register_types.CP_PERFMON_CNTX_CNTL.fields.0 8262 {"bits": [0, 0], "name": "IB_EN"} array in object:register_types.CP_PFP_IB_CONTROL.fields.0 8267 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.0 8268 {"bits": [1, 1], "name": "CNTX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.1 8269 {"bits": [15, 15], "name": "UCONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.2 8270 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.3 8271 {"bits": [24, 24], "name": "SH_CS_REG_EN"} array in object:register_types.CP_PFP_LOAD_CONTROL.fields.4 8276 {"bits": [0, 1], "name": "PIPE_STATS_ADDR_SWAP"}, array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.0 8277 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.1 8282 {"bits": [0, 5], "name": "ROQ_IB1_START"}, array in object:register_types.CP_QUEUE_THRESHOLDS.fields.0 8283 {"bits": [8, 13], "name": "ROQ_IB2_START"} array in object:register_types.CP_QUEUE_THRESHOLDS.fields.1 8288 {"bits": [0, 19], "name": "RB_RPTR"} array in object:register_types.CP_RB0_RPTR.fields.0 8293 {"bits": [0, 19], "name": "RB_OFFSET"} array in object:register_types.CP_RB_OFFSET.fields.0 8298 {"bits": [0, 27], "name": "PRE_WRITE_TIMER"}, array in object:register_types.CP_RB_WPTR_DELAY.fields.0 8299 {"bits": [28, 31], "name": "PRE_WRITE_LIMIT"} array in object:register_types.CP_RB_WPTR_DELAY.fields.1 8304 {"bits": [0, 15], "name": "POLL_FREQUENCY"}, array in object:register_types.CP_RB_WPTR_POLL_CNTL.fields.0 8305 {"bits": [16, 31], "name": "IDLE_POLL_COUNT"} array in object:register_types.CP_RB_WPTR_POLL_CNTL.fields.1 8310 {"bits": [0, 1], "name": "RINGID"} array in object:register_types.CP_RINGID.fields.0 8315 {"bits": [0, 7], "name": "RB1_START"}, array in object:register_types.CP_ROQ1_THRESHOLDS.fields.0 8316 {"bits": [8, 15], "name": "RB2_START"}, array in object:register_types.CP_ROQ1_THRESHOLDS.fields.1 8317 {"bits": [16, 23], "name": "R0_IB1_START"}, array in object:register_types.CP_ROQ1_THRESHOLDS.fields.2 8318 {"bits": [24, 31], "name": "R1_IB1_START"} array in object:register_types.CP_ROQ1_THRESHOLDS.fields.3 8323 {"bits": [0, 10], "name": "ROQ_CNT_IB2"} array in object:register_types.CP_ROQ2_AVAIL.fields.0 8328 {"bits": [0, 7], "name": "R2_IB1_START"}, array in object:register_types.CP_ROQ2_THRESHOLDS.fields.0 8329 {"bits": [8, 15], "name": "R0_IB2_START"}, array in object:register_types.CP_ROQ2_THRESHOLDS.fields.1 8330 {"bits": [16, 23], "name": "R1_IB2_START"}, array in object:register_types.CP_ROQ2_THRESHOLDS.fields.2 8331 {"bits": [24, 31], "name": "R2_IB2_START"} array in object:register_types.CP_ROQ2_THRESHOLDS.fields.3 8336 {"bits": [0, 10], "name": "ROQ_CNT_RING"}, array in object:register_types.CP_ROQ_AVAIL.fields.0 8337 {"bits": [16, 26], "name": "ROQ_CNT_IB1"} array in object:register_types.CP_ROQ_AVAIL.fields.1 8342 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT1"}, array in object:register_types.CP_ROQ_IB1_STAT.fields.0 8343 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT1"} array in object:register_types.CP_ROQ_IB1_STAT.fields.1 8348 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT2"}, array in object:register_types.CP_ROQ_IB2_STAT.fields.0 8349 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT2"} array in object:register_types.CP_ROQ_IB2_STAT.fields.1 8354 {"bits": [0, 9], "name": "ROQ_RPTR_PRIMARY"}, array in object:register_types.CP_ROQ_RB_STAT.fields.0 8355 {"bits": [16, 25], "name": "ROQ_WPTR_PRIMARY"} array in object:register_types.CP_ROQ_RB_STAT.fields.1 8360 {"bits": [0, 7], "name": "SCRATCH_INDEX"} array in object:register_types.CP_SCRATCH_INDEX.fields.0 8365 {"bits": [0, 7], "name": "SEM_ADDR_HI"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.0 8366 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.1 8367 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.2 8368 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.3 8369 {"bits": [29, 31], "name": "SEM_SELECT"} array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.4 8374 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.0 8375 {"bits": [3, 31], "name": "SEM_ADDR_LO"} array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.1 8380 {"bits": [0, 0], "name": "RBIU_TO_DMA_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT1.fields.0 8381 {"bits": [2, 2], "name": "RBIU_TO_SEM_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT1.fields.1 8382 {"bits": [4, 4], "name": "RBIU_TO_MEMWR_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT1.fields.2 8383 {"bits": [10, 10], "name": "ME_HAS_ACTIVE_CE_BUFFER_FLAG"}, array in object:register_types.CP_STALLED_STAT1.fields.3 8384 {"bits": [11, 11], "name": "ME_HAS_ACTIVE_DE_BUFFER_FLAG"}, array in object:register_types.CP_STALLED_STAT1.fields.4 8385 {"bits": [12, 12], "name": "ME_STALLED_ON_TC_WR_CONFIRM"}, array in object:register_types.CP_STALLED_STAT1.fields.5 8386 {"bits": [13, 13], "name": "ME_STALLED_ON_ATOMIC_RTN_DATA"}, array in object:register_types.CP_STALLED_STAT1.fields.6 8387 {"bits": [14, 14], "name": "ME_WAITING_ON_MC_READ_DATA"}, array in object:register_types.CP_STALLED_STAT1.fields.7 8388 {"bits": [15, 15], "name": "ME_WAITING_ON_REG_READ_DATA"}, array in object:register_types.CP_STALLED_STAT1.fields.8 8389 {"bits": [16, 16], "name": "MIU_WAITING_ON_RDREQ_FREE"}, array in object:register_types.CP_STALLED_STAT1.fields.9 8390 {"bits": [17, 17], "name": "MIU_WAITING_ON_WRREQ_FREE"}, array in object:register_types.CP_STALLED_STAT1.fields.10 8391 {"bits": [23, 23], "name": "RCIU_WAITING_ON_GDS_FREE"}, array in object:register_types.CP_STALLED_STAT1.fields.11 8392 {"bits": [24, 24], "name": "RCIU_WAITING_ON_GRBM_FREE"}, array in object:register_types.CP_STALLED_STAT1.fields.12 8393 {"bits": [25, 25], "name": "RCIU_WAITING_ON_VGT_FREE"}, array in object:register_types.CP_STALLED_STAT1.fields.13 8394 {"bits": [26, 26], "name": "RCIU_STALLED_ON_ME_READ"}, array in object:register_types.CP_STALLED_STAT1.fields.14 8395 {"bits": [27, 27], "name": "RCIU_STALLED_ON_DMA_READ"}, array in object:register_types.CP_STALLED_STAT1.fields.15 8396 {"bits": [28, 28], "name": "RCIU_HALTED_BY_REG_VIOLATION"}, array in object:register_types.CP_STALLED_STAT1.fields.16 8397 {"bits": [28, 28], "name": "RCIU_STALLED_ON_APPEND_READ"} array in object:register_types.CP_STALLED_STAT1.fields.17 8402 {"bits": [0, 0], "name": "PFP_TO_CSF_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.0 8403 {"bits": [1, 1], "name": "PFP_TO_MEQ_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.1 8404 {"bits": [2, 2], "name": "PFP_TO_RCIU_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.2 8405 {"bits": [4, 4], "name": "PFP_TO_VGT_WRITES_PENDING"}, array in object:register_types.CP_STALLED_STAT2.fields.3 8406 {"bits": [5, 5], "name": "PFP_RCIU_READ_PENDING"}, array in object:register_types.CP_STALLED_STAT2.fields.4 8407 {"bits": [6, 6], "name": "PFP_MIU_READ_PENDING"}, array in object:register_types.CP_STALLED_STAT2.fields.5 8408 {"bits": [7, 7], "name": "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.6 8409 {"bits": [8, 8], "name": "PFP_WAITING_ON_BUFFER_DATA"}, array in object:register_types.CP_STALLED_STAT2.fields.7 8410 {"bits": [9, 9], "name": "ME_WAIT_ON_CE_COUNTER"}, array in object:register_types.CP_STALLED_STAT2.fields.8 8411 {"bits": [10, 10], "name": "ME_WAIT_ON_AVAIL_BUFFER"}, array in object:register_types.CP_STALLED_STAT2.fields.9 8412 {"bits": [11, 11], "name": "GFX_CNTX_NOT_AVAIL_TO_ME"}, array in object:register_types.CP_STALLED_STAT2.fields.10 8413 {"bits": [12, 12], "name": "ME_RCIU_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.11 8414 {"bits": [13, 13], "name": "ME_TO_CONST_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.12 8415 {"bits": [14, 14], "name": "ME_WAITING_DATA_FROM_PFP"}, array in object:register_types.CP_STALLED_STAT2.fields.13 8416 {"bits": [15, 15], "name": "ME_WAITING_ON_PARTIAL_FLUSH"}, array in object:register_types.CP_STALLED_STAT2.fields.14 8417 {"bits": [16, 16], "name": "MEQ_TO_ME_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.15 8418 {"bits": [17, 17], "name": "STQ_TO_ME_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT2.fields.16 8419 {"bits": [18, 18], "name": "ME_WAITING_DATA_FROM_STQ"}, array in object:register_types.CP_STALLED_STAT2.fields.17 8420 {"bits": [19, 19], "name": "PFP_STALLED_ON_TC_WR_CONFIRM"}, array in object:register_types.CP_STALLED_STAT2.fields.18 8421 {"bits": [20, 20], "name": "PFP_STALLED_ON_ATOMIC_RTN_DATA"}, array in object:register_types.CP_STALLED_STAT2.fields.19 8422 {"bits": [21, 21], "name": "EOPD_FIFO_NEEDS_SC_EOP_DONE"}, array in object:register_types.CP_STALLED_STAT2.fields.20 8423 {"bits": [22, 22], "name": "EOPD_FIFO_NEEDS_WR_CONFIRM"}, array in object:register_types.CP_STALLED_STAT2.fields.21 8424 {"bits": [23, 23], "name": "STRMO_WR_OF_PRIM_DATA_PENDING"}, array in object:register_types.CP_STALLED_STAT2.fields.22 8425 {"bits": [24, 24], "name": "PIPE_STATS_WR_DATA_PENDING"}, array in object:register_types.CP_STALLED_STAT2.fields.23 8426 {"bits": [25, 25], "name": "APPEND_RDY_WAIT_ON_CS_DONE"}, array in object:register_types.CP_STALLED_STAT2.fields.24 8427 {"bits": [26, 26], "name": "APPEND_RDY_WAIT_ON_PS_DONE"}, array in object:register_types.CP_STALLED_STAT2.fields.25 8428 {"bits": [27, 27], "name": "APPEND_WAIT_ON_WR_CONFIRM"}, array in object:register_types.CP_STALLED_STAT2.fields.26 8429 {"bits": [28, 28], "name": "APPEND_ACTIVE_PARTITION"}, array in object:register_types.CP_STALLED_STAT2.fields.27 8430 {"bits": [29, 29], "name": "APPEND_WAITING_TO_SEND_MEMWRITE"}, array in object:register_types.CP_STALLED_STAT2.fields.28 8431 {"bits": [30, 30], "name": "SURF_SYNC_NEEDS_IDLE_CNTXS"}, array in object:register_types.CP_STALLED_STAT2.fields.29 8432 {"bits": [31, 31], "name": "SURF_SYNC_NEEDS_ALL_CLEAN"} array in object:register_types.CP_STALLED_STAT2.fields.30 8437 {"bits": [0, 0], "name": "CE_TO_CSF_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT3.fields.0 8438 {"bits": [1, 1], "name": "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT3.fields.1 8439 {"bits": [2, 2], "name": "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER"}, array in object:register_types.CP_STALLED_STAT3.fields.2 8440 {"bits": [3, 3], "name": "CE_TO_RAM_INIT_NOT_RDY"}, array in object:register_types.CP_STALLED_STAT3.fields.3 8441 {"bits": [4, 4], "name": "CE_TO_RAM_DUMP_NOT_RDY"}, array in object:register_types.CP_STALLED_STAT3.fields.4 8442 {"bits": [5, 5], "name": "CE_TO_RAM_WRITE_NOT_RDY"}, array in object:register_types.CP_STALLED_STAT3.fields.5 8443 {"bits": [6, 6], "name": "CE_TO_INC_FIFO_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT3.fields.6 8444 {"bits": [7, 7], "name": "CE_TO_WR_FIFO_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT3.fields.7 8445 {"bits": [8, 8], "name": "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, array in object:register_types.CP_STALLED_STAT3.fields.8 8446 {"bits": [10, 10], "name": "CE_WAITING_ON_BUFFER_DATA"}, array in object:register_types.CP_STALLED_STAT3.fields.9 8447 {"bits": [11, 11], "name": "CE_WAITING_ON_CE_BUFFER_FLAG"}, array in object:register_types.CP_STALLED_STAT3.fields.10 8448 {"bits": [12, 12], "name": "CE_WAITING_ON_DE_COUNTER"}, array in object:register_types.CP_STALLED_STAT3.fields.11 8449 {"bits": [13, 13], "name": "CE_WAITING_ON_DE_COUNTER_UNDERFLOW"}, array in object:register_types.CP_STALLED_STAT3.fields.12 8450 {"bits": [14, 14], "name": "TCIU_WAITING_ON_FREE"}, array in object:register_types.CP_STALLED_STAT3.fields.13 8451 {"bits": [15, 15], "name": "TCIU_WAITING_ON_TAGS"} array in object:register_types.CP_STALLED_STAT3.fields.14 8456 {"bits": [7, 7], "name": "MIU_RDREQ_BUSY"}, array in object:register_types.CP_STAT.fields.0 8457 {"bits": [8, 8], "name": "MIU_WRREQ_BUSY"}, array in object:register_types.CP_STAT.fields.1 8458 {"bits": [9, 9], "name": "ROQ_RING_BUSY"}, array in object:register_types.CP_STAT.fields.2 8459 {"bits": [10, 10], "name": "ROQ_INDIRECT1_BUSY"}, array in object:register_types.CP_STAT.fields.3 8460 {"bits": [11, 11], "name": "ROQ_INDIRECT2_BUSY"}, array in object:register_types.CP_STAT.fields.4 8461 {"bits": [12, 12], "name": "ROQ_STATE_BUSY"}, array in object:register_types.CP_STAT.fields.5 8462 {"bits": [13, 13], "name": "DC_BUSY"}, array in object:register_types.CP_STAT.fields.6 8463 {"bits": [15, 15], "name": "PFP_BUSY"}, array in object:register_types.CP_STAT.fields.7 8464 {"bits": [16, 16], "name": "MEQ_BUSY"}, array in object:register_types.CP_STAT.fields.8 8465 {"bits": [17, 17], "name": "ME_BUSY"}, array in object:register_types.CP_STAT.fields.9 8466 {"bits": [18, 18], "name": "QUERY_BUSY"}, array in object:register_types.CP_STAT.fields.10 8467 {"bits": [19, 19], "name": "SEMAPHORE_BUSY"}, array in object:register_types.CP_STAT.fields.11 8468 {"bits": [20, 20], "name": "INTERRUPT_BUSY"}, array in object:register_types.CP_STAT.fields.12 8469 {"bits": [21, 21], "name": "SURFACE_SYNC_BUSY"}, array in object:register_types.CP_STAT.fields.13 8470 {"bits": [22, 22], "name": "DMA_BUSY"}, array in object:register_types.CP_STAT.fields.14 8471 {"bits": [23, 23], "name": "RCIU_BUSY"}, array in object:register_types.CP_STAT.fields.15 8472 {"bits": [24, 24], "name": "SCRATCH_RAM_BUSY"}, array in object:register_types.CP_STAT.fields.16 8473 {"bits": [25, 25], "name": "CPC_CPG_BUSY"}, array in object:register_types.CP_STAT.fields.17 8474 {"bits": [26, 26], "name": "CE_BUSY"}, array in object:register_types.CP_STAT.fields.18 8475 {"bits": [27, 27], "name": "TCIU_BUSY"}, array in object:register_types.CP_STAT.fields.19 8476 {"bits": [28, 28], "name": "ROQ_CE_RING_BUSY"}, array in object:register_types.CP_STAT.fields.20 8477 {"bits": [29, 29], "name": "ROQ_CE_INDIRECT1_BUSY"}, array in object:register_types.CP_STAT.fields.21 8478 {"bits": [30, 30], "name": "ROQ_CE_INDIRECT2_BUSY"}, array in object:register_types.CP_STAT.fields.22 8479 {"bits": [31, 31], "name": "CP_BUSY"} array in object:register_types.CP_STAT.fields.23 8484 {"bits": [0, 8], "name": "STQ_CNT"} array in object:register_types.CP_STQ_AVAIL.fields.0 8489 {"bits": [0, 9], "name": "STQ_RPTR"} array in object:register_types.CP_STQ_STAT.fields.0 8494 {"bits": [0, 7], "name": "STQ0_START"}, array in object:register_types.CP_STQ_THRESHOLDS.fields.0 8495 {"bits": [8, 15], "name": "STQ1_START"}, array in object:register_types.CP_STQ_THRESHOLDS.fields.1 8496 {"bits": [16, 23], "name": "STQ2_START"} array in object:register_types.CP_STQ_THRESHOLDS.fields.2 8501 {"bits": [0, 1], "name": "STREAM_OUT_ADDR_SWAP"}, array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.0 8502 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.1 8507 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} array in object:register_types.CP_STRMOUT_CNTL.fields.0 8512 {"bits": [0, 7], "name": "ST_BASE_HI"} array in object:register_types.CP_ST_BASE_HI.fields.0 8517 {"bits": [2, 31], "name": "ST_BASE_LO"} array in object:register_types.CP_ST_BASE_LO.fields.0 8522 {"bits": [0, 19], "name": "ST_BUFSZ"} array in object:register_types.CP_ST_BUFSZ.fields.0 8527 {"bits": [0, 3], "name": "VMID"} array in object:register_types.CP_VMID.fields.0 8532 {"bits": [0, 2], "name": "SRC_STATE_ID"} array in object:register_types.CS_COPY_STATE.fields.0 8537 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.0 8538 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.1 8539 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.2 8540 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.3 8541 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.4 8542 {"bits": [16, 16], "name": "OFFSET_ROUND"} array in object:register_types.DB_ALPHA_TO_MASK.fields.5 8547 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.0 8548 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.1 8549 {"bits": [4, 6], "name": "SAMPLE_RATE"}, array in object:register_types.DB_COUNT_CONTROL.fields.2 8550 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.3 8551 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.4 8552 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.5 8553 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.6 8554 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.7 8555 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} array in object:register_types.DB_COUNT_CONTROL.fields.8 8560 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.0 8561 {"bits": [1, 1], "name": "Z_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.1 8562 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.2 8563 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.3 8564 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.4 8565 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.5 8566 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.6 8567 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, array in object:register_types.DB_DEPTH_CONTROL.fields.7 8568 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, array in object:register_types.DB_DEPTH_CONTROL.fields.8 8569 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} array in object:register_types.DB_DEPTH_CONTROL.fields.9 8574 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"}, array in object:register_types.DB_DEPTH_INFO.fields.0 8575 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.DB_DEPTH_INFO.fields.1 8576 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.DB_DEPTH_INFO.fields.2 8577 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, array in object:register_types.DB_DEPTH_INFO.fields.3 8578 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, array in object:register_types.DB_DEPTH_INFO.fields.4 8579 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, array in object:register_types.DB_DEPTH_INFO.fields.5 8580 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} array in object:register_types.DB_DEPTH_INFO.fields.6 8585 {"bits": [0, 10], "name": "PITCH_TILE_MAX"}, array in object:register_types.DB_DEPTH_SIZE.fields.0 8586 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"} array in object:register_types.DB_DEPTH_SIZE.fields.1 8591 {"bits": [0, 21], "name": "SLICE_TILE_MAX"} array in object:register_types.DB_DEPTH_SLICE.fields.0 8596 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.DB_DEPTH_VIEW.fields.0 8597 {"bits": [13, 23], "name": "SLICE_MAX"}, array in object:register_types.DB_DEPTH_VIEW.fields.1 8598 {"bits": [24, 24], "name": "Z_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.2 8599 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"} array in object:register_types.DB_DEPTH_VIEW.fields.3 8604 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, array in object:register_types.DB_EQAA.fields.0 8605 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, array in object:register_types.DB_EQAA.fields.1 8606 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.2 8607 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.3 8608 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, array in object:register_types.DB_EQAA.fields.4 8609 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, array in object:register_types.DB_EQAA.fields.5 8610 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, array in object:register_types.DB_EQAA.fields.6 8611 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, array in object:register_types.DB_EQAA.fields.7 8612 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, array in object:register_types.DB_EQAA.fields.8 8613 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, array in object:register_types.DB_EQAA.fields.9 8614 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, array in object:register_types.DB_EQAA.fields.10 8615 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} array in object:register_types.DB_EQAA.fields.11 8620 {"bits": [0, 0], "name": "LINEAR"}, array in object:register_types.DB_HTILE_SURFACE.fields.0 8621 {"bits": [1, 1], "name": "FULL_CACHE"}, array in object:register_types.DB_HTILE_SURFACE.fields.1 8622 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, array in object:register_types.DB_HTILE_SURFACE.fields.2 8623 {"bits": [3, 3], "name": "PRELOAD"}, array in object:register_types.DB_HTILE_SURFACE.fields.3 8624 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, array in object:register_types.DB_HTILE_SURFACE.fields.4 8625 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, array in object:register_types.DB_HTILE_SURFACE.fields.5 8626 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"} array in object:register_types.DB_HTILE_SURFACE.fields.6 8631 {"bits": [0, 7], "name": "START_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.0 8632 {"bits": [8, 15], "name": "START_Y"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.1 8633 {"bits": [16, 23], "name": "MAX_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.2 8634 {"bits": [24, 31], "name": "MAX_Y"} array in object:register_types.DB_PRELOAD_CONTROL.fields.3 8639 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.0 8640 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.1 8641 {"bits": [2, 2], "name": "DEPTH_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.2 8642 {"bits": [3, 3], "name": "STENCIL_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.3 8643 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.4 8644 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.5 8645 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.6 8646 {"bits": [7, 7], "name": "COPY_CENTROID"}, array in object:register_types.DB_RENDER_CONTROL.fields.7 8647 {"bits": [8, 11], "name": "COPY_SAMPLE"} array in object:register_types.DB_RENDER_CONTROL.fields.8 8652 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.0 8653 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.1 8654 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.2 8655 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.3 8656 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.4 8657 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.5 8658 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.6 8659 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.7 8660 {"bits": [11, 11], "name": "FORCE_Z_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.8 8661 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.9 8662 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.10 8663 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.11 8664 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.12 8665 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.13 8666 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.14 8667 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.15 8668 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.16 8669 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.17 8670 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.18 8671 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.19 8672 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.20 8673 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.21 8674 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} array in object:register_types.DB_RENDER_OVERRIDE.fields.22 8679 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.0 8680 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.1 8681 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.2 8682 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.3 8683 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.4 8684 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.5 8685 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.6 8686 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.7 8687 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.8 8688 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.9 8689 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.10 8690 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.11 8691 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.12 8692 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.13 8693 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"} array in object:register_types.DB_RENDER_OVERRIDE2.fields.14 8698 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.0 8699 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.1 8700 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.2 8701 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, array in object:register_types.DB_SHADER_CONTROL.fields.3 8702 {"bits": [6, 6], "name": "KILL_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.4 8703 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.5 8704 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.6 8705 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, array in object:register_types.DB_SHADER_CONTROL.fields.7 8706 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, array in object:register_types.DB_SHADER_CONTROL.fields.8 8707 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.9 8708 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.10 8709 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} array in object:register_types.DB_SHADER_CONTROL.fields.11 8714 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0 8715 {"bits": [4, 11], "name": "COMPAREVALUE0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.1 8716 {"bits": [12, 19], "name": "COMPAREMASK0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.2 8717 {"bits": [24, 24], "name": "ENABLE0"} array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.3 8722 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0 8723 {"bits": [4, 11], "name": "COMPAREVALUE1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.1 8724 {"bits": [12, 19], "name": "COMPAREMASK1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.2 8725 {"bits": [24, 24], "name": "ENABLE1"} array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.3 8730 {"bits": [0, 7], "name": "STENCILTESTVAL"}, array in object:register_types.DB_STENCILREFMASK.fields.0 8731 {"bits": [8, 15], "name": "STENCILMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.1 8732 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.2 8733 {"bits": [24, 31], "name": "STENCILOPVAL"} array in object:register_types.DB_STENCILREFMASK.fields.3 8738 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.0 8739 {"bits": [8, 15], "name": "STENCILMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.1 8740 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.2 8741 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} array in object:register_types.DB_STENCILREFMASK_BF.fields.3 8746 {"bits": [0, 7], "name": "CLEAR"} array in object:register_types.DB_STENCIL_CLEAR.fields.0 8751 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.0 8752 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, array in object:register_types.DB_STENCIL_CONTROL.fields.1 8753 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.2 8754 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.3 8755 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.4 8756 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} array in object:register_types.DB_STENCIL_CONTROL.fields.5 8761 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, array in object:register_types.DB_STENCIL_INFO.fields.0 8762 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.DB_STENCIL_INFO.fields.1 8763 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, array in object:register_types.DB_STENCIL_INFO.fields.2 8764 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_STENCIL_INFO.fields.3 8765 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} array in object:register_types.DB_STENCIL_INFO.fields.4 8770 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, array in object:register_types.DB_Z_INFO.fields.0 8771 {"bits": [2, 3], "name": "NUM_SAMPLES"}, array in object:register_types.DB_Z_INFO.fields.1 8772 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.DB_Z_INFO.fields.2 8773 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, array in object:register_types.DB_Z_INFO.fields.3 8774 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_Z_INFO.fields.4 8775 {"bits": [28, 28], "name": "READ_SIZE"}, array in object:register_types.DB_Z_INFO.fields.5 8776 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, array in object:register_types.DB_Z_INFO.fields.6 8777 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} array in object:register_types.DB_Z_INFO.fields.7 8782 {"bits": [0, 17], "name": "DEBUG_INDEX"} array in object:register_types.DEBUG_INDEX.fields.0 8787 {"bits": [0, 2], "name": "NUM_PIPES"}, array in object:register_types.GB_ADDR_CONFIG.fields.0 8788 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.1 8789 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.2 8790 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"}, array in object:register_types.GB_ADDR_CONFIG.fields.3 8791 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.4 8792 {"bits": [20, 22], "name": "NUM_GPUS"}, array in object:register_types.GB_ADDR_CONFIG.fields.5 8793 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.6 8794 {"bits": [28, 29], "name": "ROW_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.7 8795 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"} array in object:register_types.GB_ADDR_CONFIG.fields.8 8800 {"bits": [0, 1], "enum_ref": "GB_TILE_MODE0__MICRO_TILE_MODE", "name": "MICRO_TILE_MODE"}, array in object:register_types.GB_TILE_MODE0.fields.0 8801 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.GB_TILE_MODE0.fields.1 8802 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.GB_TILE_MODE0.fields.2 8803 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.GB_TILE_MODE0.fields.3 8804 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, array in object:register_types.GB_TILE_MODE0.fields.4 8805 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} array in object:register_types.GB_TILE_MODE0.fields.5 8810 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.GB_TILE_MODE10.fields.0 8811 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.GB_TILE_MODE10.fields.1 8812 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.GB_TILE_MODE10.fields.2 8813 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, array in object:register_types.GB_TILE_MODE10.fields.3 8814 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} array in object:register_types.GB_TILE_MODE10.fields.4 8819 {"bits": [0, 7], "name": "READ_TIMEOUT"} array in object:register_types.GRBM_CNTL.fields.0 8824 {"bits": [1, 1], "name": "IGNORE_RDY"}, array in object:register_types.GRBM_DEBUG.fields.0 8825 {"bits": [5, 5], "name": "IGNORE_FAO"}, array in object:register_types.GRBM_DEBUG.fields.1 8826 {"bits": [6, 6], "name": "DISABLE_READ_TIMEOUT"}, array in object:register_types.GRBM_DEBUG.fields.2 8827 {"bits": [7, 7], "name": "SNAPSHOT_FREE_CNTRS"}, array in object:register_types.GRBM_DEBUG.fields.3 8828 {"bits": [8, 11], "name": "HYSTERESIS_GUI_ACTIVE"}, array in object:register_types.GRBM_DEBUG.fields.4 8829 {"bits": [12, 12], "name": "GFX_CLOCK_DOMAIN_OVERRIDE"} array in object:register_types.GRBM_DEBUG.fields.5 8834 {"bits": [0, 5], "name": "GRBM_DEBUG_INDEX"} array in object:register_types.GRBM_DEBUG_CNTL.fields.0 8839 {"bits": [0, 0], "name": "CPF_RDY"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.0 8840 {"bits": [1, 1], "name": "CPG_RDY"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.1 8841 {"bits": [1, 1], "name": "SRBM_RDY"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.2 8842 {"bits": [3, 3], "name": "WD_ME0PIPE0_RDY"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.3 8843 {"bits": [4, 4], "name": "WD_ME0PIPE1_RDY"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.4 8844 {"bits": [6, 6], "name": "SE0SPI_ME0PIPE0_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.5 8845 {"bits": [7, 7], "name": "SE0SPI_ME0PIPE1_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.6 8846 {"bits": [8, 8], "name": "SE1SPI_ME0PIPE0_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.7 8847 {"bits": [9, 9], "name": "GDS_RDY"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.8 8848 {"bits": [9, 9], "name": "SE1SPI_ME0PIPE1_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.9 8849 {"bits": [10, 10], "name": "SE2SPI_ME0PIPE0_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.10 8850 {"bits": [11, 11], "name": "SE2SPI_ME0PIPE1_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.11 8851 {"bits": [12, 12], "name": "SE3SPI_ME0PIPE0_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.12 8852 {"bits": [13, 13], "name": "SE3SPI_ME0PIPE1_RDY0"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.13 8853 {"bits": [14, 14], "name": "SE0SPI_ME0PIPE0_RDY1"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.14 8854 {"bits": [15, 15], "name": "SE0SPI_ME0PIPE1_RDY1"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.15 8855 {"bits": [16, 16], "name": "SE1SPI_ME0PIPE0_RDY1"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.16 8856 {"bits": [17, 17], "name": "SE1SPI_ME0PIPE1_RDY1"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.17 8857 {"bits": [18, 18], "name": "SE2SPI_ME0PIPE0_RDY1"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.18 8858 {"bits": [19, 19], "name": "SE2SPI_ME0PIPE1_RDY1"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.19 8859 {"bits": [20, 20], "name": "SE3SPI_ME0PIPE0_RDY1"}, array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.20 8860 {"bits": [21, 21], "name": "SE3SPI_ME0PIPE1_RDY1"} array in object:register_types.GRBM_DEBUG_SNAPSHOT.fields.21 8865 {"bits": [0, 3], "name": "PREFIX_DELAY_CNT"}, array in object:register_types.GRBM_GFX_CLKEN_CNTL.fields.0 8866 {"bits": [8, 12], "name": "POST_DELAY_CNT"} array in object:register_types.GRBM_GFX_CLKEN_CNTL.fields.1 8871 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.0 8872 {"bits": [8, 15], "name": "SH_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.1 8873 {"bits": [16, 23], "name": "SE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.2 8874 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.3 8875 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.4 8876 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} array in object:register_types.GRBM_GFX_INDEX.fields.5 8881 {"bits": [0, 0], "name": "RDERR_INT_ENABLE"}, array in object:register_types.GRBM_INT_CNTL.fields.0 8882 {"bits": [19, 19], "name": "GUI_IDLE_INT_ENABLE"} array in object:register_types.GRBM_INT_CNTL.fields.1 8887 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.0 8888 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.1 8889 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.2 8890 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.3 8891 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.4 8892 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.5 8893 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.6 8894 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.7 8895 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.8 8896 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.9 8897 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.10 8898 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.11 8899 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.12 8900 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.13 8901 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.14 8902 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.15 8903 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.16 8904 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.17 8905 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.18 8910 {"bits": [0, 3], "name": "REQ_TYPE"}, array in object:register_types.GRBM_PWR_CNTL.fields.0 8911 {"bits": [4, 7], "name": "RSP_TYPE"} array in object:register_types.GRBM_PWR_CNTL.fields.1 8916 {"bits": [2, 17], "name": "READ_ADDRESS"}, array in object:register_types.GRBM_READ_ERROR.fields.0 8917 {"bits": [20, 21], "name": "READ_PIPEID"}, array in object:register_types.GRBM_READ_ERROR.fields.1 8918 {"bits": [22, 23], "name": "READ_MEID"}, array in object:register_types.GRBM_READ_ERROR.fields.2 8919 {"bits": [31, 31], "name": "READ_ERROR"} array in object:register_types.GRBM_READ_ERROR.fields.3 8924 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.0 8925 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.1 8926 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.2 8927 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.3 8928 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.4 8929 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.5 8930 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.6 8931 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.7 8932 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.8 8933 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.9 8934 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.10 8935 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.11 8940 {"bits": [0, 5], "name": "SKEW_TOP_THRESHOLD"}, array in object:register_types.GRBM_SKEW_CNTL.fields.0 8941 {"bits": [6, 11], "name": "SKEW_COUNT"} array in object:register_types.GRBM_SKEW_CNTL.fields.1 8946 {"bits": [0, 0], "name": "SOFT_RESET_CP"}, array in object:register_types.GRBM_SOFT_RESET.fields.0 8947 {"bits": [2, 2], "name": "SOFT_RESET_RLC"}, array in object:register_types.GRBM_SOFT_RESET.fields.1 8948 {"bits": [16, 16], "name": "SOFT_RESET_GFX"}, array in object:register_types.GRBM_SOFT_RESET.fields.2 8949 {"bits": [17, 17], "name": "SOFT_RESET_CPF"}, array in object:register_types.GRBM_SOFT_RESET.fields.3 8950 {"bits": [18, 18], "name": "SOFT_RESET_CPC"}, array in object:register_types.GRBM_SOFT_RESET.fields.4 8951 {"bits": [19, 19], "name": "SOFT_RESET_CPG"} array in object:register_types.GRBM_SOFT_RESET.fields.5 8956 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS.fields.0 8957 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.1 8958 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.2 8959 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.3 8960 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.4 8961 {"bits": [12, 12], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.5 8962 {"bits": [13, 13], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.6 8963 {"bits": [14, 14], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.7 8964 {"bits": [15, 15], "name": "GDS_BUSY"}, array in object:register_types.GRBM_STATUS.fields.8 8965 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.9 8966 {"bits": [17, 17], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS.fields.10 8967 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.11 8968 {"bits": [19, 19], "name": "IA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.12 8969 {"bits": [20, 20], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS.fields.13 8970 {"bits": [21, 21], "name": "WD_BUSY"}, array in object:register_types.GRBM_STATUS.fields.14 8971 {"bits": [22, 22], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.15 8972 {"bits": [23, 23], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.16 8973 {"bits": [24, 24], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS.fields.17 8974 {"bits": [25, 25], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.18 8975 {"bits": [26, 26], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.19 8976 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, array in object:register_types.GRBM_STATUS.fields.20 8977 {"bits": [29, 29], "name": "CP_BUSY"}, array in object:register_types.GRBM_STATUS.fields.21 8978 {"bits": [30, 30], "name": "CB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.22 8979 {"bits": [31, 31], "name": "GUI_ACTIVE"} array in object:register_types.GRBM_STATUS.fields.23 8984 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS2.fields.0 8985 {"bits": [0, 0], "name": "RLC_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.1 8986 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.2 8987 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.3 8988 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.4 8989 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.5 8990 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.6 8991 {"bits": [8, 8], "name": "RLC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.7 8992 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.8 8993 {"bits": [9, 9], "name": "TC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.9 8994 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.10 8995 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.11 8996 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.12 8997 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.13 8998 {"bits": [28, 28], "name": "CPF_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.14 8999 {"bits": [29, 29], "name": "CPC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.15 9000 {"bits": [30, 30], "name": "CPG_BUSY"} array in object:register_types.GRBM_STATUS2.fields.16 9005 {"bits": [1, 1], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.0 9006 {"bits": [2, 2], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.1 9007 {"bits": [22, 22], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.2 9008 {"bits": [23, 23], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.3 9009 {"bits": [24, 24], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.4 9010 {"bits": [25, 25], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.5 9011 {"bits": [26, 26], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.6 9012 {"bits": [27, 27], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.7 9013 {"bits": [29, 29], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.8 9014 {"bits": [30, 30], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.9 9015 {"bits": [31, 31], "name": "CB_BUSY"} array in object:register_types.GRBM_STATUS_SE0.fields.10 9020 {"bits": [0, 7], "name": "WAIT_IDLE_CLOCKS"} array in object:register_types.GRBM_WAIT_IDLE_CLOCKS.fields.0 9025 {"bits": [0, 0], "name": "IA_BUSY"}, array in object:register_types.IA_CNTL_STATUS.fields.0 9026 {"bits": [1, 1], "name": "IA_DMA_BUSY"}, array in object:register_types.IA_CNTL_STATUS.fields.1 9027 {"bits": [2, 2], "name": "IA_DMA_REQ_BUSY"}, array in object:register_types.IA_CNTL_STATUS.fields.2 9028 {"bits": [3, 3], "name": "IA_GRP_BUSY"}, array in object:register_types.IA_CNTL_STATUS.fields.3 9029 {"bits": [4, 4], "name": "IA_ADC_BUSY"} array in object:register_types.IA_CNTL_STATUS.fields.4 9034 {"bits": [0, 5], "name": "IA_DEBUG_INDX"}, array in object:register_types.IA_DEBUG_CNTL.fields.0 9035 {"bits": [6, 6], "name": "IA_DEBUG_SEL_BUS_B"} array in object:register_types.IA_DEBUG_CNTL.fields.1 9040 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.0 9041 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.1 9042 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.2 9043 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.3 9044 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.4 9045 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} array in object:register_types.IA_MULTI_VGT_PARAM.fields.5 9050 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.0 9051 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.1 9052 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.2 9053 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.3 9054 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.4 9059 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.IA_PERFCOUNTER1_SELECT.fields.0 9060 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.IA_PERFCOUNTER1_SELECT.fields.1 9065 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.IA_VMID_OVERRIDE.fields.0 9066 {"bits": [1, 4], "name": "VMID"} array in object:register_types.IA_VMID_OVERRIDE.fields.1 9071 {"bits": [0, 0], "name": "UCP_ENA_0"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.0 9072 {"bits": [1, 1], "name": "UCP_ENA_1"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.1 9073 {"bits": [2, 2], "name": "UCP_ENA_2"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.2 9074 {"bits": [3, 3], "name": "UCP_ENA_3"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.3 9075 {"bits": [4, 4], "name": "UCP_ENA_4"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.4 9076 {"bits": [5, 5], "name": "UCP_ENA_5"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.5 9077 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.6 9078 {"bits": [14, 15], "name": "PS_UCP_MODE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.7 9079 {"bits": [16, 16], "name": "CLIP_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.8 9080 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.9 9081 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.10 9082 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.11 9083 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.12 9084 {"bits": [21, 21], "name": "VTX_KILL_OR"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.13 9085 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.14 9086 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.15 9087 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.16 9088 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.17 9089 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"} array in object:register_types.PA_CL_CLIP_CNTL.fields.18 9094 {"bits": [31, 31], "name": "CL_BUSY"} array in object:register_types.PA_CL_CNTL_STATUS.fields.0 9099 {"bits": [0, 0], "name": "CLIP_VTX_REORDER_ENA"}, array in object:register_types.PA_CL_ENHANCE.fields.0 9100 {"bits": [1, 2], "name": "NUM_CLIP_SEQ"}, array in object:register_types.PA_CL_ENHANCE.fields.1 9101 {"bits": [3, 3], "name": "CLIPPED_PRIM_SEQ_STALL"}, array in object:register_types.PA_CL_ENHANCE.fields.2 9102 {"bits": [4, 4], "name": "VE_NAN_PROC_DISABLE"}, array in object:register_types.PA_CL_ENHANCE.fields.3 9103 {"bits": [5, 5], "name": "XTRA_DEBUG_REG_SEL"}, array in object:register_types.PA_CL_ENHANCE.fields.4 9104 {"bits": [28, 28], "name": "ECO_SPARE3"}, array in object:register_types.PA_CL_ENHANCE.fields.5 9105 {"bits": [29, 29], "name": "ECO_SPARE2"}, array in object:register_types.PA_CL_ENHANCE.fields.6 9106 {"bits": [30, 30], "name": "ECO_SPARE1"}, array in object:register_types.PA_CL_ENHANCE.fields.7 9107 {"bits": [31, 31], "name": "ECO_SPARE0"} array in object:register_types.PA_CL_ENHANCE.fields.8 9112 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.0 9113 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.1 9114 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.2 9115 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.3 9116 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.4 9117 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.5 9118 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.6 9119 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.7 9120 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.8 9121 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.9 9122 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.10 9123 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.11 9124 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.12 9125 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.13 9126 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.14 9127 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} array in object:register_types.PA_CL_NANINF_CNTL.fields.15 9132 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.0 9133 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.1 9134 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.2 9135 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.3 9136 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.4 9137 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.5 9138 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.6 9139 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.7 9140 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.8 9141 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.9 9142 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.10 9143 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.11 9144 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.12 9145 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.13 9146 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.14 9147 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.15 9148 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.16 9149 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.17 9150 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.18 9151 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.19 9152 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.20 9153 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.21 9154 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.22 9155 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.23 9156 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.24 9157 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"} array in object:register_types.PA_CL_VS_OUT_CNTL.fields.25 9162 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.0 9163 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.1 9164 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.2 9165 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.3 9166 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.4 9167 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.5 9168 {"bits": [8, 8], "name": "VTX_XY_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.6 9169 {"bits": [9, 9], "name": "VTX_Z_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.7 9170 {"bits": [10, 10], "name": "VTX_W0_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.8 9171 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} array in object:register_types.PA_CL_VTE_CNTL.fields.9 9176 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.0 9177 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, array in object:register_types.PA_SC_AA_CONFIG.fields.1 9178 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, array in object:register_types.PA_SC_AA_CONFIG.fields.2 9179 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.3 9180 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"} array in object:register_types.PA_SC_AA_CONFIG.fields.4 9185 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.0 9186 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.1 9191 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.0 9192 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.1 9197 {"bits": [0, 3], "name": "S0_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.0 9198 {"bits": [4, 7], "name": "S0_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.1 9199 {"bits": [8, 11], "name": "S1_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.2 9200 {"bits": [12, 15], "name": "S1_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.3 9201 {"bits": [16, 19], "name": "S2_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.4 9202 {"bits": [20, 23], "name": "S2_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.5 9203 {"bits": [24, 27], "name": "S3_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.6 9204 {"bits": [28, 31], "name": "S3_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.7 9209 {"bits": [0, 3], "name": "S4_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.0 9210 {"bits": [4, 7], "name": "S4_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.1 9211 {"bits": [8, 11], "name": "S5_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.2 9212 {"bits": [12, 15], "name": "S5_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.3 9213 {"bits": [16, 19], "name": "S6_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.4 9214 {"bits": [20, 23], "name": "S6_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.5 9215 {"bits": [24, 27], "name": "S7_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.6 9216 {"bits": [28, 31], "name": "S7_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.7 9221 {"bits": [0, 3], "name": "S8_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.0 9222 {"bits": [4, 7], "name": "S8_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.1 9223 {"bits": [8, 11], "name": "S9_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.2 9224 {"bits": [12, 15], "name": "S9_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.3 9225 {"bits": [16, 19], "name": "S10_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.4 9226 {"bits": [20, 23], "name": "S10_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.5 9227 {"bits": [24, 27], "name": "S11_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.6 9228 {"bits": [28, 31], "name": "S11_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.7 9233 {"bits": [0, 3], "name": "S12_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.0 9234 {"bits": [4, 7], "name": "S12_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.1 9235 {"bits": [8, 11], "name": "S13_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.2 9236 {"bits": [12, 15], "name": "S13_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.3 9237 {"bits": [16, 19], "name": "S14_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.4 9238 {"bits": [20, 23], "name": "S14_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.5 9239 {"bits": [24, 27], "name": "S15_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.6 9240 {"bits": [28, 31], "name": "S15_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.7 9245 {"bits": [0, 3], "name": "DISTANCE_0"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.0 9246 {"bits": [4, 7], "name": "DISTANCE_1"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.1 9247 {"bits": [8, 11], "name": "DISTANCE_2"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.2 9248 {"bits": [12, 15], "name": "DISTANCE_3"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.3 9249 {"bits": [16, 19], "name": "DISTANCE_4"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.4 9250 {"bits": [20, 23], "name": "DISTANCE_5"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.5 9251 {"bits": [24, 27], "name": "DISTANCE_6"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.6 9252 {"bits": [28, 31], "name": "DISTANCE_7"} array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.7 9257 {"bits": [0, 3], "name": "DISTANCE_8"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.0 9258 {"bits": [4, 7], "name": "DISTANCE_9"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.1 9259 {"bits": [8, 11], "name": "DISTANCE_10"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.2 9260 {"bits": [12, 15], "name": "DISTANCE_11"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.3 9261 {"bits": [16, 19], "name": "DISTANCE_12"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.4 9262 {"bits": [20, 23], "name": "DISTANCE_13"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.5 9263 {"bits": [24, 27], "name": "DISTANCE_14"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.6 9264 {"bits": [28, 31], "name": "DISTANCE_15"} array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.7 9269 {"bits": [0, 14], "name": "BR_X"}, array in object:register_types.PA_SC_CLIPRECT_0_BR.fields.0 9270 {"bits": [16, 30], "name": "BR_Y"} array in object:register_types.PA_SC_CLIPRECT_0_BR.fields.1 9275 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.0 9276 {"bits": [16, 30], "name": "TL_Y"} array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.1 9281 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} array in object:register_types.PA_SC_CLIPRECT_RULE.fields.0 9286 {"bits": [0, 5], "name": "SC_DEBUG_INDX"} array in object:register_types.PA_SC_DEBUG_CNTL.fields.0 9291 {"bits": [0, 3], "name": "ER_TRI"}, array in object:register_types.PA_SC_EDGERULE.fields.0 9292 {"bits": [4, 7], "name": "ER_POINT"}, array in object:register_types.PA_SC_EDGERULE.fields.1 9293 {"bits": [8, 11], "name": "ER_RECT"}, array in object:register_types.PA_SC_EDGERULE.fields.2 9294 {"bits": [12, 17], "name": "ER_LINE_LR"}, array in object:register_types.PA_SC_EDGERULE.fields.3 9295 {"bits": [18, 23], "name": "ER_LINE_RL"}, array in object:register_types.PA_SC_EDGERULE.fields.4 9296 {"bits": [24, 27], "name": "ER_LINE_TB"}, array in object:register_types.PA_SC_EDGERULE.fields.5 9297 {"bits": [28, 31], "name": "ER_LINE_BT"} array in object:register_types.PA_SC_EDGERULE.fields.6 9302 {"bits": [0, 0], "name": "ENABLE_PA_SC_OUT_OF_ORDER"}, array in object:register_types.PA_SC_ENHANCE.fields.0 9303 {"bits": [1, 1], "name": "DISABLE_SC_DB_TILE_FIX"}, array in object:register_types.PA_SC_ENHANCE.fields.1 9304 {"bits": [2, 2], "name": "DISABLE_AA_MASK_FULL_FIX"}, array in object:register_types.PA_SC_ENHANCE.fields.2 9305 {"bits": [3, 3], "name": "ENABLE_1XMSAA_SAMPLE_LOCATIONS"}, array in object:register_types.PA_SC_ENHANCE.fields.3 9306 {"bits": [4, 4], "name": "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID"}, array in object:register_types.PA_SC_ENHANCE.fields.4 9307 {"bits": [5, 5], "name": "DISABLE_SCISSOR_FIX"}, array in object:register_types.PA_SC_ENHANCE.fields.5 9308 {"bits": [6, 7], "name": "DISABLE_PW_BUBBLE_COLLAPSE"}, array in object:register_types.PA_SC_ENHANCE.fields.6 9309 {"bits": [8, 8], "name": "SEND_UNLIT_STILES_TO_PACKER"}, array in object:register_types.PA_SC_ENHANCE.fields.7 9310 {"bits": [9, 9], "name": "DISABLE_DUALGRAD_PERF_OPTIMIZATION"}, array in object:register_types.PA_SC_ENHANCE.fields.8 9311 {"bits": [10, 10], "name": "DISABLE_SC_PROCESS_RESET_PRIM"}, array in object:register_types.PA_SC_ENHANCE.fields.9 9312 {"bits": [11, 11], "name": "DISABLE_SC_PROCESS_RESET_SUPERTILE"}, array in object:register_types.PA_SC_ENHANCE.fields.10 9313 {"bits": [12, 12], "name": "DISABLE_SC_PROCESS_RESET_TILE"}, array in object:register_types.PA_SC_ENHANCE.fields.11 9314 {"bits": [13, 13], "name": "DISABLE_PA_SC_GUIDANCE"}, array in object:register_types.PA_SC_ENHANCE.fields.12 9315 {"bits": [14, 14], "name": "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS"}, array in object:register_types.PA_SC_ENHANCE.fields.13 9316 {"bits": [15, 15], "name": "ENABLE_MULTICYCLE_BUBBLE_FREEZE"}, array in object:register_types.PA_SC_ENHANCE.fields.14 9317 {"bits": [16, 16], "name": "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE"}, array in object:register_types.PA_SC_ENHANCE.fields.15 9318 {"bits": [17, 17], "name": "ENABLE_OUT_OF_ORDER_POLY_MODE"}, array in object:register_types.PA_SC_ENHANCE.fields.16 9319 {"bits": [18, 18], "name": "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST"}, array in object:register_types.PA_SC_ENHANCE.fields.17 9320 {"bits": [19, 19], "name": "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING"}, array in object:register_types.PA_SC_ENHANCE.fields.18 9321 {"bits": [20, 20], "name": "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY"}, array in object:register_types.PA_SC_ENHANCE.fields.19 9322 {"bits": [21, 21], "name": "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING"}, array in object:register_types.PA_SC_ENHANCE.fields.20 9323 {"bits": [22, 22], "name": "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING"}, array in object:register_types.PA_SC_ENHANCE.fields.21 9324 {"bits": [23, 23], "name": "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS"}, array in object:register_types.PA_SC_ENHANCE.fields.22 9325 {"bits": [24, 24], "name": "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID"}, array in object:register_types.PA_SC_ENHANCE.fields.23 9326 {"bits": [30, 30], "name": "ECO_SPARE1"}, array in object:register_types.PA_SC_ENHANCE.fields.24 9327 {"bits": [31, 31], "name": "ECO_SPARE0"} array in object:register_types.PA_SC_ENHANCE.fields.25 9332 {"bits": [0, 7], "name": "DEPTH"} array in object:register_types.PA_SC_FIFO_DEPTH_CNTL.fields.0 9337 {"bits": [0, 5], "name": "SC_FRONTEND_PRIM_FIFO_SIZE"}, array in object:register_types.PA_SC_FIFO_SIZE.fields.0 9338 {"bits": [6, 14], "name": "SC_BACKEND_PRIM_FIFO_SIZE"}, array in object:register_types.PA_SC_FIFO_SIZE.fields.1 9339 {"bits": [15, 20], "name": "SC_HIZ_TILE_FIFO_SIZE"}, array in object:register_types.PA_SC_FIFO_SIZE.fields.2 9340 {"bits": [23, 31], "name": "SC_EARLYZ_TILE_FIFO_SIZE"} array in object:register_types.PA_SC_FIFO_SIZE.fields.3 9345 {"bits": [0, 15], "name": "FORCE_EOV_MAX_CLK_CNT"}, array in object:register_types.PA_SC_FORCE_EOV_MAX_CNTS.fields.0 9346 {"bits": [16, 31], "name": "FORCE_EOV_MAX_REZ_CNT"} array in object:register_types.PA_SC_FORCE_EOV_MAX_CNTS.fields.1 9351 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.0 9352 {"bits": [16, 30], "name": "TL_Y"}, array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.1 9353 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.2 9358 {"bits": [0, 5], "name": "SC_DB_TILE_IF_FIFO_SIZE"}, array in object:register_types.PA_SC_IF_FIFO_SIZE.fields.0 9359 {"bits": [6, 11], "name": "SC_DB_QUAD_IF_FIFO_SIZE"}, array in object:register_types.PA_SC_IF_FIFO_SIZE.fields.1 9360 {"bits": [12, 17], "name": "SC_SPI_IF_FIFO_SIZE"}, array in object:register_types.PA_SC_IF_FIFO_SIZE.fields.2 9361 {"bits": [18, 23], "name": "SC_BCI_IF_FIFO_SIZE"} array in object:register_types.PA_SC_IF_FIFO_SIZE.fields.3 9366 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, array in object:register_types.PA_SC_LINE_CNTL.fields.0 9367 {"bits": [10, 10], "name": "LAST_PIXEL"}, array in object:register_types.PA_SC_LINE_CNTL.fields.1 9368 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.2 9369 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"} array in object:register_types.PA_SC_LINE_CNTL.fields.3 9374 {"bits": [0, 15], "name": "LINE_PATTERN"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.0 9375 {"bits": [16, 23], "name": "REPEAT_COUNT"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.1 9376 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.2 9377 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} array in object:register_types.PA_SC_LINE_STIPPLE.fields.3 9382 {"bits": [0, 3], "name": "CURRENT_PTR"}, array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.0 9383 {"bits": [8, 15], "name": "CURRENT_COUNT"} array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.1 9388 {"bits": [0, 0], "name": "MSAA_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.0 9389 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.1 9390 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.2 9391 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"} array in object:register_types.PA_SC_MODE_CNTL_0.fields.3 9396 {"bits": [0, 0], "name": "WALK_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.0 9397 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.1 9398 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.2 9399 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.3 9400 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.4 9401 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.5 9402 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.6 9403 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.7 9404 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.8 9405 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.9 9406 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.10 9407 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.11 9408 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.12 9409 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.13 9410 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.14 9411 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.15 9412 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.16 9413 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.17 9414 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.18 9415 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.19 9416 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.20 9417 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.21 9418 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.22 9419 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} array in object:register_types.PA_SC_MODE_CNTL_1.fields.23 9424 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.PA_SC_PERFCOUNTER0_SELECT.fields.0 9425 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.PA_SC_PERFCOUNTER0_SELECT.fields.1 9426 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.PA_SC_PERFCOUNTER0_SELECT.fields.2 9431 {"bits": [0, 8], "name": "PERF_SEL"} array in object:register_types.PA_SC_PERFCOUNTER1_SELECT.fields.0 9436 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.0 9437 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.1 9438 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.2 9439 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.3 9440 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.4 9441 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.5 9442 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.6 9443 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.7 9444 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.8 9445 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.9 9446 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.10 9447 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.11 9448 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.12 9449 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.13 9450 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG.fields.14 9455 {"bits": [0, 15], "name": "BR_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.0 9456 {"bits": [16, 31], "name": "BR_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.1 9461 {"bits": [0, 15], "name": "TL_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.0 9462 {"bits": [16, 31], "name": "TL_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.1 9467 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, array in object:register_types.PA_SC_WINDOW_OFFSET.fields.0 9468 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} array in object:register_types.PA_SC_WINDOW_OFFSET.fields.1 9473 {"bits": [31, 31], "name": "SU_BUSY"} array in object:register_types.PA_SU_CNTL_STATUS.fields.0 9478 {"bits": [0, 4], "name": "SU_DEBUG_INDX"} array in object:register_types.PA_SU_DEBUG_CNTL.fields.0 9483 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.0 9484 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.1 9489 {"bits": [0, 15], "name": "WIDTH"} array in object:register_types.PA_SU_LINE_CNTL.fields.0 9494 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.0 9495 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.1 9496 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.2 9497 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.3 9502 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} array in object:register_types.PA_SU_LINE_STIPPLE_VALUE.fields.0 9507 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} array in object:register_types.PA_SU_PERFCOUNTER0_HI.fields.0 9512 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.0 9513 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.1 9514 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.2 9519 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.0 9520 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.1 9525 {"bits": [0, 15], "name": "MIN_SIZE"}, array in object:register_types.PA_SU_POINT_MINMAX.fields.0 9526 {"bits": [16, 31], "name": "MAX_SIZE"} array in object:register_types.PA_SU_POINT_MINMAX.fields.1 9531 {"bits": [0, 15], "name": "HEIGHT"}, array in object:register_types.PA_SU_POINT_SIZE.fields.0 9532 {"bits": [16, 31], "name": "WIDTH"} array in object:register_types.PA_SU_POINT_SIZE.fields.1 9537 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.0 9538 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.1 9543 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.0 9544 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.1 9545 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.2 9546 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.3 9547 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.4 9548 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.5 9549 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.6 9550 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.7 9551 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.8 9552 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.9 9553 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.10 9558 {"bits": [0, 0], "name": "CULL_FRONT"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.0 9559 {"bits": [1, 1], "name": "CULL_BACK"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.1 9560 {"bits": [2, 2], "name": "FACE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.2 9561 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.3 9562 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ array in object:register_types.PA_SU_SC_MODE_CNTL.fields.4 9563 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE array in object:register_types.PA_SU_SC_MODE_CNTL.fields.5 9564 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.6 9565 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.7 9566 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.8 9567 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.9 9568 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.10 9569 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.11 9570 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"} array in object:register_types.PA_SU_SC_MODE_CNTL.fields.12 9575 {"bits": [0, 0], "name": "PIX_CENTER"}, array in object:register_types.PA_SU_VTX_CNTL.fields.0 9576 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, array in object:register_types.PA_SU_VTX_CNTL.fields.1 9577 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} array in object:register_types.PA_SU_VTX_CNTL.fields.2 9582 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, array in object:register_types.SCRATCH_UMSK.fields.0 9583 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} array in object:register_types.SCRATCH_UMSK.fields.1 9588 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.0 9589 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.1 9590 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.2 9591 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.3 9592 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, array in object:register_types.SPI_BARYC_CNTL.fields.4 9593 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, array in object:register_types.SPI_BARYC_CNTL.fields.5 9594 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} array in object:register_types.SPI_BARYC_CNTL.fields.6 9599 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, array in object:register_types.SPI_CONFIG_CNTL.fields.0 9600 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, array in object:register_types.SPI_CONFIG_CNTL.fields.1 9601 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.2 9602 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.3 9603 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, array in object:register_types.SPI_CONFIG_CNTL.fields.4 9604 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"} array in object:register_types.SPI_CONFIG_CNTL.fields.5 9609 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.0 9610 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.1 9611 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.2 9612 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.3 9613 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.4 9614 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.5 9615 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} array in object:register_types.SPI_INTERP_CONTROL_0.fields.6 9620 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.0 9621 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.1 9622 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.2 9623 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.3 9624 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.4 9625 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.5 9626 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.6 9627 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.7 9628 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.8 9629 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.9 9630 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.10 9631 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.11 9632 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.12 9633 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.13 9634 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, array in object:register_types.SPI_PS_INPUT_ADDR.fields.14 9635 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} array in object:register_types.SPI_PS_INPUT_ADDR.fields.15 9640 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.0 9641 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.1 9642 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.2 9643 {"bits": [13, 16], "name": "CYL_WRAP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.3 9644 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.4 9645 {"bits": [18, 18], "name": "DUP"} array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.5 9650 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.0 9651 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.1 9652 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.2 9653 {"bits": [18, 18], "name": "DUP"} array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.3 9658 {"bits": [0, 5], "name": "NUM_INTERP"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.0 9659 {"bits": [6, 6], "name": "PARAM_GEN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.1 9660 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} array in object:register_types.SPI_PS_IN_CONTROL.fields.2 9665 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.0 9666 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.1 9667 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.2 9668 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.3 9669 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.4 9670 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.5 9671 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.6 9672 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_COL_FORMAT.fields.7 9677 {"bits": [0, 7], "name": "MEM_BASE"} array in object:register_types.SPI_SHADER_PGM_HI_ES.fields.0 9682 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.0 9683 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.1 9684 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.2 9685 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.3 9686 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.4 9687 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.5 9688 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.6 9689 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.7 9690 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.8 9691 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.9 9692 {"bits": [27, 29], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.10 9693 {"bits": [30, 30], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.11 9698 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.0 9699 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.1 9700 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.2 9701 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3 9702 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.4 9703 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.5 9704 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.6 9705 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.7 9706 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.8 9707 {"bits": [25, 27], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.9 9708 {"bits": [28, 28], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.10 9713 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.0 9714 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.1 9715 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.2 9716 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3 9717 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.4 9718 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.5 9719 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.6 9720 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.7 9721 {"bits": [24, 26], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.8 9722 {"bits": [27, 27], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.9 9727 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.0 9728 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.1 9729 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.2 9730 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3 9731 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.4 9732 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.5 9733 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.6 9734 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.7 9735 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.8 9736 {"bits": [26, 28], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.9 9737 {"bits": [29, 29], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.10 9742 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.0 9743 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.1 9744 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.2 9745 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3 9746 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.4 9747 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.5 9748 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.6 9749 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.7 9750 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.8 9751 {"bits": [25, 27], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.9 9752 {"bits": [28, 28], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.10 9757 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES.fields.0 9758 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES.fields.1 9759 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES.fields.2 9760 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES.fields.3 9761 {"bits": [8, 14], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES.fields.4 9762 {"bits": [20, 28], "name": "LDS_SIZE"} array in object:register_types.SPI_SHADER_PGM_RSRC2_ES.fields.5 9767 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.0 9768 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.1 9769 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.2 9770 {"bits": [7, 13], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3 9775 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.0 9776 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.1 9777 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.2 9778 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.3 9779 {"bits": [8, 8], "name": "TG_SIZE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.4 9780 {"bits": [9, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5 9785 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS.fields.0 9786 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS.fields.1 9787 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS.fields.2 9788 {"bits": [7, 15], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS.fields.3 9789 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_LS.fields.4 9794 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.0 9795 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.1 9796 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.2 9797 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.3 9798 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.4 9799 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5 9804 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.0 9805 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.1 9806 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.2 9807 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.3 9808 {"bits": [8, 8], "name": "SO_BASE0_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.4 9809 {"bits": [9, 9], "name": "SO_BASE1_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.5 9810 {"bits": [10, 10], "name": "SO_BASE2_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.6 9811 {"bits": [11, 11], "name": "SO_BASE3_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.7 9812 {"bits": [12, 12], "name": "SO_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.8 9813 {"bits": [13, 19], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9 9818 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.0 9819 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.1 9820 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.2 9821 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_POS_FORMAT.fields.3 9826 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_Z_FORMAT.fields.0 9831 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.0 9832 {"bits": [6, 6], "name": "VS_HALF_PACK"} array in object:register_types.SPI_VS_OUT_CONFIG.fields.1 9837 {"bits": [0, 0], "name": "INST_INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.0 9838 {"bits": [1, 1], "name": "DATA_INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.1 9839 {"bits": [2, 2], "name": "INVALIDATE_VOLATILE"} array in object:register_types.SQC_CACHES.fields.2 9844 {"bits": [0, 1], "name": "INST_CACHE_SIZE"}, array in object:register_types.SQC_CONFIG.fields.0 9845 {"bits": [2, 3], "name": "DATA_CACHE_SIZE"}, array in object:register_types.SQC_CONFIG.fields.1 9846 {"bits": [4, 5], "name": "MISS_FIFO_DEPTH"}, array in object:register_types.SQC_CONFIG.fields.2 9847 {"bits": [6, 6], "name": "HIT_FIFO_DEPTH"}, array in object:register_types.SQC_CONFIG.fields.3 9848 {"bits": [7, 7], "name": "FORCE_ALWAYS_MISS"}, array in object:register_types.SQC_CONFIG.fields.4 9849 {"bits": [8, 8], "name": "FORCE_IN_ORDER"}, array in object:register_types.SQC_CONFIG.fields.5 9850 {"bits": [9, 9], "name": "IDENTITY_HASH_BANK"}, array in object:register_types.SQC_CONFIG.fields.6 9851 {"bits": [10, 10], "name": "IDENTITY_HASH_SET"}, array in object:register_types.SQC_CONFIG.fields.7 9852 {"bits": [11, 11], "name": "PER_VMID_INV_DISABLE"} array in object:register_types.SQC_CONFIG.fields.8 9857 {"bits": [0, 7], "name": "INST_SEC"}, array in object:register_types.SQC_SECDED_CNT.fields.0 9858 {"bits": [8, 15], "name": "INST_DED"}, array in object:register_types.SQC_SECDED_CNT.fields.1 9859 {"bits": [16, 23], "name": "DATA_SEC"}, array in object:register_types.SQC_SECDED_CNT.fields.2 9860 {"bits": [24, 31], "name": "DATA_DED"} array in object:register_types.SQC_SECDED_CNT.fields.3 9865 {"bits": [0, 15], "name": "FORCE_CU_ON_SH0"}, array in object:register_types.SQ_ALU_CLK_CTRL.fields.0 9866 {"bits": [16, 31], "name": "FORCE_CU_ON_SH1"} array in object:register_types.SQ_ALU_CLK_CTRL.fields.1 9871 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.0 9872 {"bits": [16, 29], "name": "STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.1 9873 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.2 9874 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} array in object:register_types.SQ_BUF_RSRC_WORD1.fields.3 9879 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.0 9880 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.1 9881 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.2 9882 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.3 9883 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.4 9884 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.5 9885 {"bits": [19, 20], "name": "ELEMENT_SIZE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.6 9886 {"bits": [21, 22], "name": "INDEX_STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.7 9887 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.8 9888 {"bits": [24, 24], "name": "ATC"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.9 9889 {"bits": [25, 25], "name": "HASH_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.10 9890 {"bits": [26, 26], "name": "HEAP"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.11 9891 {"bits": [27, 29], "name": "MTYPE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.12 9892 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} array in object:register_types.SQ_BUF_RSRC_WORD3.fields.13 9897 {"bits": [0, 7], "name": "UNUSED"}, array in object:register_types.SQ_CONFIG.fields.0 9898 {"bits": [8, 8], "name": "DEBUG_EN"}, array in object:register_types.SQ_CONFIG.fields.1 9899 {"bits": [9, 9], "name": "DISABLE_SCA_BYPASS"}, array in object:register_types.SQ_CONFIG.fields.2 9900 {"bits": [10, 10], "name": "DISABLE_IB_DEP_CHECK"}, array in object:register_types.SQ_CONFIG.fields.3 9901 {"bits": [11, 11], "name": "ENABLE_SOFT_CLAUSE"}, array in object:register_types.SQ_CONFIG.fields.4 9902 {"bits": [12, 12], "name": "EARLY_TA_DONE_DISABLE"}, array in object:register_types.SQ_CONFIG.fields.5 9903 {"bits": [13, 13], "name": "DUA_FLAT_LOCK_ENABLE"}, array in object:register_types.SQ_CONFIG.fields.6 9904 {"bits": [14, 14], "name": "DUA_LDS_BYPASS_DISABLE"}, array in object:register_types.SQ_CONFIG.fields.7 9905 {"bits": [15, 15], "name": "DUA_FLAT_LDS_PINGPONG_DISABLE"} array in object:register_types.SQ_CONFIG.fields.8 9910 {"bits": [0, 0], "name": "BUSY"}, array in object:register_types.SQ_DEBUG_STS_GLOBAL.fields.0 9911 {"bits": [1, 1], "name": "INTERRUPT_MSG_BUSY"}, array in object:register_types.SQ_DEBUG_STS_GLOBAL.fields.1 9912 {"bits": [4, 15], "name": "WAVE_LEVEL_SH0"}, array in object:register_types.SQ_DEBUG_STS_GLOBAL.fields.2 9913 {"bits": [16, 27], "name": "WAVE_LEVEL_SH1"} array in object:register_types.SQ_DEBUG_STS_GLOBAL.fields.3 9918 {"bits": [0, 5], "name": "LDS_DED"}, array in object:register_types.SQ_DED_CNT.fields.0 9919 {"bits": [8, 12], "name": "SGPR_DED"}, array in object:register_types.SQ_DED_CNT.fields.1 9920 {"bits": [16, 24], "name": "VGPR_DED"} array in object:register_types.SQ_DED_CNT.fields.2 9925 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_DED_INFO.fields.0 9926 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_DED_INFO.fields.1 9927 {"bits": [6, 8], "name": "SOURCE"}, array in object:register_types.SQ_DED_INFO.fields.2 9928 {"bits": [9, 12], "name": "VM_ID"} array in object:register_types.SQ_DED_INFO.fields.3 9933 {"bits": [0, 3], "name": "INTERRUPT_FIFO_SIZE"}, array in object:register_types.SQ_FIFO_SIZES.fields.0 9934 {"bits": [8, 11], "name": "TTRACE_FIFO_SIZE"}, array in object:register_types.SQ_FIFO_SIZES.fields.1 9935 {"bits": [16, 17], "name": "EXPORT_BUF_SIZE"}, array in object:register_types.SQ_FIFO_SIZES.fields.2 9936 {"bits": [18, 19], "name": "VMEM_DATA_FIFO_SIZE"} array in object:register_types.SQ_FIFO_SIZES.fields.3 9941 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.0 9942 {"bits": [8, 19], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.1 9943 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.2 9944 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.3 9945 {"bits": [30, 31], "name": "MTYPE"} array in object:register_types.SQ_IMG_RSRC_WORD1.fields.4 9950 {"bits": [0, 13], "name": "WIDTH"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.0 9951 {"bits": [14, 27], "name": "HEIGHT"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.1 9952 {"bits": [28, 30], "name": "PERF_MOD"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.2 9953 {"bits": [31, 31], "name": "INTERLACED"} array in object:register_types.SQ_IMG_RSRC_WORD2.fields.3 9958 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.0 9959 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.1 9960 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.2 9961 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.3 9962 {"bits": [12, 15], "name": "BASE_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.4 9963 {"bits": [16, 19], "name": "LAST_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.5 9964 {"bits": [20, 24], "name": "TILING_INDEX"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.6 9965 {"bits": [25, 25], "name": "POW2_PAD"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.7 9966 {"bits": [26, 26], "name": "MTYPE"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.8 9967 {"bits": [27, 27], "name": "ATC"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.9 9968 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} array in object:register_types.SQ_IMG_RSRC_WORD3.fields.10 9973 {"bits": [0, 12], "name": "DEPTH"}, array in object:register_types.SQ_IMG_RSRC_WORD4.fields.0 9974 {"bits": [13, 26], "name": "PITCH"} array in object:register_types.SQ_IMG_RSRC_WORD4.fields.1 9979 {"bits": [0, 12], "name": "BASE_ARRAY"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.0 9980 {"bits": [13, 25], "name": "LAST_ARRAY"} array in object:register_types.SQ_IMG_RSRC_WORD5.fields.1 9985 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.0 9986 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.1 9987 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.2 9988 {"bits": [21, 31], "name": "UNUNSED"} array in object:register_types.SQ_IMG_RSRC_WORD6.fields.3 9993 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.0 9994 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.1 9995 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.2 9996 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.3 9997 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.4 9998 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.5 9999 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.6 10000 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.7 10001 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.8 10002 {"bits": [21, 26], "name": "ANISO_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.9 10003 {"bits": [27, 27], "name": "TRUNC_COORD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.10 10004 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.11 10005 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"} array in object:register_types.SQ_IMG_SAMP_WORD0.fields.12 10010 {"bits": [0, 11], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.0 10011 {"bits": [12, 23], "name": "MAX_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.1 10012 {"bits": [24, 27], "name": "PERF_MIP"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.2 10013 {"bits": [28, 31], "name": "PERF_Z"} array in object:register_types.SQ_IMG_SAMP_WORD1.fields.3 10018 {"bits": [0, 13], "name": "LOD_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.0 10019 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.1 10020 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.2 10021 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.3 10022 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.4 10023 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.5 10024 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.6 10025 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.7 10026 {"bits": [30, 30], "name": "FILTER_PREC_FIX"} array in object:register_types.SQ_IMG_SAMP_WORD2.fields.8 10031 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.0 10032 {"bits": [29, 29], "name": "UPGRADED_DEPTH"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.1 10033 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} array in object:register_types.SQ_IMG_SAMP_WORD3.fields.2 10038 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_IND_INDEX.fields.0 10039 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_IND_INDEX.fields.1 10040 {"bits": [6, 11], "name": "THREAD_ID"}, array in object:register_types.SQ_IND_INDEX.fields.2 10041 {"bits": [12, 12], "name": "AUTO_INCR"}, array in object:register_types.SQ_IND_INDEX.fields.3 10042 {"bits": [13, 13], "name": "FORCE_READ"}, array in object:register_types.SQ_IND_INDEX.fields.4 10043 {"bits": [14, 14], "name": "READ_TIMEOUT"}, array in object:register_types.SQ_IND_INDEX.fields.5 10044 {"bits": [15, 15], "name": "UNINDEXED"}, array in object:register_types.SQ_IND_INDEX.fields.6 10045 {"bits": [16, 31], "name": "INDEX"} array in object:register_types.SQ_IND_INDEX.fields.7 10050 {"bits": [0, 0], "name": "THREAD_TRACE"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.0 10051 {"bits": [1, 1], "name": "WLT"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.1 10052 {"bits": [2, 2], "name": "THREAD_TRACE_BUF_FULL"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.2 10053 {"bits": [3, 3], "name": "REG_TIMESTAMP"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.3 10054 {"bits": [4, 4], "name": "CMD_TIMESTAMP"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.4 10055 {"bits": [5, 5], "name": "HOST_CMD_OVERFLOW"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.5 10056 {"bits": [6, 6], "name": "HOST_REG_OVERFLOW"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.6 10057 {"bits": [7, 7], "name": "IMMED_OVERFLOW"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.7 10058 {"bits": [25, 25], "name": "SE_ID"}, array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.8 10059 {"bits": [26, 27], "name": "ENCODING"} array in object:register_types.SQ_INTERRUPT_WORD_AUTO.fields.9 10064 {"bits": [0, 0], "name": "START"}, array in object:register_types.SQ_LB_CTR_CTRL.fields.0 10065 {"bits": [1, 1], "name": "LOAD"}, array in object:register_types.SQ_LB_CTR_CTRL.fields.1 10066 {"bits": [2, 2], "name": "CLEAR"} array in object:register_types.SQ_LB_CTR_CTRL.fields.2 10071 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.0 10072 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.1 10073 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.2 10074 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.3 10075 {"bits": [24, 27], "name": "SIMD_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.4 10076 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.5 10081 {"bits": [0, 0], "name": "PS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.0 10082 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1 10083 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2 10084 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3 10085 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4 10086 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5 10087 {"bits": [6, 6], "name": "CS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.6 10088 {"bits": [8, 12], "name": "CNTR_RATE"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.7 10089 {"bits": [13, 13], "name": "DISABLE_FLUSH"} array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.8 10094 {"bits": [0, 13], "name": "MIN_POWER"}, array in object:register_types.SQ_POWER_THROTTLE.fields.0 10095 {"bits": [16, 29], "name": "MAX_POWER"}, array in object:register_types.SQ_POWER_THROTTLE.fields.1 10096 {"bits": [30, 31], "name": "PHASE_OFFSET"} array in object:register_types.SQ_POWER_THROTTLE.fields.2 10101 {"bits": [0, 13], "name": "MAX_POWER_DELTA"}, array in object:register_types.SQ_POWER_THROTTLE2.fields.0 10102 {"bits": [16, 25], "name": "SHORT_TERM_INTERVAL_SIZE"}, array in object:register_types.SQ_POWER_THROTTLE2.fields.1 10103 {"bits": [27, 30], "name": "LONG_TERM_INTERVAL_RATIO"}, array in object:register_types.SQ_POWER_THROTTLE2.fields.2 10104 {"bits": [31, 31], "name": "USE_REF_CLOCK"} array in object:register_types.SQ_POWER_THROTTLE2.fields.3 10109 {"bits": [0, 6], "name": "RET"}, array in object:register_types.SQ_RANDOM_WAVE_PRI.fields.0 10110 {"bits": [7, 9], "name": "RUI"}, array in object:register_types.SQ_RANDOM_WAVE_PRI.fields.1 10111 {"bits": [10, 20], "name": "RNG"} array in object:register_types.SQ_RANDOM_WAVE_PRI.fields.2 10116 {"bits": [0, 5], "name": "SRBM_CREDITS"}, array in object:register_types.SQ_REG_CREDITS.fields.0 10117 {"bits": [8, 11], "name": "CMD_CREDITS"}, array in object:register_types.SQ_REG_CREDITS.fields.1 10118 {"bits": [28, 28], "name": "REG_BUSY"}, array in object:register_types.SQ_REG_CREDITS.fields.2 10119 {"bits": [29, 29], "name": "SRBM_OVERFLOW"}, array in object:register_types.SQ_REG_CREDITS.fields.3 10120 {"bits": [30, 30], "name": "IMMED_OVERFLOW"}, array in object:register_types.SQ_REG_CREDITS.fields.4 10121 {"bits": [31, 31], "name": "CMD_OVERFLOW"} array in object:register_types.SQ_REG_CREDITS.fields.5 10126 {"bits": [0, 5], "name": "LDS_SEC"}, array in object:register_types.SQ_SEC_CNT.fields.0 10127 {"bits": [8, 12], "name": "SGPR_SEC"}, array in object:register_types.SQ_SEC_CNT.fields.1 10128 {"bits": [16, 24], "name": "VGPR_SEC"} array in object:register_types.SQ_SEC_CNT.fields.2 10133 {"bits": [31, 31], "name": "RESET_BUFFER"} array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.0 10138 {"bits": [0, 2], "name": "HIWATER"} array in object:register_types.SQ_THREAD_TRACE_HIWATER.fields.0 10143 {"bits": [0, 4], "name": "CU_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.0 10144 {"bits": [5, 5], "name": "SH_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.1 10145 {"bits": [7, 7], "name": "REG_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.2 10146 {"bits": [12, 13], "name": "VM_ID_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.3 10147 {"bits": [14, 14], "name": "SPI_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.4 10148 {"bits": [15, 15], "name": "SQ_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.5 10149 {"bits": [16, 31], "name": "RANDOM_SEED"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.6 10150 {"bits": [16, 31], "name": "RANDOM_SEED"} array in object:register_types.SQ_THREAD_TRACE_MASK.fields.7 10155 {"bits": [0, 2], "name": "MASK_PS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.0 10156 {"bits": [3, 5], "name": "MASK_VS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.1 10157 {"bits": [6, 8], "name": "MASK_GS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.2 10158 {"bits": [9, 11], "name": "MASK_ES"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.3 10159 {"bits": [12, 14], "name": "MASK_HS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.4 10160 {"bits": [15, 17], "name": "MASK_LS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.5 10161 {"bits": [18, 20], "name": "MASK_CS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.6 10162 {"bits": [21, 22], "name": "MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.7 10163 {"bits": [23, 24], "name": "CAPTURE_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.8 10164 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.9 10165 {"bits": [26, 26], "name": "PRIV"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.10 10166 {"bits": [27, 28], "name": "ISSUE_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.11 10167 {"bits": [29, 29], "name": "TEST_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.12 10168 {"bits": [30, 30], "name": "INTERRUPT_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.13 10169 {"bits": [31, 31], "name": "WRAP"} array in object:register_types.SQ_THREAD_TRACE_MODE.fields.14 10174 {"bits": [0, 15], "name": "SH0_MASK"}, array in object:register_types.SQ_THREAD_TRACE_PERF_MASK.fields.0 10175 {"bits": [16, 31], "name": "SH1_MASK"} array in object:register_types.SQ_THREAD_TRACE_PERF_MASK.fields.1 10180 {"bits": [0, 21], "name": "SIZE"} array in object:register_types.SQ_THREAD_TRACE_SIZE.fields.0 10185 {"bits": [0, 2], "name": "FINISH_PENDING"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.0 10186 {"bits": [16, 18], "name": "FINISH_DONE"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.1 10187 {"bits": [29, 29], "name": "NEW_BUF"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.2 10188 {"bits": [30, 30], "name": "BUSY"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.3 10189 {"bits": [31, 31], "name": "FULL"} array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.4 10194 {"bits": [0, 15], "name": "TOKEN_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0 10195 {"bits": [16, 23], "name": "REG_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.1 10196 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.2 10201 {"bits": [0, 29], "name": "WPTR"}, array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.0 10202 {"bits": [30, 31], "name": "READ_OFFSET"} array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.1 10207 {"bits": [0, 5], "name": "VGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.0 10208 {"bits": [8, 13], "name": "VGPR_SIZE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.1 10209 {"bits": [16, 21], "name": "SGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.2 10210 {"bits": [24, 27], "name": "SGPR_SIZE"} array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.3 10215 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.0 10216 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.1 10217 {"bits": [6, 7], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.2 10218 {"bits": [8, 11], "name": "CU_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.3 10219 {"bits": [12, 12], "name": "SH_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.4 10220 {"bits": [13, 13], "name": "SE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.5 10221 {"bits": [16, 19], "name": "TG_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.6 10222 {"bits": [20, 23], "name": "VM_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.7 10223 {"bits": [24, 26], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.8 10224 {"bits": [27, 29], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.9 10225 {"bits": [30, 31], "name": "ME_ID"} array in object:register_types.SQ_WAVE_HW_ID.fields.10 10230 {"bits": [0, 2], "name": "IBUF_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.0 10231 {"bits": [3, 3], "name": "PC_INVALID"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.1 10232 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.2 10233 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.3 10234 {"bits": [8, 9], "name": "IBUF_RPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.4 10235 {"bits": [10, 11], "name": "IBUF_WPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.5 10236 {"bits": [16, 18], "name": "INST_STR_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.6 10237 {"bits": [19, 21], "name": "MISC_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.7 10238 {"bits": [22, 23], "name": "ECC_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.8 10239 {"bits": [24, 24], "name": "IS_HYB"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.9 10240 {"bits": [25, 26], "name": "HYB_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.10 10241 {"bits": [27, 27], "name": "KILL"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.11 10242 {"bits": [28, 28], "name": "NEED_KILL_IFETCH"} array in object:register_types.SQ_WAVE_IB_DBG0.fields.12 10247 {"bits": [0, 3], "name": "VM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.0 10248 {"bits": [4, 6], "name": "EXP_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.1 10249 {"bits": [8, 12], "name": "LGKM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.2 10250 {"bits": [13, 15], "name": "VALU_CNT"} array in object:register_types.SQ_WAVE_IB_STS.fields.3 10255 {"bits": [0, 7], "name": "LDS_BASE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.0 10256 {"bits": [12, 20], "name": "LDS_SIZE"} array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.1 10261 {"bits": [0, 3], "name": "FP_ROUND"}, array in object:register_types.SQ_WAVE_MODE.fields.0 10262 {"bits": [4, 7], "name": "FP_DENORM"}, array in object:register_types.SQ_WAVE_MODE.fields.1 10263 {"bits": [8, 8], "name": "DX10_CLAMP"}, array in object:register_types.SQ_WAVE_MODE.fields.2 10264 {"bits": [9, 9], "name": "IEEE"}, array in object:register_types.SQ_WAVE_MODE.fields.3 10265 {"bits": [10, 10], "name": "LOD_CLAMPED"}, array in object:register_types.SQ_WAVE_MODE.fields.4 10266 {"bits": [11, 11], "name": "DEBUG_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.5 10267 {"bits": [12, 18], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.6 10268 {"bits": [28, 28], "name": "VSKIP"}, array in object:register_types.SQ_WAVE_MODE.fields.7 10269 {"bits": [29, 31], "name": "CSP"} array in object:register_types.SQ_WAVE_MODE.fields.8 10274 {"bits": [0, 7], "name": "PC_HI"} array in object:register_types.SQ_WAVE_PC_HI.fields.0 10279 {"bits": [0, 0], "name": "SCC"}, array in object:register_types.SQ_WAVE_STATUS.fields.0 10280 {"bits": [1, 2], "name": "SPI_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.1 10281 {"bits": [3, 4], "name": "WAVE_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.2 10282 {"bits": [5, 5], "name": "PRIV"}, array in object:register_types.SQ_WAVE_STATUS.fields.3 10283 {"bits": [6, 6], "name": "TRAP_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.4 10284 {"bits": [7, 7], "name": "TTRACE_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.5 10285 {"bits": [8, 8], "name": "EXPORT_RDY"}, array in object:register_types.SQ_WAVE_STATUS.fields.6 10286 {"bits": [9, 9], "name": "EXECZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.7 10287 {"bits": [10, 10], "name": "VCCZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.8 10288 {"bits": [11, 11], "name": "IN_TG"}, array in object:register_types.SQ_WAVE_STATUS.fields.9 10289 {"bits": [12, 12], "name": "IN_BARRIER"}, array in object:register_types.SQ_WAVE_STATUS.fields.10 10290 {"bits": [13, 13], "name": "HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.11 10291 {"bits": [14, 14], "name": "TRAP"}, array in object:register_types.SQ_WAVE_STATUS.fields.12 10292 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.13 10293 {"bits": [16, 16], "name": "VALID"}, array in object:register_types.SQ_WAVE_STATUS.fields.14 10294 {"bits": [17, 17], "name": "ECC_ERR"}, array in object:register_types.SQ_WAVE_STATUS.fields.15 10295 {"bits": [18, 18], "name": "SKIP_EXPORT"}, array in object:register_types.SQ_WAVE_STATUS.fields.16 10296 {"bits": [19, 19], "name": "PERF_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.17 10297 {"bits": [20, 20], "name": "COND_DBG_USER"}, array in object:register_types.SQ_WAVE_STATUS.fields.18 10298 {"bits": [21, 21], "name": "COND_DBG_SYS"}, array in object:register_types.SQ_WAVE_STATUS.fields.19 10299 {"bits": [22, 22], "name": "DATA_ATC"}, array in object:register_types.SQ_WAVE_STATUS.fields.20 10300 {"bits": [23, 23], "name": "INST_ATC"}, array in object:register_types.SQ_WAVE_STATUS.fields.21 10301 {"bits": [24, 26], "name": "DISPATCH_CACHE_CTRL"}, array in object:register_types.SQ_WAVE_STATUS.fields.22 10302 {"bits": [27, 27], "name": "MUST_EXPORT"} array in object:register_types.SQ_WAVE_STATUS.fields.23 10307 {"bits": [0, 7], "name": "ADDR_HI"} array in object:register_types.SQ_WAVE_TBA_HI.fields.0 10312 {"bits": [0, 6], "enum_ref": "EXCP_EN", "name": "EXCP"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.0 10313 {"bits": [16, 21], "name": "EXCP_CYCLE"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.1 10314 {"bits": [29, 31], "name": "DP_RATE"} array in object:register_types.SQ_WAVE_TRAPSTS.fields.2 10319 {"bits": [0, 1], "name": "CACHE_INVALIDATION"}, array in object:register_types.VGT_CACHE_INVALIDATION.fields.0 10320 {"bits": [5, 5], "name": "VS_NO_EXTRA_BUFFER"}, array in object:register_types.VGT_CACHE_INVALIDATION.fields.1 10321 {"bits": [6, 7], "name": "AUTO_INVLD_EN"}, array in object:register_types.VGT_CACHE_INVALIDATION.fields.2 10322 {"bits": [9, 9], "name": "USE_GS_DONE"}, array in object:register_types.VGT_CACHE_INVALIDATION.fields.3 10323 {"bits": [11, 11], "name": "DIS_RANGE_FULL_INVLD"}, array in object:register_types.VGT_CACHE_INVALIDATION.fields.4 10324 {"bits": [12, 12], "name": "GS_LATE_ALLOC_EN"}, array in object:register_types.VGT_CACHE_INVALIDATION.fields.5 10325 {"bits": [13, 13], "name": "STREAMOUT_FULL_FLUSH"}, array in object:register_types.VGT_CACHE_INVALIDATION.fields.6 10326 {"bits": [16, 20], "name": "ES_LIMIT"} array in object:register_types.VGT_CACHE_INVALIDATION.fields.7 10331 {"bits": [0, 0], "name": "VGT_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.0 10332 {"bits": [1, 1], "name": "VGT_OUT_INDX_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.1 10333 {"bits": [2, 2], "name": "VGT_OUT_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.2 10334 {"bits": [3, 3], "name": "VGT_PT_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.3 10335 {"bits": [4, 4], "name": "VGT_TE_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.4 10336 {"bits": [5, 5], "name": "VGT_VR_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.5 10337 {"bits": [6, 6], "name": "VGT_PI_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.6 10338 {"bits": [7, 7], "name": "VGT_GS_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.7 10339 {"bits": [8, 8], "name": "VGT_HS_BUSY"}, array in object:register_types.VGT_CNTL_STATUS.fields.8 10340 {"bits": [9, 9], "name": "VGT_TE11_BUSY"} array in object:register_types.VGT_CNTL_STATUS.fields.9 10345 {"bits": [0, 5], "name": "VGT_DEBUG_INDX"}, array in object:register_types.VGT_DEBUG_CNTL.fields.0 10346 {"bits": [6, 6], "name": "VGT_DEBUG_SEL_BUS_B"} array in object:register_types.VGT_DEBUG_CNTL.fields.1 10351 {"bits": [0, 7], "name": "BASE_ADDR"} array in object:register_types.VGT_DMA_BASE_HI.fields.0 10356 {"bits": [0, 8], "name": "DMA_DATA_FIFO_DEPTH"} array in object:register_types.VGT_DMA_DATA_FIFO_DEPTH.fields.0 10361 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.0 10362 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.1 10363 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.2 10364 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.3 10365 {"bits": [8, 8], "name": "ATC"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.4 10366 {"bits": [9, 9], "name": "NOT_EOP"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.5 10367 {"bits": [10, 10], "name": "REQ_PATH"} array in object:register_types.VGT_DMA_INDEX_TYPE.fields.6 10372 {"bits": [0, 5], "name": "DMA_REQ_FIFO_DEPTH"} array in object:register_types.VGT_DMA_REQ_FIFO_DEPTH.fields.0 10377 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.0 10378 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.1 10379 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.2 10380 {"bits": [5, 5], "name": "NOT_EOP"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.3 10381 {"bits": [6, 6], "name": "USE_OPAQUE"} array in object:register_types.VGT_DRAW_INITIATOR.fields.4 10386 {"bits": [0, 5], "name": "DRAW_INIT_FIFO_DEPTH"} array in object:register_types.VGT_DRAW_INIT_FIFO_DEPTH.fields.0 10391 {"bits": [0, 14], "name": "ITEMSIZE"} array in object:register_types.VGT_ESGS_RING_ITEMSIZE.fields.0 10396 {"bits": [0, 10], "name": "ES_PER_GS"} array in object:register_types.VGT_ES_PER_GS.fields.0 10401 {"bits": [0, 27], "name": "ADDRESS_LOW"} array in object:register_types.VGT_EVENT_ADDRESS_REG.fields.0 10406 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.0 10407 {"bits": [18, 26], "name": "ADDRESS_HI"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.1 10408 {"bits": [27, 27], "name": "EXTENDED_EVENT"} array in object:register_types.VGT_EVENT_INITIATOR.fields.2 10413 {"bits": [0, 6], "name": "VS_DEALLOC_TBL_DEPTH"}, array in object:register_types.VGT_FIFO_DEPTHS.fields.0 10414 {"bits": [7, 7], "name": "RESERVED_0"}, array in object:register_types.VGT_FIFO_DEPTHS.fields.1 10415 {"bits": [8, 21], "name": "CLIPP_FIFO_DEPTH"}, array in object:register_types.VGT_FIFO_DEPTHS.fields.2 10416 {"bits": [22, 31], "name": "RESERVED_1"} array in object:register_types.VGT_FIFO_DEPTHS.fields.3 10421 {"bits": [0, 3], "name": "DECR"} array in object:register_types.VGT_GROUP_DECR.fields.0 10426 {"bits": [0, 3], "name": "FIRST_DECR"} array in object:register_types.VGT_GROUP_FIRST_DECR.fields.0 10431 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0 10432 {"bits": [14, 14], "name": "RETAIN_ORDER"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.1 10433 {"bits": [15, 15], "name": "RETAIN_QUADS"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.2 10434 {"bits": [16, 18], "name": "PRIM_ORDER"} array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.3 10439 {"bits": [0, 0], "name": "COMP_X_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.0 10440 {"bits": [1, 1], "name": "COMP_Y_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.1 10441 {"bits": [2, 2], "name": "COMP_Z_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.2 10442 {"bits": [3, 3], "name": "COMP_W_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.3 10443 {"bits": [8, 15], "name": "STRIDE"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.4 10444 {"bits": [16, 23], "name": "SHIFT"} array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.5 10449 {"bits": [0, 3], "name": "X_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.0 10450 {"bits": [4, 7], "name": "X_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.1 10451 {"bits": [8, 11], "name": "Y_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.2 10452 {"bits": [12, 15], "name": "Y_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.3 10453 {"bits": [16, 19], "name": "Z_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.4 10454 {"bits": [20, 23], "name": "Z_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.5 10455 {"bits": [24, 27], "name": "W_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.6 10456 {"bits": [28, 31], "name": "W_OFFSET"} array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.7 10461 {"bits": [0, 14], "name": "OFFSET"} array in object:register_types.VGT_GSVS_RING_OFFSET_1.fields.0 10466 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.0 10467 {"bits": [2, 8], "name": "CNT"} array in object:register_types.VGT_GS_INSTANCE_CNT.fields.1 10472 {"bits": [0, 10], "name": "MAX_VERT_OUT"} array in object:register_types.VGT_GS_MAX_VERT_OUT.fields.0 10477 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, array in object:register_types.VGT_GS_MODE.fields.0 10478 {"bits": [3, 3], "name": "RESERVED_0"}, array in object:register_types.VGT_GS_MODE.fields.1 10479 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, array in object:register_types.VGT_GS_MODE.fields.2 10480 {"bits": [6, 10], "name": "RESERVED_1"}, array in object:register_types.VGT_GS_MODE.fields.3 10481 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, array in object:register_types.VGT_GS_MODE.fields.4 10482 {"bits": [12, 12], "name": "RESERVED_2"}, array in object:register_types.VGT_GS_MODE.fields.5 10483 {"bits": [13, 13], "name": "ES_PASSTHRU"}, array in object:register_types.VGT_GS_MODE.fields.6 10484 {"bits": [14, 14], "name": "COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.7 10485 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.8 10486 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, array in object:register_types.VGT_GS_MODE.fields.9 10487 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, array in object:register_types.VGT_GS_MODE.fields.10 10488 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, array in object:register_types.VGT_GS_MODE.fields.11 10489 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.12 10490 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.13 10491 {"bits": [21, 22], "name": "ONCHIP"} array in object:register_types.VGT_GS_MODE.fields.14 10496 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0 10497 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1 10498 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2 10499 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3 10500 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.4 10505 {"bits": [0, 10], "name": "GS_PER_ES"} array in object:register_types.VGT_GS_PER_ES.fields.0 10510 {"bits": [0, 3], "name": "GS_PER_VS"} array in object:register_types.VGT_GS_PER_VS.fields.0 10515 {"bits": [0, 4], "name": "VERT_REUSE"} array in object:register_types.VGT_GS_VERTEX_REUSE.fields.0 10520 {"bits": [0, 1], "name": "TESS_MODE"} array in object:register_types.VGT_HOS_CNTL.fields.0 10525 {"bits": [0, 7], "name": "REUSE_DEPTH"} array in object:register_types.VGT_HOS_REUSE_DEPTH.fields.0 10530 {"bits": [0, 6], "name": "OFFCHIP_BUFFERING"}, array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.0 10531 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1 10536 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} array in object:register_types.VGT_INDEX_TYPE.fields.0 10541 {"bits": [0, 2], "name": "SRC_STATE_ID"}, array in object:register_types.VGT_LAST_COPY_STATE.fields.0 10542 {"bits": [16, 18], "name": "DST_STATE_ID"} array in object:register_types.VGT_LAST_COPY_STATE.fields.1 10547 {"bits": [0, 7], "name": "NUM_PATCHES"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.0 10548 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.1 10549 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} array in object:register_types.VGT_LS_HS_CONFIG.fields.2 10554 {"bits": [0, 1], "name": "MC_TIME_STAMP_RES"} array in object:register_types.VGT_MC_LAT_CNTL.fields.0 10559 {"bits": [0, 0], "name": "RESET_EN"} array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.0 10564 {"bits": [0, 2], "name": "PATH_SELECT"} array in object:register_types.VGT_OUTPUT_PATH_CNTL.fields.0 10569 {"bits": [0, 6], "name": "DEALLOC_DIST"} array in object:register_types.VGT_OUT_DEALLOC_CNTL.fields.0 10574 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} array in object:register_types.VGT_PERFCOUNTER_SEID_MASK.fields.0 10579 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.0 10580 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"} array in object:register_types.VGT_PRIMITIVEID_EN.fields.1 10585 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} array in object:register_types.VGT_PRIMITIVE_TYPE.fields.0 10590 {"bits": [0, 0], "name": "REUSE_OFF"} array in object:register_types.VGT_REUSE_OFF.fields.0 10595 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.0 10596 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.1 10597 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.2 10598 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.3 10599 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.4 10600 {"bits": [8, 8], "name": "DYNAMIC_HS"} array in object:register_types.VGT_SHADER_STAGES_EN.fields.5 10605 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.0 10606 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.1 10607 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.2 10608 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.3 10613 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.0 10614 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.1 10615 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.2 10616 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.3 10617 {"bits": [4, 6], "name": "RAST_STREAM"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.4 10618 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.5 10619 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} array in object:register_types.VGT_STRMOUT_CONFIG.fields.6 10624 {"bits": [0, 8], "name": "VERTEX_STRIDE"} array in object:register_types.VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE.fields.0 10629 {"bits": [0, 9], "name": "STRIDE"} array in object:register_types.VGT_STRMOUT_VTX_STRIDE_0.fields.0 10634 {"bits": [0, 0], "name": "DUAL_CORE_EN"}, array in object:register_types.VGT_SYS_CONFIG.fields.0 10635 {"bits": [1, 6], "name": "MAX_LS_HS_THDGRP"}, array in object:register_types.VGT_SYS_CONFIG.fields.1 10636 {"bits": [7, 7], "name": "ADC_EVENT_FILTER_DISABLE"} array in object:register_types.VGT_SYS_CONFIG.fields.2 10641 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, array in object:register_types.VGT_TF_PARAM.fields.0 10642 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, array in object:register_types.VGT_TF_PARAM.fields.1 10643 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, array in object:register_types.VGT_TF_PARAM.fields.2 10644 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, array in object:register_types.VGT_TF_PARAM.fields.3 10645 {"bits": [9, 9], "name": "DEPRECATED"}, array in object:register_types.VGT_TF_PARAM.fields.4 10646 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, array in object:register_types.VGT_TF_PARAM.fields.5 10647 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, array in object:register_types.VGT_TF_PARAM.fields.6 10648 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"} array in object:register_types.VGT_TF_PARAM.fields.7 10653 {"bits": [0, 15], "name": "SIZE"} array in object:register_types.VGT_TF_RING_SIZE.fields.0 10658 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} array in object:register_types.VGT_VERTEX_REUSE_BLOCK_CNTL.fields.0 10663 {"bits": [0, 0], "name": "VTX_CNT_EN"} array in object:register_types.VGT_VTX_CNT_EN.fields.0 10668 {"bits": [0, 9], "name": "PRIM_COUNT"} array in object:register_types.VGT_VTX_VECT_EJECT_REG.fields.0 [all...]
H A D	gfx10.json	11592 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.0 11593 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.1 11594 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.2 11595 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.3 11596 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.4 11597 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.5 11598 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.6 11599 {"bits": [30, 30], "name": "ENABLE"}, array in object:register_types.CB_BLEND0_CONTROL.fields.7 11600 {"bits": [31, 31], "name": "DISABLE_ROP3"} array in object:register_types.CB_BLEND0_CONTROL.fields.8 11605 {"bits" array in object:register_types.CB_COLOR0_ATTRIB.fields.0 11606 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.1 11607 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.2 11608 {"bits": [12, 14], "name": "NUM_SAMPLES"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.3 11609 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.4 11610 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.5 11611 {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.6 11612 {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"} array in object:register_types.CB_COLOR0_ATTRIB.fields.7 11617 {"bits": [0, 13], "name": "MIP0_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB2.fields.0 11618 {"bits": [14, 27], "name": "MIP0_WIDTH"}, array in object:register_types.CB_COLOR0_ATTRIB2.fields.1 11619 {"bits": [28, 31], "name": "MAX_MIP"} array in object:register_types.CB_COLOR0_ATTRIB2.fields.2 11624 {"bits": [0, 12], "name": "MIP0_DEPTH"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.0 11625 {"bits": [13, 13], "name": "META_LINEAR"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.1 11626 {"bits": [14, 18], "name": "COLOR_SW_MODE"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.2 11627 {"bits": [19, 23], "name": "FMASK_SW_MODE"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.3 11628 {"bits": [24, 25], "name": "RESOURCE_TYPE"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.4 11629 {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.5 11630 {"bits": [27, 29], "name": "RESOURCE_LEVEL"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.6 11631 {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"} array in object:register_types.CB_COLOR0_ATTRIB3.fields.7 11636 {"bits": [0, 7], "name": "BASE_256B"} array in object:register_types.CB_COLOR0_BASE_EXT.fields.0 11641 {"bits": [0, 13], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_CMASK_SLICE.fields.0 11646 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.0 11647 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.1 11648 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": " array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2 11649 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MI array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3 11650 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.4 11651 {"bits": [7, 8], "name": "COLOR_TRANSFORM"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.5 11652 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.6 11653 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.7 11654 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.8 11655 {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.9 11656 {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.10 11657 {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"} array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.11 11662 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, array in object:register_types.CB_COLOR0_INFO.fields.0 11663 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, array in object:register_types.CB_COLOR0_INFO.fields.1 11664 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, array in object:register_types.CB_COLOR0_INFO.fields.2 11665 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.3 11666 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, array in object:register_types.CB_COLOR0_INFO.fields.4 11667 {"bits": [13, 13], "name": "FAST_CLEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.5 11668 {"bits": [14, 14], "name": "COMPRESSION"}, array in object:register_types.CB_COLOR0_INFO.fields.6 11669 {"bits": [15, 15], "name": "BLEND_CLAMP"}, array in object:register_types.CB_COLOR0_INFO.fields.7 11670 {"bits": [16, 16], "name": "BLEND_BYPASS"}, array in object:register_types.CB_COLOR0_INFO.fields.8 11671 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, array in object:register_types.CB_COLOR0_INFO.fields.9 11672 {"bits": [18, 18], "name": "ROUND_MODE"}, array in object:register_types.CB_COLOR0_INFO.fields.10 11673 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.11 11674 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, array in object:register_types.CB_COLOR0_INFO.fields.12 11675 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, array in object:register_types.CB_COLOR0_INFO.fields.13 11676 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.14 11677 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"}, array in object:register_types.CB_COLOR0_INFO.fields.15 11678 {"bits": [28, 28], "name": "DCC_ENABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.16 11679 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.17 11680 {"bits": [31, 31], "name": "ALT_TILE_MODE"} array in object:register_types.CB_COLOR0_INFO.fields.18 11685 {"bits": [0, 10], "name": "TILE_MAX"}, array in object:register_types.CB_COLOR0_PITCH.fields.0 11686 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} array in object:register_types.CB_COLOR0_PITCH.fields.1 11691 {"bits": [0, 21], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_SLICE.fields.0 11696 {"bits": [0, 12], "name": "SLICE_START"}, array in object:register_types.CB_COLOR0_VIEW.fields.0 11697 {"bits": [13, 25], "name": "SLICE_MAX"}, array in object:register_types.CB_COLOR0_VIEW.fields.1 11698 {"bits": [26, 29], "name": "MIP_LEVEL"} array in object:register_types.CB_COLOR0_VIEW.fields.2 11703 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"}, array in object:register_types.CB_COLOR_CONTROL.fields.0 11704 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, array in object:register_types.CB_COLOR_CONTROL.fields.1 11705 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, array in object:register_types.CB_COLOR_CONTROL.fields.2 11706 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} array in object:register_types.CB_COLOR_CONTROL.fields.3 11711 {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"}, array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.0 11712 {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"}, array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.1 11713 {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"}, array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.2 11714 {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"} array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.3 11719 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_DCC_CONTROL.fields.0 11720 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}, array in object:register_types.CB_DCC_CONTROL.fields.1 11721 {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"}, array in object:register_types.CB_DCC_CONTROL.fields.2 11722 {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"}, array in object:register_types.CB_DCC_CONTROL.fields.3 11723 {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"}, array in object:register_types.CB_DCC_CONTROL.fields.4 11724 {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"}, array in object:register_types.CB_DCC_CONTROL.fields.5 11725 {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"}, array in object:register_types.CB_DCC_CONTROL.fields.6 11726 {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"} array in object:register_types.CB_DCC_CONTROL.fields.7 11731 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.0 11732 {"bits": [10, 18], "name": "PERF_SEL1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.1 11733 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.2 11734 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.3 11735 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.4 11740 {"bits": [0, 8], "name": "PERF_SEL2"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.0 11741 {"bits": [10, 18], "name": "PERF_SEL3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.1 11742 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.2 11743 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.3 11748 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.0 11749 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.1 11754 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.0 11755 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.1 11756 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.2 11757 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.3 11758 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.4 11759 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.5 11760 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.6 11761 {"bits": [13, 15], "name": "MRT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.7 11762 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.8 11763 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.9 11764 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.10 11765 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"} array in object:register_types.CB_PERFCOUNTER_FILTER.fields.11 11770 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.0 11771 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.1 11772 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.2 11773 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.3 11774 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.4 11775 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.5 11776 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.6 11777 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.7 11778 {"bits": [30, 30], "name": "FMASK_BIG_PAGE"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.8 11779 {"bits": [31, 31], "name": "COLOR_BIG_PAGE"} array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.9 11784 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.0 11785 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.1 11786 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.2 11787 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.3 11788 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.4 11789 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.5 11790 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.6 11791 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} array in object:register_types.CB_SHADER_MASK.fields.7 11796 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.0 11797 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.1 11798 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.2 11799 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.3 11800 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.4 11801 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.5 11802 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.6 11803 {"bits": [28, 31], "name": "TARGET7_ENABLE"} array in object:register_types.CB_TARGET_MASK.fields.7 11808 {"bits": [0, 7], "name": "DEST_BASE_HI_256B"} array in object:register_types.COHER_DEST_BASE_HI_0.fields.0 11813 {"bits": [0, 10], "name": "INDEX"} array in object:register_types.COMPUTE_DDID_INDEX.fields.0 11818 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.0 11819 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.1 11820 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.2 11821 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.3 11822 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.4 11823 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.5 11824 {"bits": [6, 6], "name": "ORDER_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.6 11825 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.7 11826 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.8 11827 {"bits": [12, 12], "name": "RESERVED"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.9 11828 {"bits": [13, 13], "name": "TUNNEL_ENABLE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.10 11829 {"bits": [14, 14], "name": "RESTORE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.11 11830 {"bits": [15, 15], "name": "CS_W32_EN"} array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.12 11835 {"bits": [0, 9], "name": "OFF_DELAY"}, array in object:register_types.COMPUTE_DISPATCH_TUNNEL.fields.0 11836 {"bits": [10, 10], "name": "IMMEDIATE"} array in object:register_types.COMPUTE_DISPATCH_TUNNEL.fields.1 11841 {"bits": [0, 1], "name": "SEND_SEID"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.0 11842 {"bits": [2, 2], "name": "RESERVED2"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.1 11843 {"bits": [3, 3], "name": "RESERVED3"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.2 11844 {"bits": [4, 4], "name": "RESERVED4"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.3 11845 {"bits": [5, 16], "name": "WAVE_ID_BASE"} array in object:register_types.COMPUTE_MISC_RESERVED.fields.4 11850 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, array in object:register_types.COMPUTE_NUM_THREAD_X.fields.0 11851 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} array in object:register_types.COMPUTE_NUM_THREAD_X.fields.1 11856 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"} array in object:register_types.COMPUTE_PERFCOUNT_ENABLE.fields.0 11861 {"bits": [0, 7], "name": "DATA"} array in object:register_types.COMPUTE_PGM_HI.fields.0 11866 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.0 11867 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.1 11868 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.2 11869 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.3 11870 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.4 11871 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.5 11872 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.6 11873 {"bits": [24, 24], "name": "BULKY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.7 11874 {"bits": [26, 26], "name": "FP16_OVFL"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.8 11875 {"bits": [29, 29], "name": "WGP_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.9 11876 {"bits": [30, 30], "name": "MEM_ORDERED"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.10 11877 {"bits": [31, 31], "name": "FWD_PROGRESS"} array in object:register_types.COMPUTE_PGM_RSRC1.fields.11 11882 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.0 11883 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.1 11884 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.2 11885 {"bits": [7, 7], "name": "TGID_X_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.3 11886 {"bits": [8, 8], "name": "TGID_Y_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.4 11887 {"bits": [9, 9], "name": "TGID_Z_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.5 11888 {"bits": [10, 10], "name": "TG_SIZE_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.6 11889 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.7 11890 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.8 11891 {"bits": [15, 23], "name": "LDS_SIZE"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.9 11892 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.COMPUTE_PGM_RSRC2.fields.10 11897 {"bits": [0, 3], "name": "SHARED_VGPR_CNT"} array in object:register_types.COMPUTE_PGM_RSRC3.fields.0 11902 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"} array in object:register_types.COMPUTE_PIPELINESTAT_ENABLE.fields.0 11907 {"bits": [0, 29], "name": "PAYLOAD"}, array in object:register_types.COMPUTE_RELAUNCH.fields.0 11908 {"bits": [30, 30], "name": "IS_EVENT"}, array in object:register_types.COMPUTE_RELAUNCH.fields.1 11909 {"bits": [31, 31], "name": "IS_STATE"} array in object:register_types.COMPUTE_RELAUNCH.fields.2 11914 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.0 11915 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.1 11916 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.2 11917 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.3 11918 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.4 11919 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.5 11920 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.6 11921 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.7 11922 {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"} array in object:register_types.COMPUTE_REQ_CTRL.fields.8 11927 {"bits": [0, 9], "name": "WAVES_PER_SH"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.0 11928 {"bits": [12, 15], "name": "TG_PER_CU"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.1 11929 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.2 11930 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.3 11931 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.4 11932 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.5 11937 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"} array in object:register_types.COMPUTE_THREAD_TRACE_ENABLE.fields.0 11942 {"bits": [0, 11], "name": "WAVES"}, array in object:register_types.COMPUTE_TMPRING_SIZE.fields.0 11943 {"bits": [12, 24], "name": "WAVESIZE"} array in object:register_types.COMPUTE_TMPRING_SIZE.fields.1 11948 {"bits": [0, 3], "name": "DATA"} array in object:register_types.COMPUTE_VMID.fields.0 11953 {"bits": [0, 15], "name": "ADDR"} array in object:register_types.COMPUTE_WAVE_RESTORE_ADDR_HI.fields.0 11958 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.0 11959 {"bits": [30, 30], "name": "CLEAR"}, array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.1 11960 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.2 11965 {"bits": [0, 2], "name": "INDEX"}, array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.0 11966 {"bits": [30, 30], "name": "ALWAYS"}, array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.1 11967 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.2 11972 {"bits": [0, 4], "name": "INDEX"}, array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.0 11973 {"bits": [30, 30], "name": "CLEAR"}, array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.1 11974 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.2 11979 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.0 11980 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.1 11981 {"bits": [24, 27], "name": "CNTR_MODE3"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.2 11982 {"bits": [28, 31], "name": "CNTR_MODE2"} array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.3 11987 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.0 11988 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.1 11989 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.2 11990 {"bits": [24, 27], "name": "CNTR_MODE1"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.3 11991 {"bits": [28, 31], "name": "CNTR_MODE0"} array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.4 11996 {"bits": [0, 4], "name": "INDEX"}, array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.0 11997 {"bits": [30, 30], "name": "ALWAYS"}, array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.1 11998 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.2 12003 {"bits": [0, 15], "name": "MEM_ADDR_HI"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.0 12004 {"bits": [16, 16], "name": "CS_PS_SEL"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.1 12005 {"bits": [25, 26], "name": "CACHE_POLICY"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.2 12006 {"bits": [29, 31], "name": "COMMAND"} array in object:register_types.CP_APPEND_ADDR_HI.fields.3 12011 {"bits": [2, 31], "name": "MEM_ADDR_LO"} array in object:register_types.CP_APPEND_ADDR_LO.fields.0 12016 {"bits": [0, 15], "name": "IB1_BASE_HI"} array in object:register_types.CP_CE_IB1_BASE_HI.fields.0 12021 {"bits": [2, 31], "name": "IB1_BASE_LO"} array in object:register_types.CP_CE_IB1_BASE_LO.fields.0 12026 {"bits": [0, 19], "name": "IB1_BUFSZ"} array in object:register_types.CP_CE_IB1_BUFSZ.fields.0 12031 {"bits": [0, 19], "name": "IB1_CMD_REQSZ"} array in object:register_types.CP_CE_IB1_CMD_BUFSZ.fields.0 12036 {"bits": [0, 15], "name": "IB2_BASE_HI"} array in object:register_types.CP_CE_IB2_BASE_HI.fields.0 12041 {"bits": [2, 31], "name": "IB2_BASE_LO"} array in object:register_types.CP_CE_IB2_BASE_LO.fields.0 12046 {"bits": [0, 19], "name": "IB2_BUFSZ"} array in object:register_types.CP_CE_IB2_BUFSZ.fields.0 12051 {"bits": [0, 19], "name": "IB2_CMD_REQSZ"} array in object:register_types.CP_CE_IB2_CMD_BUFSZ.fields.0 12056 {"bits": [0, 15], "name": "INIT_BASE_HI"} array in object:register_types.CP_CE_INIT_BASE_HI.fields.0 12061 {"bits": [5, 31], "name": "INIT_BASE_LO"} array in object:register_types.CP_CE_INIT_BASE_LO.fields.0 12066 {"bits": [0, 11], "name": "INIT_BUFSZ"} array in object:register_types.CP_CE_INIT_BUFSZ.fields.0 12071 {"bits": [0, 11], "name": "INIT_CMD_REQSZ"} array in object:register_types.CP_CE_INIT_CMD_BUFSZ.fields.0 12076 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"} array in object:register_types.CP_COHER_BASE_HI.fields.0 12081 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.0 12082 {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.1 12083 {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.2 12084 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.3 12085 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.4 12086 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.5 12087 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.6 12088 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.7 12089 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.8 12090 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.9 12091 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.10 12092 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.11 12093 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"} array in object:register_types.CP_COHER_CNTL.fields.12 12098 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"} array in object:register_types.CP_COHER_SIZE_HI.fields.0 12103 {"bits": [0, 5], "name": "START_DELAY_COUNT"} array in object:register_types.CP_COHER_START_DELAY.fields.0 12108 {"bits": [24, 25], "name": "MEID"}, array in object:register_types.CP_COHER_STATUS.fields.0 12109 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_COHER_STATUS.fields.1 12114 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.0 12115 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.1 12116 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.2 12117 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.3 12118 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.4 12119 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.5 12120 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.6 12121 {"bits": [7, 7], "name": "MEC1_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.7 12122 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.8 12123 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.9 12124 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.10 12125 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.11 12126 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.12 12127 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.13 12128 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.14 12129 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.15 12130 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.16 12131 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.17 12132 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.18 12133 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.19 12134 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.20 12135 {"bits": [23, 23], "name": "MEC2_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.21 12136 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.22 12137 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.23 12138 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.24 12139 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.25 12140 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.26 12141 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"} array in object:register_types.CP_CPC_BUSY_STAT.fields.27 12146 {"bits": [0, 0], "name": "MES_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.0 12147 {"bits": [2, 2], "name": "MES_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.1 12148 {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.2 12149 {"bits": [7, 7], "name": "MES_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.3 12150 {"bits": [8, 8], "name": "MES_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.4 12151 {"bits": [10, 10], "name": "MES_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.5 12152 {"bits": [11, 11], "name": "MES_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.6 12153 {"bits": [12, 12], "name": "MES_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.7 12154 {"bits": [13, 13], "name": "MES_PIPE3_BUSY"} array in object:register_types.CP_CPC_BUSY_STAT2.fields.8 12159 {"bits": [0, 5], "name": "FREE_COUNT"} array in object:register_types.CP_CPC_GRBM_FREE_COUNT.fields.0 12164 {"bits": [0, 3], "name": "COUNT"} array in object:register_types.CP_CPC_HALT_HYST_COUNT.fields.0 12169 {"bits": [0, 8], "name": "SCRATCH_INDEX"}, array in object:register_types.CP_CPC_SCRATCH_INDEX.fields.0 12170 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"} array in object:register_types.CP_CPC_SCRATCH_INDEX.fields.1 12175 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.0 12176 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.1 12177 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.2 12178 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.3 12179 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.4 12180 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.5 12181 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.6 12182 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.7 12183 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.8 12184 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.9 12185 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.10 12186 {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.11 12187 {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.12 12188 {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.13 12189 {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"} array in object:register_types.CP_CPC_STALLED_STAT1.fields.14 12194 {"bits": [0, 0], "name": "MEC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.0 12195 {"bits": [1, 1], "name": "MEC2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.1 12196 {"bits": [2, 2], "name": "DC0_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.2 12197 {"bits": [3, 3], "name": "DC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.3 12198 {"bits": [4, 4], "name": "RCIU1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.4 12199 {"bits": [5, 5], "name": "RCIU2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.5 12200 {"bits": [6, 6], "name": "ROQ1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.6 12201 {"bits": [7, 7], "name": "ROQ2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.7 12202 {"bits": [10, 10], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.8 12203 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.9 12204 {"bits": [12, 12], "name": "QU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.10 12205 {"bits": [13, 13], "name": "UTCL2IU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.11 12206 {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.12 12207 {"bits": [15, 15], "name": "GCRIU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.13 12208 {"bits": [16, 16], "name": "MES_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.14 12209 {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.15 12210 {"bits": [18, 18], "name": "RCIU3_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.16 12211 {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.17 12212 {"bits": [29, 29], "name": "CPG_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.18 12213 {"bits": [30, 30], "name": "CPF_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.19 12214 {"bits": [31, 31], "name": "CPC_BUSY"} array in object:register_types.CP_CPC_STATUS.fields.20 12219 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.0 12220 {"bits": [1, 1], "name": "CSF_RING_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.1 12221 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.2 12222 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.3 12223 {"bits": [4, 4], "name": "CSF_STATE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.4 12224 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.5 12225 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.6 12226 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.7 12227 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.8 12228 {"bits": [9, 9], "name": "CSF_DATA_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.9 12229 {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.10 12230 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.11 12231 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.12 12232 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.13 12233 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.14 12234 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.15 12235 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.16 12236 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.17 12237 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.18 12238 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.19 12239 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.20 12240 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.21 12241 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.22 12242 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.23 12243 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.24 12244 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.25 12245 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.26 12246 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.27 12247 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.28 12248 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.29 12249 {"bits": [30, 30], "name": "HQD_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.30 12250 {"bits": [31, 31], "name": "HQD_IB_BUSY"} array in object:register_types.CP_CPF_BUSY_STAT.fields.31 12255 {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.0 12256 {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.1 12257 {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.2 12258 {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.3 12259 {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.4 12260 {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.5 12261 {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.6 12262 {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.7 12263 {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"} array in object:register_types.CP_CPF_BUSY_STAT2.fields.8 12268 {"bits": [0, 2], "name": "FREE_COUNT"} array in object:register_types.CP_CPF_GRBM_FREE_COUNT.fields.0 12273 {"bits": [0, 0], "name": "RING_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.0 12274 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.1 12275 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.2 12276 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.3 12277 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.4 12278 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.5 12279 {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.6 12280 {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.7 12281 {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.8 12282 {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.9 12283 {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.10 12284 {"bits": [12, 12], "name": "DATA_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.11 12285 {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"} array in object:register_types.CP_CPF_STALLED_STAT1.fields.12 12290 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.0 12291 {"bits": [1, 1], "name": "CSF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.1 12292 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.2 12293 {"bits": [5, 5], "name": "ROQ_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.3 12294 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.4 12295 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.5 12296 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.6 12297 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.7 12298 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.8 12299 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.9 12300 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.10 12301 {"bits": [13, 13], "name": "INTERRUPT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.11 12302 {"bits": [14, 14], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.12 12303 {"bits": [15, 15], "name": "HQD_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.13 12304 {"bits": [16, 16], "name": "PRT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.14 12305 {"bits": [17, 17], "name": "UTCL2IU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.15 12306 {"bits": [18, 18], "name": "RCIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.16 12307 {"bits": [19, 19], "name": "RCIU_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.17 12308 {"bits": [20, 20], "name": "RCIU_CMP_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.18 12309 {"bits": [21, 21], "name": "ROQ_DATA_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.19 12310 {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.20 12311 {"bits": [23, 23], "name": "GCRIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.21 12312 {"bits": [24, 24], "name": "MES_HQD_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.22 12313 {"bits": [26, 26], "name": "CPF_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.23 12314 {"bits": [27, 27], "name": "CPF_CMP_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.24 12315 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.25 12316 {"bits": [30, 30], "name": "CPC_CPF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.26 12317 {"bits": [31, 31], "name": "CPF_BUSY"} array in object:register_types.CP_CPF_STATUS.fields.27 12322 {"bits": [0, 15], "name": "DB_BASE_HI"} array in object:register_types.CP_DB_BASE_HI.fields.0 12327 {"bits": [2, 31], "name": "DB_BASE_LO"} array in object:register_types.CP_DB_BASE_LO.fields.0 12332 {"bits": [0, 19], "name": "DB_BUFSZ"} array in object:register_types.CP_DB_BUFSZ.fields.0 12337 {"bits": [0, 19], "name": "DB_CMD_REQSZ"} array in object:register_types.CP_DB_CMD_BUFSZ.fields.0 12342 {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"}, array in object:register_types.CP_DMA_CNTL.fields.0 12343 {"bits": [1, 1], "name": "WATCH_CONTROL"}, array in object:register_types.CP_DMA_CNTL.fields.1 12344 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, array in object:register_types.CP_DMA_CNTL.fields.2 12345 {"bits": [16, 24], "name": "BUFFER_DEPTH"}, array in object:register_types.CP_DMA_CNTL.fields.3 12346 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, array in object:register_types.CP_DMA_CNTL.fields.4 12347 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, array in object:register_types.CP_DMA_CNTL.fields.5 12348 {"bits": [30, 31], "name": "PIO_COUNT"} array in object:register_types.CP_DMA_CNTL.fields.6 12353 {"bits": [0, 15], "name": "ADDR_HI"}, array in object:register_types.CP_DMA_ME_CMD_ADDR_HI.fields.0 12354 {"bits": [16, 31], "name": "RSVD"} array in object:register_types.CP_DMA_ME_CMD_ADDR_HI.fields.1 12359 {"bits": [0, 1], "name": "RSVD"}, array in object:register_types.CP_DMA_ME_CMD_ADDR_LO.fields.0 12360 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_DMA_ME_CMD_ADDR_LO.fields.1 12365 {"bits": [0, 25], "name": "BYTE_COUNT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.0 12366 {"bits": [26, 26], "name": "SAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.1 12367 {"bits": [27, 27], "name": "DAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.2 12368 {"bits": [28, 28], "name": "SAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.3 12369 {"bits": [29, 29], "name": "DAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.4 12370 {"bits": [30, 30], "name": "RAW_WAIT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.5 12371 {"bits": [31, 31], "name": "DIS_WC"} array in object:register_types.CP_DMA_ME_COMMAND.fields.6 12376 {"bits": [0, 15], "name": "DST_ADDR_HI"} array in object:register_types.CP_DMA_ME_DST_ADDR_HI.fields.0 12381 {"bits": [0, 15], "name": "SRC_ADDR_HI"} array in object:register_types.CP_DMA_ME_SRC_ADDR_HI.fields.0 12386 {"bits": [10, 10], "name": "MEMLOG_CLEAR"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.0 12387 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.1 12388 {"bits": [15, 15], "name": "SRC_VOLATLE"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.2 12389 {"bits": [20, 21], "name": "DST_SELECT"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.3 12390 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.4 12391 {"bits": [27, 27], "name": "DST_VOLATLE"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.5 12392 {"bits": [29, 30], "name": "SRC_SELECT"} array in object:register_types.CP_DMA_PFP_CONTROL.fields.6 12397 {"bits": [0, 25], "name": "DMA_READ_TAG"}, array in object:register_types.CP_DMA_READ_TAGS.fields.0 12398 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} array in object:register_types.CP_DMA_READ_TAGS.fields.1 12403 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.0 12404 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.1 12405 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.2 12406 {"bits": [8, 8], "name": "MODE"} array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.3 12411 {"bits": [0, 15], "name": "MIN"}, array in object:register_types.CP_DRAW_WINDOW_LO.fields.0 12412 {"bits": [16, 31], "name": "MAX"} array in object:register_types.CP_DRAW_WINDOW_LO.fields.1 12417 {"bits": [0, 15], "name": "ADDR_HI"} array in object:register_types.CP_EOP_DONE_ADDR_HI.fields.0 12422 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.0 12427 {"bits": [16, 17], "name": "DST_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.0 12428 {"bits": [24, 26], "name": "INT_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.1 12429 {"bits": [29, 31], "name": "DATA_SEL"} array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.2 12434 {"bits": [2, 27], "name": "DOORBELL_OFFSET"} array in object:register_types.CP_EOP_DONE_DOORBELL.fields.0 12439 {"bits": [12, 23], "name": "GCR_CNTL"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.0 12440 {"bits": [25, 26], "name": "CACHE_POLICY"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.1 12441 {"bits": [27, 27], "name": "EOP_VOLATILE"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.2 12442 {"bits": [28, 28], "name": "EXECUTE"} array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.3 12447 {"bits": [0, 19], "name": "IB1_OFFSET"} array in object:register_types.CP_IB1_OFFSET.fields.0 12452 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} array in object:register_types.CP_IB1_PREAMBLE_BEGIN.fields.0 12457 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} array in object:register_types.CP_IB1_PREAMBLE_END.fields.0 12462 {"bits": [0, 19], "name": "IB2_OFFSET"} array in object:register_types.CP_IB2_OFFSET.fields.0 12467 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} array in object:register_types.CP_IB2_PREAMBLE_BEGIN.fields.0 12472 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} array in object:register_types.CP_IB2_PREAMBLE_END.fields.0 12477 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} array in object:register_types.CP_INDEX_TYPE.fields.0 12482 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.0 12483 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.1 12484 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.2 12485 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.3 12486 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.4 12487 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.5 12488 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.6 12489 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.7 12490 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.8 12491 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.9 12492 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.10 12493 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.11 12494 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"} array in object:register_types.CP_ME_COHER_CNTL.fields.12 12499 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, array in object:register_types.CP_ME_COHER_STATUS.fields.0 12500 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_ME_COHER_STATUS.fields.1 12505 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"}, array in object:register_types.CP_ME_MC_RADDR_HI.fields.0 12506 {"bits": [22, 23], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_RADDR_HI.fields.1 12511 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} array in object:register_types.CP_ME_MC_RADDR_LO.fields.0 12516 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"}, array in object:register_types.CP_ME_MC_WADDR_HI.fields.0 12517 {"bits": [22, 23], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_WADDR_HI.fields.1 12522 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} array in object:register_types.CP_ME_MC_WADDR_LO.fields.0 12527 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.0 12528 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.1 12529 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, array in object:register_types.CP_PERFMON_CNTL.fields.2 12530 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.CP_PERFMON_CNTL.fields.3 12535 {"bits": [31, 31], "name": "PERFMON_ENABLE"} array in object:register_types.CP_PERFMON_CNTX_CNTL.fields.0 12540 {"bits": [0, 1], "name": "STATUS"} array in object:register_types.CP_PFP_COMPLETION_STATUS.fields.0 12545 {"bits": [0, 7], "name": "IB_EN"} array in object:register_types.CP_PFP_IB_CONTROL.fields.0 12550 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.0 12551 {"bits": [1, 1], "name": "CNTX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.1 12552 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.2 12553 {"bits": [24, 24], "name": "SH_CS_REG_EN"} array in object:register_types.CP_PFP_LOAD_CONTROL.fields.3 12558 {"bits": [0, 1], "name": "PIPE_ID"} array in object:register_types.CP_PIPEID.fields.0 12563 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"} array in object:register_types.CP_PIPE_STATS_ADDR_HI.fields.0 12568 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.0 12573 {"bits": [25, 26], "name": "CACHE_POLICY"} array in object:register_types.CP_PIPE_STATS_CONTROL.fields.0 12578 {"bits": [0, 0], "name": "NOT_VISIBLE"} array in object:register_types.CP_PRED_NOT_VISIBLE.fields.0 12583 {"bits": [0, 19], "name": "RB_OFFSET"} array in object:register_types.CP_RB_OFFSET.fields.0 12588 {"bits": [0, 0], "name": "Z_PASS_ACITVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.0 12589 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.1 12590 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.2 12591 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.3 12592 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.4 12593 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.5 12594 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.6 12595 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"} array in object:register_types.CP_SAMPLE_STATUS.fields.7 12600 {"bits": [0, 7], "name": "SCRATCH_INDEX"}, array in object:register_types.CP_SCRATCH_INDEX.fields.0 12601 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"} array in object:register_types.CP_SCRATCH_INDEX.fields.1 12606 {"bits": [0, 15], "name": "SEM_ADDR_HI"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.0 12607 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.1 12608 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.2 12609 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.3 12610 {"bits": [29, 31], "name": "SEM_SELECT"} array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.4 12615 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.0 12616 {"bits": [3, 31], "name": "SEM_ADDR_LO"} array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.1 12621 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"} array in object:register_types.CP_STREAM_OUT_ADDR_HI.fields.0 12626 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.0 12631 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} array in object:register_types.CP_STRMOUT_CNTL.fields.0 12636 {"bits": [0, 15], "name": "ST_BASE_HI"} array in object:register_types.CP_ST_BASE_HI.fields.0 12641 {"bits": [2, 31], "name": "ST_BASE_LO"} array in object:register_types.CP_ST_BASE_LO.fields.0 12646 {"bits": [0, 19], "name": "ST_BUFSZ"} array in object:register_types.CP_ST_BUFSZ.fields.0 12651 {"bits": [0, 19], "name": "ST_CMD_REQSZ"} array in object:register_types.CP_ST_CMD_BUFSZ.fields.0 12656 {"bits": [0, 3], "name": "VMID"} array in object:register_types.CP_VMID.fields.0 12661 {"bits": [0, 2], "name": "SRC_STATE_ID"} array in object:register_types.CS_COPY_STATE.fields.0 12666 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.0 12667 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.1 12668 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.2 12669 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.3 12670 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.4 12671 {"bits": [16, 16], "name": "OFFSET_ROUND"} array in object:register_types.DB_ALPHA_TO_MASK.fields.5 12676 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.0 12677 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.1 12678 {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.2 12679 {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.3 12680 {"bits": [4, 6], "name": "SAMPLE_RATE"}, array in object:register_types.DB_COUNT_CONTROL.fields.4 12681 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.5 12682 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.6 12683 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.7 12684 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.8 12685 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.9 12686 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} array in object:register_types.DB_COUNT_CONTROL.fields.10 12691 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.0 12692 {"bits": [1, 1], "name": "Z_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.1 12693 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.2 12694 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.3 12695 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.4 12696 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.5 12697 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.6 12698 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, array in object:register_types.DB_DEPTH_CONTROL.fields.7 12699 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, array in object:register_types.DB_DEPTH_CONTROL.fields.8 12700 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} array in object:register_types.DB_DEPTH_CONTROL.fields.9 12705 {"bits": [0, 13], "name": "X_MAX"}, array in object:register_types.DB_DEPTH_SIZE_XY.fields.0 12706 {"bits": [16, 29], "name": "Y_MAX"} array in object:register_types.DB_DEPTH_SIZE_XY.fields.1 12711 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.DB_DEPTH_VIEW.fields.0 12712 {"bits": [11, 12], "name": "SLICE_START_HI"}, array in object:register_types.DB_DEPTH_VIEW.fields.1 12713 {"bits": [13, 23], "name": "SLICE_MAX"}, array in object:register_types.DB_DEPTH_VIEW.fields.2 12714 {"bits": [24, 24], "name": "Z_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.3 12715 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.4 12716 {"bits": [26, 29], "name": "MIPID"}, array in object:register_types.DB_DEPTH_VIEW.fields.5 12717 {"bits": [30, 31], "name": "SLICE_MAX_HI"} array in object:register_types.DB_DEPTH_VIEW.fields.6 12722 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, array in object:register_types.DB_DFSM_CONTROL.fields.0 12723 {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"}, array in object:register_types.DB_DFSM_CONTROL.fields.1 12724 {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"} array in object:register_types.DB_DFSM_CONTROL.fields.2 12729 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, array in object:register_types.DB_EQAA.fields.0 12730 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, array in object:register_types.DB_EQAA.fields.1 12731 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.2 12732 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.3 12733 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, array in object:register_types.DB_EQAA.fields.4 12734 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, array in object:register_types.DB_EQAA.fields.5 12735 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, array in object:register_types.DB_EQAA.fields.6 12736 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, array in object:register_types.DB_EQAA.fields.7 12737 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, array in object:register_types.DB_EQAA.fields.8 12738 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, array in object:register_types.DB_EQAA.fields.9 12739 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, array in object:register_types.DB_EQAA.fields.10 12740 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} array in object:register_types.DB_EQAA.fields.11 12745 {"bits": [0, 0], "name": "RESERVED_FIELD_1"}, array in object:register_types.DB_HTILE_SURFACE.fields.0 12746 {"bits": [1, 1], "name": "FULL_CACHE"}, array in object:register_types.DB_HTILE_SURFACE.fields.1 12747 {"bits": [2, 2], "name": "RESERVED_FIELD_2"}, array in object:register_types.DB_HTILE_SURFACE.fields.2 12748 {"bits": [3, 3], "name": "RESERVED_FIELD_3"}, array in object:register_types.DB_HTILE_SURFACE.fields.3 12749 {"bits": [4, 9], "name": "RESERVED_FIELD_4"}, array in object:register_types.DB_HTILE_SURFACE.fields.4 12750 {"bits": [10, 15], "name": "RESERVED_FIELD_5"}, array in object:register_types.DB_HTILE_SURFACE.fields.5 12751 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}, array in object:register_types.DB_HTILE_SURFACE.fields.6 12752 {"bits": [17, 17], "name": "RESERVED_FIELD_6"}, array in object:register_types.DB_HTILE_SURFACE.fields.7 12753 {"bits": [18, 18], "name": "PIPE_ALIGNED"} array in object:register_types.DB_HTILE_SURFACE.fields.8 12758 {"bits": [0, 30], "name": "COUNT_HI"} array in object:register_types.DB_OCCLUSION_COUNT0_HI.fields.0 12763 {"bits": [0, 7], "name": "START_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.0 12764 {"bits": [8, 15], "name": "START_Y"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.1 12765 {"bits": [16, 23], "name": "MAX_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.2 12766 {"bits": [24, 31], "name": "MAX_Y"} array in object:register_types.DB_PRELOAD_CONTROL.fields.3 12771 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.0 12772 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.1 12773 {"bits": [2, 2], "name": "DEPTH_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.2 12774 {"bits": [3, 3], "name": "STENCIL_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.3 12775 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.4 12776 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.5 12777 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.6 12778 {"bits": [7, 7], "name": "COPY_CENTROID"}, array in object:register_types.DB_RENDER_CONTROL.fields.7 12779 {"bits": [8, 11], "name": "COPY_SAMPLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.8 12780 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"} array in object:register_types.DB_RENDER_CONTROL.fields.9 12785 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.0 12786 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.1 12787 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.2 12788 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.3 12789 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.4 12790 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.5 12791 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.6 12792 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.7 12793 {"bits": [11, 11], "name": "FORCE_Z_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.8 12794 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.9 12795 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.10 12796 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.11 12797 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.12 12798 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.13 12799 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.14 12800 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.15 12801 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.16 12802 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.17 12803 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.18 12804 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.19 12805 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.20 12806 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.21 12807 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} array in object:register_types.DB_RENDER_OVERRIDE.fields.22 12812 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.0 12813 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.1 12814 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.2 12815 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.3 12816 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.4 12817 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.5 12818 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.6 12819 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.7 12820 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.8 12821 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.9 12822 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.10 12823 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.11 12824 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.12 12825 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.13 12826 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.14 12827 {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"} array in object:register_types.DB_RENDER_OVERRIDE2.fields.15 12832 {"bits": [0, 10], "name": "FIELD_1"}, array in object:register_types.DB_RESERVED_REG_1.fields.0 12833 {"bits": [11, 21], "name": "FIELD_2"} array in object:register_types.DB_RESERVED_REG_1.fields.1 12838 {"bits": [0, 3], "name": "FIELD_1"}, array in object:register_types.DB_RESERVED_REG_2.fields.0 12839 {"bits": [4, 7], "name": "FIELD_2"}, array in object:register_types.DB_RESERVED_REG_2.fields.1 12840 {"bits": [8, 12], "name": "FIELD_3"}, array in object:register_types.DB_RESERVED_REG_2.fields.2 12841 {"bits": [13, 14], "name": "FIELD_4"}, array in object:register_types.DB_RESERVED_REG_2.fields.3 12842 {"bits": [15, 16], "name": "FIELD_5"}, array in object:register_types.DB_RESERVED_REG_2.fields.4 12843 {"bits": [17, 18], "name": "FIELD_6"}, array in object:register_types.DB_RESERVED_REG_2.fields.5 12844 {"bits": [19, 20], "name": "FIELD_7"}, array in object:register_types.DB_RESERVED_REG_2.fields.6 12845 {"bits": [28, 31], "name": "RESOURCE_LEVEL"} array in object:register_types.DB_RESERVED_REG_2.fields.7 12850 {"bits": [0, 21], "name": "FIELD_1"} array in object:register_types.DB_RESERVED_REG_3.fields.0 12855 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.0 12856 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.1 12857 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.2 12858 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.3 12859 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.4 12860 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.5 12861 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.6 12862 {"bits": [24, 24], "name": "Z_BIG_PAGE"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.7 12863 {"bits": [25, 25], "name": "S_BIG_PAGE"} array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.8 12868 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.0 12869 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.1 12870 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.2 12871 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, array in object:register_types.DB_SHADER_CONTROL.fields.3 12872 {"bits": [6, 6], "name": "KILL_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.4 12873 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.5 12874 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.6 12875 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, array in object:register_types.DB_SHADER_CONTROL.fields.7 12876 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, array in object:register_types.DB_SHADER_CONTROL.fields.8 12877 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.9 12878 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.10 12879 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, array in object:register_types.DB_SHADER_CONTROL.fields.11 12880 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.12 12881 {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.13 12882 {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"}, array in object:register_types.DB_SHADER_CONTROL.fields.14 12883 {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"}, array in object:register_types.DB_SHADER_CONTROL.fields.15 12884 {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"} array in object:register_types.DB_SHADER_CONTROL.fields.16 12889 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0 12890 {"bits": [4, 11], "name": "COMPAREVALUE0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.1 12891 {"bits": [12, 19], "name": "COMPAREMASK0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.2 12892 {"bits": [24, 24], "name": "ENABLE0"} array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.3 12897 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0 12898 {"bits": [4, 11], "name": "COMPAREVALUE1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.1 12899 {"bits": [12, 19], "name": "COMPAREMASK1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.2 12900 {"bits": [24, 24], "name": "ENABLE1"} array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.3 12905 {"bits": [0, 7], "name": "STENCILTESTVAL"}, array in object:register_types.DB_STENCILREFMASK.fields.0 12906 {"bits": [8, 15], "name": "STENCILMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.1 12907 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.2 12908 {"bits": [24, 31], "name": "STENCILOPVAL"} array in object:register_types.DB_STENCILREFMASK.fields.3 12913 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.0 12914 {"bits": [8, 15], "name": "STENCILMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.1 12915 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.2 12916 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} array in object:register_types.DB_STENCILREFMASK_BF.fields.3 12921 {"bits": [0, 7], "name": "CLEAR"} array in object:register_types.DB_STENCIL_CLEAR.fields.0 12926 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.0 12927 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, array in object:register_types.DB_STENCIL_CONTROL.fields.1 12928 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.2 12929 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.3 12930 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.4 12931 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} array in object:register_types.DB_STENCIL_CONTROL.fields.5 12936 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, array in object:register_types.DB_STENCIL_INFO.fields.0 12937 {"bits": [4, 8], "name": "SW_MODE"}, array in object:register_types.DB_STENCIL_INFO.fields.1 12938 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, array in object:register_types.DB_STENCIL_INFO.fields.2 12939 {"bits": [11, 11], "name": "ITERATE_FLUSH"}, array in object:register_types.DB_STENCIL_INFO.fields.3 12940 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, array in object:register_types.DB_STENCIL_INFO.fields.4 12941 {"bits": [13, 15], "name": "RESERVED_FIELD_1"}, array in object:register_types.DB_STENCIL_INFO.fields.5 12942 {"bits": [20, 20], "name": "ITERATE_256"}, array in object:register_types.DB_STENCIL_INFO.fields.6 12943 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_STENCIL_INFO.fields.7 12944 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} array in object:register_types.DB_STENCIL_INFO.fields.8 12949 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, array in object:register_types.DB_Z_INFO.fields.0 12950 {"bits": [2, 3], "name": "NUM_SAMPLES"}, array in object:register_types.DB_Z_INFO.fields.1 12951 {"bits": [4, 8], "name": "SW_MODE"}, array in object:register_types.DB_Z_INFO.fields.2 12952 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, array in object:register_types.DB_Z_INFO.fields.3 12953 {"bits": [11, 11], "name": "ITERATE_FLUSH"}, array in object:register_types.DB_Z_INFO.fields.4 12954 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, array in object:register_types.DB_Z_INFO.fields.5 12955 {"bits": [13, 15], "name": "RESERVED_FIELD_1"}, array in object:register_types.DB_Z_INFO.fields.6 12956 {"bits": [16, 19], "name": "MAXMIP"}, array in object:register_types.DB_Z_INFO.fields.7 12957 {"bits": [20, 20], "name": "ITERATE_256"}, array in object:register_types.DB_Z_INFO.fields.8 12958 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"}, array in object:register_types.DB_Z_INFO.fields.9 12959 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_Z_INFO.fields.10 12960 {"bits": [28, 28], "name": "READ_SIZE"}, array in object:register_types.DB_Z_INFO.fields.11 12961 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, array in object:register_types.DB_Z_INFO.fields.12 12962 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} array in object:register_types.DB_Z_INFO.fields.13 12967 {"bits": [0, 7], "name": "BASE_HI"} array in object:register_types.DB_Z_READ_BASE_HI.fields.0 12972 {"bits": [0, 2], "name": "NUM_PIPES"}, array in object:register_types.GB_ADDR_CONFIG.fields.0 12973 {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.1 12974 {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"}, array in object:register_types.GB_ADDR_CONFIG.fields.2 12975 {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"}, array in object:register_types.GB_ADDR_CONFIG.fields.3 12976 {"bits": [26, 27], "name": "NUM_RB_PER_SE"} array in object:register_types.GB_ADDR_CONFIG.fields.4 12981 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, array in object:register_types.GB_MACROTILE_MODE0.fields.0 12982 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.1 12983 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.2 12984 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} array in object:register_types.GB_MACROTILE_MODE0.fields.3 12989 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.GB_TILE_MODE0.fields.0 12990 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.GB_TILE_MODE0.fields.1 12991 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.GB_TILE_MODE0.fields.2 12992 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, array in object:register_types.GB_TILE_MODE0.fields.3 12993 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} array in object:register_types.GB_TILE_MODE0.fields.4 12998 {"bits": [0, 1], "name": "COMPARE_MODE0"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.0 12999 {"bits": [2, 3], "name": "COMPARE_MODE1"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.1 13000 {"bits": [4, 5], "name": "COMPARE_MODE2"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.2 13001 {"bits": [6, 7], "name": "COMPARE_MODE3"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.3 13002 {"bits": [8, 11], "name": "COMPARE_VALUE0"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.4 13003 {"bits": [12, 15], "name": "COMPARE_VALUE1"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.5 13004 {"bits": [16, 19], "name": "COMPARE_VALUE2"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.6 13005 {"bits": [20, 23], "name": "COMPARE_VALUE3"} array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.7 13010 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.GCR_PERFCOUNTER1_SELECT.fields.0 13011 {"bits": [24, 27], "name": "PERF_MODE"}, array in object:register_types.GCR_PERFCOUNTER1_SELECT.fields.1 13012 {"bits": [28, 31], "name": "CNTL_MODE"} array in object:register_types.GCR_PERFCOUNTER1_SELECT.fields.2 13017 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER0_CFG.fields.0 13018 {"bits": [8, 15], "name": "PERF_SEL_END"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER0_CFG.fields.1 13019 {"bits": [24, 27], "name": "PERF_MODE"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER0_CFG.fields.2 13020 {"bits": [28, 28], "name": "ENABLE"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER0_CFG.fields.3 13021 {"bits": [29, 29], "name": "CLEAR"} array in object:register_types.GC_ATC_L2_PERFCOUNTER0_CFG.fields.4 13026 {"bits": [0, 15], "name": "COUNTER_HI"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER_HI.fields.0 13027 {"bits": [16, 31], "name": "COMPARE_VALUE"} array in object:register_types.GC_ATC_L2_PERFCOUNTER_HI.fields.1 13032 {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.0 13033 {"bits": [8, 15], "name": "START_TRIGGER"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.1 13034 {"bits": [16, 23], "name": "STOP_TRIGGER"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.2 13035 {"bits": [24, 24], "name": "ENABLE_ANY"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.3 13036 {"bits": [25, 25], "name": "CLEAR_ALL"}, array in object:register_types.GC_ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.4 13037 {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"} array in object:register_types.GC_ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.5 13042 {"bits": [0, 15], "name": "BASE"}, array in object:register_types.GDS_ATOM_BASE.fields.0 13043 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_BASE.fields.1 13048 {"bits": [0, 5], "name": "AINC"}, array in object:register_types.GDS_ATOM_CNTL.fields.0 13049 {"bits": [6, 7], "name": "UNUSED1"}, array in object:register_types.GDS_ATOM_CNTL.fields.1 13050 {"bits": [8, 9], "name": "DMODE"}, array in object:register_types.GDS_ATOM_CNTL.fields.2 13051 {"bits": [10, 31], "name": "UNUSED2"} array in object:register_types.GDS_ATOM_CNTL.fields.3 13056 {"bits": [0, 0], "name": "COMPLETE"}, array in object:register_types.GDS_ATOM_COMPLETE.fields.0 13057 {"bits": [1, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_COMPLETE.fields.1 13062 {"bits": [0, 7], "name": "OFFSET0"}, array in object:register_types.GDS_ATOM_OFFSET0.fields.0 13063 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET0.fields.1 13068 {"bits": [0, 7], "name": "OFFSET1"}, array in object:register_types.GDS_ATOM_OFFSET1.fields.0 13069 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET1.fields.1 13074 {"bits": [0, 7], "name": "OP"}, array in object:register_types.GDS_ATOM_OP.fields.0 13075 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OP.fields.1 13080 {"bits": [0, 15], "name": "SIZE"}, array in object:register_types.GDS_ATOM_SIZE.fields.0 13081 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_SIZE.fields.1 13086 {"bits": [0, 0], "name": "FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.0 13087 {"bits": [1, 12], "name": "COUNTER"}, array in object:register_types.GDS_GWS_RESOURCE.fields.1 13088 {"bits": [13, 13], "name": "TYPE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.2 13089 {"bits": [14, 14], "name": "DED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.3 13090 {"bits": [15, 15], "name": "RELEASE_ALL"}, array in object:register_types.GDS_GWS_RESOURCE.fields.4 13091 {"bits": [16, 26], "name": "HEAD_QUEUE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.5 13092 {"bits": [27, 27], "name": "HEAD_VALID"}, array in object:register_types.GDS_GWS_RESOURCE.fields.6 13093 {"bits": [28, 28], "name": "HEAD_FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.7 13094 {"bits": [29, 29], "name": "HALTED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.8 13095 {"bits": [30, 31], "name": "UNUSED1"} array in object:register_types.GDS_GWS_RESOURCE.fields.9 13100 {"bits": [0, 15], "name": "RESOURCE_CNT"}, array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.0 13101 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.1 13106 {"bits": [0, 5], "name": "INDEX"}, array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.0 13107 {"bits": [6, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.1 13112 {"bits": [0, 15], "name": "DS_ADDRESS"}, array in object:register_types.GDS_OA_ADDRESS.fields.0 13113 {"bits": [16, 19], "name": "CRAWLER_TYPE"}, array in object:register_types.GDS_OA_ADDRESS.fields.1 13114 {"bits": [20, 23], "name": "CRAWLER"}, array in object:register_types.GDS_OA_ADDRESS.fields.2 13115 {"bits": [24, 29], "name": "UNUSED"}, array in object:register_types.GDS_OA_ADDRESS.fields.3 13116 {"bits": [30, 30], "name": "NO_ALLOC"}, array in object:register_types.GDS_OA_ADDRESS.fields.4 13117 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.GDS_OA_ADDRESS.fields.5 13122 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.GDS_OA_CNTL.fields.0 13123 {"bits": [4, 31], "name": "UNUSED"} array in object:register_types.GDS_OA_CNTL.fields.1 13128 {"bits": [0, 30], "name": "VALUE"}, array in object:register_types.GDS_OA_INCDEC.fields.0 13129 {"bits": [31, 31], "name": "INCDEC"} array in object:register_types.GDS_OA_INCDEC.fields.1 13134 {"bits": [0, 8], "name": "PRIM_GRP_SIZE"}, array in object:register_types.GE_CNTL.fields.0 13135 {"bits": [9, 17], "name": "VERT_GRP_SIZE"}, array in object:register_types.GE_CNTL.fields.1 13136 {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"}, array in object:register_types.GE_CNTL.fields.2 13137 {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"} array in object:register_types.GE_CNTL.fields.3 13142 {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"} array in object:register_types.GE_MAX_OUTPUT_PER_SUBGROUP.fields.0 13147 {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"}, array in object:register_types.GE_NGG_SUBGRP_CNTL.fields.0 13148 {"bits": [9, 17], "name": "THDS_PER_SUBGRP"} array in object:register_types.GE_NGG_SUBGRP_CNTL.fields.1 13153 {"bits": [0, 0], "name": "OVERSUB_EN"}, array in object:register_types.GE_PC_ALLOC.fields.0 13154 {"bits": [1, 10], "name": "NUM_PC_LINES"} array in object:register_types.GE_PC_ALLOC.fields.1 13159 {"bits": [0, 9], "name": "PERF_SEL0"}, array in object:register_types.GE_PERFCOUNTER0_SELECT.fields.0 13160 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.GE_PERFCOUNTER0_SELECT.fields.1 13161 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.GE_PERFCOUNTER0_SELECT.fields.2 13162 {"bits": [24, 27], "name": "PERF_MODE0"}, array in object:register_types.GE_PERFCOUNTER0_SELECT.fields.3 13163 {"bits": [28, 31], "name": "PERF_MODE1"} array in object:register_types.GE_PERFCOUNTER0_SELECT.fields.4 13168 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.GE_PERFCOUNTER0_SELECT1.fields.0 13169 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.GE_PERFCOUNTER0_SELECT1.fields.1 13170 {"bits": [24, 27], "name": "PERF_MODE2"}, array in object:register_types.GE_PERFCOUNTER0_SELECT1.fields.2 13171 {"bits": [28, 31], "name": "PERF_MODE3"} array in object:register_types.GE_PERFCOUNTER0_SELECT1.fields.3 13176 {"bits": [0, 9], "name": "PERF_SEL0"}, array in object:register_types.GE_PERFCOUNTER4_SELECT.fields.0 13177 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.GE_PERFCOUNTER4_SELECT.fields.1 13182 {"bits": [0, 2], "name": "RT_SLICE"}, array in object:register_types.GE_STEREO_CNTL.fields.0 13183 {"bits": [3, 6], "name": "VIEWPORT"}, array in object:register_types.GE_STEREO_CNTL.fields.1 13184 {"bits": [8, 8], "name": "EN_STEREO"} array in object:register_types.GE_STEREO_CNTL.fields.2 13189 {"bits": [0, 0], "name": "EN_USER_VGPR1"}, array in object:register_types.GE_USER_VGPR_EN.fields.0 13190 {"bits": [1, 1], "name": "EN_USER_VGPR2"}, array in object:register_types.GE_USER_VGPR_EN.fields.1 13191 {"bits": [2, 2], "name": "EN_USER_VGPR3"} array in object:register_types.GE_USER_VGPR_EN.fields.2 13196 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.0 13197 {"bits": [8, 15], "name": "SA_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.1 13198 {"bits": [16, 23], "name": "SE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.2 13199 {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.3 13200 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.4 13201 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} array in object:register_types.GRBM_GFX_INDEX.fields.5 13206 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.0 13207 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.1 13208 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.2 13209 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.3 13210 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.4 13211 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.5 13212 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.6 13213 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.7 13214 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.8 13215 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.9 13216 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.10 13217 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.11 13218 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.12 13219 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.13 13220 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.14 13221 {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.15 13222 {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.16 13223 {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.17 13224 {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.18 13225 {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.19 13230 {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.0 13231 {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.1 13232 {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.2 13233 {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.3 13234 {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.4 13235 {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.5 13236 {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.6 13237 {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.7 13242 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.0 13243 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.1 13244 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.2 13245 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.3 13246 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.4 13247 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.5 13248 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.6 13249 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.7 13250 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.8 13251 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.9 13252 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.10 13253 {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.11 13254 {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.12 13255 {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.13 13256 {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.14 13261 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS.fields.0 13262 {"bits": [5, 5], "name": "RSMU_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.1 13263 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.2 13264 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.3 13265 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.4 13266 {"bits": [12, 12], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.5 13267 {"bits": [13, 13], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.6 13268 {"bits": [14, 14], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.7 13269 {"bits": [15, 15], "name": "GDS_BUSY"}, array in object:register_types.GRBM_STATUS.fields.8 13270 {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.9 13271 {"bits": [20, 20], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS.fields.10 13272 {"bits": [21, 21], "name": "GE_BUSY"}, array in object:register_types.GRBM_STATUS.fields.11 13273 {"bits": [22, 22], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.12 13274 {"bits": [23, 23], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.13 13275 {"bits": [24, 24], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS.fields.14 13276 {"bits": [25, 25], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.15 13277 {"bits": [26, 26], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.16 13278 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, array in object:register_types.GRBM_STATUS.fields.17 13279 {"bits": [29, 29], "name": "CP_BUSY"}, array in object:register_types.GRBM_STATUS.fields.18 13280 {"bits": [30, 30], "name": "CB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.19 13281 {"bits": [31, 31], "name": "GUI_ACTIVE"} array in object:register_types.GRBM_STATUS.fields.20 13286 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS2.fields.0 13287 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.1 13288 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.2 13289 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.3 13290 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.4 13291 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.5 13292 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.6 13293 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.7 13294 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.8 13295 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.9 13296 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.10 13297 {"bits": [14, 14], "name": "RLC_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.11 13298 {"bits": [15, 15], "name": "UTCL2_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.12 13299 {"bits": [16, 16], "name": "EA_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.13 13300 {"bits": [17, 17], "name": "RMI_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.14 13301 {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.15 13302 {"bits": [19, 19], "name": "CPF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.16 13303 {"bits": [20, 20], "name": "EA_LINK_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.17 13304 {"bits": [21, 21], "name": "SDMA_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.18 13305 {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.19 13306 {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.20 13307 {"bits": [24, 24], "name": "RLC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.21 13308 {"bits": [25, 25], "name": "TCP_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.22 13309 {"bits": [28, 28], "name": "CPF_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.23 13310 {"bits": [29, 29], "name": "CPC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.24 13311 {"bits": [30, 30], "name": "CPG_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.25 13312 {"bits": [31, 31], "name": "CPAXI_BUSY"} array in object:register_types.GRBM_STATUS2.fields.26 13317 {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.0 13318 {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.1 13319 {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.2 13320 {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.3 13321 {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.4 13322 {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.5 13323 {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.6 13324 {"bits": [13, 13], "name": "PH_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.7 13325 {"bits": [14, 14], "name": "CH_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.8 13326 {"bits": [15, 15], "name": "GL2CC_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.9 13327 {"bits": [16, 16], "name": "GL1CC_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.10 13328 {"bits": [28, 28], "name": "GUS_LINK_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.11 13329 {"bits": [29, 29], "name": "GUS_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.12 13330 {"bits": [30, 30], "name": "UTCL1_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.13 13331 {"bits": [31, 31], "name": "PMM_BUSY"} array in object:register_types.GRBM_STATUS3.fields.14 13336 {"bits": [1, 1], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.0 13337 {"bits": [2, 2], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.1 13338 {"bits": [3, 3], "name": "UTCL1_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.2 13339 {"bits": [4, 4], "name": "TCP_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.3 13340 {"bits": [5, 5], "name": "GL1CC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.4 13341 {"bits": [21, 21], "name": "RMI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.5 13342 {"bits": [22, 22], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.6 13343 {"bits": [24, 24], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.7 13344 {"bits": [25, 25], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.8 13345 {"bits": [26, 26], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.9 13346 {"bits": [27, 27], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.10 13347 {"bits": [29, 29], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.11 13348 {"bits": [30, 30], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.12 13349 {"bits": [31, 31], "name": "CB_BUSY"} array in object:register_types.GRBM_STATUS_SE0.fields.13 13354 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.0 13355 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.1 13356 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.2 13357 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.3 13358 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.4 13359 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} array in object:register_types.IA_MULTI_VGT_PARAM.fields.5 13364 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.0 13365 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.1 13366 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.2 13367 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.3 13368 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.4 13369 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.5 13370 {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.6 13371 {"bits": [22, 22], "name": "EN_INST_OPT_ADV"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.7 13372 {"bits": [23, 23], "name": "HW_USE_ONLY"} array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.8 13377 {"bits": [0, 0], "name": "UCP_ENA_0"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.0 13378 {"bits": [1, 1], "name": "UCP_ENA_1"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.1 13379 {"bits": [2, 2], "name": "UCP_ENA_2"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.2 13380 {"bits": [3, 3], "name": "UCP_ENA_3"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.3 13381 {"bits": [4, 4], "name": "UCP_ENA_4"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.4 13382 {"bits": [5, 5], "name": "UCP_ENA_5"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.5 13383 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.6 13384 {"bits": [14, 15], "name": "PS_UCP_MODE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.7 13385 {"bits": [16, 16], "name": "CLIP_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.8 13386 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.9 13387 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.10 13388 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.11 13389 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.12 13390 {"bits": [21, 21], "name": "VTX_KILL_OR"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.13 13391 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.14 13392 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.15 13393 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.16 13394 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.17 13395 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.18 13396 {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"} array in object:register_types.PA_CL_CLIP_CNTL.fields.19 13401 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.0 13402 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.1 13403 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.2 13404 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.3 13405 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.4 13406 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.5 13407 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.6 13408 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.7 13409 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.8 13410 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.9 13411 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.10 13412 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.11 13413 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.12 13414 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.13 13415 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.14 13416 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} array in object:register_types.PA_CL_NANINF_CNTL.fields.15 13421 {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"}, array in object:register_types.PA_CL_NGG_CNTL.fields.0 13422 {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"} array in object:register_types.PA_CL_NGG_CNTL.fields.1 13427 {"bits": [0, 0], "name": "OBJ_ID_SEL"}, array in object:register_types.PA_CL_OBJPRIM_ID_CNTL.fields.0 13428 {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"} array in object:register_types.PA_CL_OBJPRIM_ID_CNTL.fields.1 13433 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.0 13434 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.1 13435 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.2 13436 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.3 13437 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.4 13438 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.5 13439 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.6 13440 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.7 13441 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.8 13442 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.9 13443 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.10 13444 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.11 13445 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.12 13446 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.13 13447 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.14 13448 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.15 13449 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.16 13450 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.17 13451 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.18 13452 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.19 13453 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.20 13454 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.21 13455 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.22 13456 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.23 13457 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.24 13458 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.25 13459 {"bits": [26, 26], "name": "USE_VTX_SHD_OBJPRIM_ID"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.26 13460 {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"} array in object:register_types.PA_CL_VS_OUT_CNTL.fields.27 13465 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.0 13466 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.1 13467 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.2 13468 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.3 13469 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.4 13470 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.5 13471 {"bits": [8, 8], "name": "VTX_XY_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.6 13472 {"bits": [9, 9], "name": "VTX_Z_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.7 13473 {"bits": [10, 10], "name": "VTX_W0_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.8 13474 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} array in object:register_types.PA_CL_VTE_CNTL.fields.9 13479 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.0 13480 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, array in object:register_types.PA_SC_AA_CONFIG.fields.1 13481 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, array in object:register_types.PA_SC_AA_CONFIG.fields.2 13482 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.3 13483 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}, array in object:register_types.PA_SC_AA_CONFIG.fields.4 13484 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"} array in object:register_types.PA_SC_AA_CONFIG.fields.5 13489 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.0 13490 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.1 13495 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.0 13496 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.1 13501 {"bits": [0, 3], "name": "S0_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.0 13502 {"bits": [4, 7], "name": "S0_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.1 13503 {"bits": [8, 11], "name": "S1_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.2 13504 {"bits": [12, 15], "name": "S1_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.3 13505 {"bits": [16, 19], "name": "S2_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.4 13506 {"bits": [20, 23], "name": "S2_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.5 13507 {"bits": [24, 27], "name": "S3_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.6 13508 {"bits": [28, 31], "name": "S3_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.7 13513 {"bits": [0, 3], "name": "S4_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.0 13514 {"bits": [4, 7], "name": "S4_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.1 13515 {"bits": [8, 11], "name": "S5_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.2 13516 {"bits": [12, 15], "name": "S5_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.3 13517 {"bits": [16, 19], "name": "S6_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.4 13518 {"bits": [20, 23], "name": "S6_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.5 13519 {"bits": [24, 27], "name": "S7_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.6 13520 {"bits": [28, 31], "name": "S7_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.7 13525 {"bits": [0, 3], "name": "S8_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.0 13526 {"bits": [4, 7], "name": "S8_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.1 13527 {"bits": [8, 11], "name": "S9_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.2 13528 {"bits": [12, 15], "name": "S9_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.3 13529 {"bits": [16, 19], "name": "S10_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.4 13530 {"bits": [20, 23], "name": "S10_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.5 13531 {"bits": [24, 27], "name": "S11_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.6 13532 {"bits": [28, 31], "name": "S11_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.7 13537 {"bits": [0, 3], "name": "S12_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.0 13538 {"bits": [4, 7], "name": "S12_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.1 13539 {"bits": [8, 11], "name": "S13_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.2 13540 {"bits": [12, 15], "name": "S13_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.3 13541 {"bits": [16, 19], "name": "S14_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.4 13542 {"bits": [20, 23], "name": "S14_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.5 13543 {"bits": [24, 27], "name": "S15_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.6 13544 {"bits": [28, 31], "name": "S15_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.7 13549 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.0 13550 {"bits": [2, 2], "name": "BIN_SIZE_X"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.1 13551 {"bits": [3, 3], "name": "BIN_SIZE_Y"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.2 13552 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.3 13553 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.4 13554 {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.5 13555 {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.6 13556 {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.7 13557 {"bits": [19, 26], "name": "FPOVS_PER_BATCH"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.8 13558 {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.9 13559 {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.10 13560 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"} array in object:register_types.PA_SC_BINNER_CNTL_0.fields.11 13565 {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"}, array in object:register_types.PA_SC_BINNER_CNTL_1.fields.0 13566 {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"} array in object:register_types.PA_SC_BINNER_CNTL_1.fields.1 13571 {"bits": [0, 3], "name": "DISTANCE_0"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.0 13572 {"bits": [4, 7], "name": "DISTANCE_1"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.1 13573 {"bits": [8, 11], "name": "DISTANCE_2"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.2 13574 {"bits": [12, 15], "name": "DISTANCE_3"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.3 13575 {"bits": [16, 19], "name": "DISTANCE_4"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.4 13576 {"bits": [20, 23], "name": "DISTANCE_5"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.5 13577 {"bits": [24, 27], "name": "DISTANCE_6"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.6 13578 {"bits": [28, 31], "name": "DISTANCE_7"} array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.7 13583 {"bits": [0, 3], "name": "DISTANCE_8"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.0 13584 {"bits": [4, 7], "name": "DISTANCE_9"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.1 13585 {"bits": [8, 11], "name": "DISTANCE_10"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.2 13586 {"bits": [12, 15], "name": "DISTANCE_11"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.3 13587 {"bits": [16, 19], "name": "DISTANCE_12"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.4 13588 {"bits": [20, 23], "name": "DISTANCE_13"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.5 13589 {"bits": [24, 27], "name": "DISTANCE_14"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.6 13590 {"bits": [28, 31], "name": "DISTANCE_15"} array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.7 13595 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.0 13596 {"bits": [16, 30], "name": "TL_Y"} array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.1 13601 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} array in object:register_types.PA_SC_CLIPRECT_RULE.fields.0 13606 {"bits": [0, 0], "name": "OVER_RAST_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.0 13607 {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.1 13608 {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.2 13609 {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.3 13610 {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.4 13611 {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.5 13612 {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.6 13613 {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.7 13614 {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.8 13615 {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.9 13616 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE" array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.10 13617 {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.11 13618 {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.12 13619 {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.13 13620 {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.14 13621 {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.15 13622 {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.16 13623 {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.17 13624 {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.18 13625 {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"} array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.19 13630 {"bits": [0, 3], "name": "ER_TRI"}, array in object:register_types.PA_SC_EDGERULE.fields.0 13631 {"bits": [4, 7], "name": "ER_POINT"}, array in object:register_types.PA_SC_EDGERULE.fields.1 13632 {"bits": [8, 11], "name": "ER_RECT"}, array in object:register_types.PA_SC_EDGERULE.fields.2 13633 {"bits": [12, 17], "name": "ER_LINE_LR"}, array in object:register_types.PA_SC_EDGERULE.fields.3 13634 {"bits": [18, 23], "name": "ER_LINE_RL"}, array in object:register_types.PA_SC_EDGERULE.fields.4 13635 {"bits": [24, 27], "name": "ER_LINE_TB"}, array in object:register_types.PA_SC_EDGERULE.fields.5 13636 {"bits": [28, 31], "name": "ER_LINE_BT"} array in object:register_types.PA_SC_EDGERULE.fields.6 13641 {"bits": [0, 7], "name": "TOP_QTR"}, array in object:register_types.PA_SC_HORIZ_GRID.fields.0 13642 {"bits": [8, 15], "name": "TOP_HALF"}, array in object:register_types.PA_SC_HORIZ_GRID.fields.1 13643 {"bits": [16, 23], "name": "BOT_HALF"}, array in object:register_types.PA_SC_HORIZ_GRID.fields.2 13644 {"bits": [24, 31], "name": "BOT_QTR"} array in object:register_types.PA_SC_HORIZ_GRID.fields.3 13649 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, array in object:register_types.PA_SC_LINE_CNTL.fields.0 13650 {"bits": [10, 10], "name": "LAST_PIXEL"}, array in object:register_types.PA_SC_LINE_CNTL.fields.1 13651 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.2 13652 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.3 13653 {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"} array in object:register_types.PA_SC_LINE_CNTL.fields.4 13658 {"bits": [0, 15], "name": "LINE_PATTERN"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.0 13659 {"bits": [16, 23], "name": "REPEAT_COUNT"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.1 13660 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.2 13661 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} array in object:register_types.PA_SC_LINE_STIPPLE.fields.3 13666 {"bits": [0, 3], "name": "CURRENT_PTR"}, array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.0 13667 {"bits": [8, 15], "name": "CURRENT_COUNT"} array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.1 13672 {"bits": [0, 0], "name": "MSAA_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.0 13673 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.1 13674 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.2 13675 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.3 13676 {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.4 13677 {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.5 13678 {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"} array in object:register_types.PA_SC_MODE_CNTL_0.fields.6 13683 {"bits": [0, 0], "name": "WALK_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.0 13684 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.1 13685 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.2 13686 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.3 13687 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.4 13688 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.5 13689 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.6 13690 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.7 13691 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.8 13692 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.9 13693 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.10 13694 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.11 13695 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.12 13696 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.13 13697 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.14 13698 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.15 13699 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.16 13700 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.17 13701 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.18 13702 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.19 13703 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.20 13704 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.21 13705 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.22 13706 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} array in object:register_types.PA_SC_MODE_CNTL_1.fields.23 13711 {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"}, array in object:register_types.PA_SC_NGG_MODE_CNTL.fields.0 13712 {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"} array in object:register_types.PA_SC_NGG_MODE_CNTL.fields.1 13717 {"bits": [0, 13], "name": "X_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_H.fields.0 13722 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"}, array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.0 13723 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.1 13728 {"bits": [0, 15], "name": "COUNT"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_OCCURRENCE.fields.0 13733 {"bits": [0, 13], "name": "Y_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_V.fields.0 13738 {"bits": [0, 9], "name": "PERF_SEL"} array in object:register_types.PA_SC_PERFCOUNTER1_SELECT.fields.0 13743 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.0 13744 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.1 13745 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.2 13746 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.3 13747 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.4 13748 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.5 13749 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.6 13750 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.7 13751 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.8 13752 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.9 13753 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.10 13754 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.11 13755 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.12 13756 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.13 13757 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG.fields.14 13762 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0 13763 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1 13764 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2 13769 {"bits": [0, 7], "name": "LEFT_QTR"}, array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.0 13770 {"bits": [8, 15], "name": "LEFT_HALF"}, array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.1 13771 {"bits": [16, 23], "name": "RIGHT_HALF"}, array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.2 13772 {"bits": [24, 31], "name": "RIGHT_QTR"} array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.3 13777 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.0 13778 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"} array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.1 13783 {"bits": [0, 15], "name": "X"}, array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.0 13784 {"bits": [16, 31], "name": "Y"} array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.1 13789 {"bits": [0, 15], "name": "BR_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.0 13790 {"bits": [16, 31], "name": "BR_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.1 13795 {"bits": [0, 15], "name": "TL_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.0 13796 {"bits": [16, 31], "name": "TL_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.1 13801 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.0 13802 {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.1 13803 {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.2 13804 {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"} array in object:register_types.PA_SC_SHADER_CONTROL.fields.3 13809 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.0 13810 {"bits": [1, 2], "name": "NUM_SE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.1 13811 {"bits": [5, 6], "name": "NUM_RB_PER_SE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.2 13812 {"bits": [8, 8], "name": "DISABLE_SRBSL_DB_OPTIMIZED_PACKING"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.3 13813 {"bits": [12, 13], "name": "NUM_SC"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.4 13814 {"bits": [16, 17], "name": "NUM_RB_PER_SC"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.5 13815 {"bits": [20, 20], "name": "NUM_PACKER_PER_SC"} array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.6 13820 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, array in object:register_types.PA_SC_WINDOW_OFFSET.fields.0 13821 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} array in object:register_types.PA_SC_WINDOW_OFFSET.fields.1 13826 {"bits": [0, 14], "name": "BR_X"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_BR.fields.0 13827 {"bits": [16, 30], "name": "BR_Y"} array in object:register_types.PA_SC_WINDOW_SCISSOR_BR.fields.1 13832 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.0 13833 {"bits": [16, 30], "name": "TL_Y"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.1 13834 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.2 13839 {"bits": [1, 4], "name": "STEREO_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.0 13840 {"bits": [5, 7], "name": "RT_SLICE_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.1 13841 {"bits": [8, 11], "name": "RT_SLICE_OFFSET"}, array in object:register_types.PA_STEREO_CNTL.fields.2 13842 {"bits": [16, 18], "name": "VP_ID_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.3 13843 {"bits": [19, 22], "name": "VP_ID_OFFSET"} array in object:register_types.PA_STEREO_CNTL.fields.4 13848 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.0 13849 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.1 13854 {"bits": [0, 15], "name": "WIDTH"} array in object:register_types.PA_SU_LINE_CNTL.fields.0 13859 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.0 13860 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.1 13861 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.2 13862 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.3 13867 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} array in object:register_types.PA_SU_LINE_STIPPLE_VALUE.fields.0 13872 {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.0 13873 {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.1 13874 {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.2 13875 {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.3 13876 {"bits": [4, 4], "name": "USE_PROVOKING_ZW"} array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.4 13881 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} array in object:register_types.PA_SU_PERFCOUNTER0_HI.fields.0 13886 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.0 13887 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.1 13888 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.2 13889 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.3 13890 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.4 13895 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.0 13896 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.1 13897 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.2 13898 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.3 13903 {"bits": [0, 15], "name": "MIN_SIZE"}, array in object:register_types.PA_SU_POINT_MINMAX.fields.0 13904 {"bits": [16, 31], "name": "MAX_SIZE"} array in object:register_types.PA_SU_POINT_MINMAX.fields.1 13909 {"bits": [0, 15], "name": "HEIGHT"}, array in object:register_types.PA_SU_POINT_SIZE.fields.0 13910 {"bits": [16, 31], "name": "WIDTH"} array in object:register_types.PA_SU_POINT_SIZE.fields.1 13915 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.0 13916 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.1 13921 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.0 13922 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.1 13923 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.2 13924 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.3 13925 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.4 13926 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.5 13927 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.6 13928 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.7 13929 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.8 13930 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.9 13931 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.10 13936 {"bits": [0, 0], "name": "CULL_FRONT"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.0 13937 {"bits": [1, 1], "name": "CULL_BACK"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.1 13938 {"bits": [2, 2], "name": "FACE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.2 13939 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.3 13940 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ array in object:register_types.PA_SU_SC_MODE_CNTL.fields.4 13941 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE array in object:register_types.PA_SU_SC_MODE_CNTL.fields.5 13942 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.6 13943 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.7 13944 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.8 13945 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.9 13946 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.10 13947 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.11 13948 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.12 13949 {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.13 13950 {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.14 13951 {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"} array in object:register_types.PA_SU_SC_MODE_CNTL.fields.15 13956 {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.0 13957 {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.1 13958 {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.2 13959 {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.3 13960 {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.4 13961 {"bits": [5, 5], "name": "SRBSL_ENABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.5 13962 {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"} array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.6 13967 {"bits": [0, 0], "name": "PIX_CENTER"}, array in object:register_types.PA_SU_VTX_CNTL.fields.0 13968 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, array in object:register_types.PA_SU_VTX_CNTL.fields.1 13969 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} array in object:register_types.PA_SU_VTX_CNTL.fields.2 13974 {"bits": [0, 3], "name": "FEATURE_SEL"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.0 13975 {"bits": [4, 7], "name": "SE_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.1 13976 {"bits": [8, 11], "name": "SA_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.2 13977 {"bits": [12, 15], "name": "WGP_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.3 13978 {"bits": [16, 17], "name": "EVENT_SEL"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.4 13979 {"bits": [18, 19], "name": "UNUSED"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.5 13980 {"bits": [20, 20], "name": "ENABLE"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.6 13981 {"bits": [21, 31], "name": "RESERVED"} array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.7 13986 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.0 13987 {"bits": [1, 1], "name": "MODE_SELECT"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.1 13988 {"bits": [2, 2], "name": "RESET"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.2 13989 {"bits": [3, 31], "name": "RESERVED"} array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.3 13994 {"bits": [0, 3], "name": "VFID"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.0 13995 {"bits": [4, 5], "name": "CNT_ID"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.1 13996 {"bits": [6, 31], "name": "RESERVED"} array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.2 14001 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"} array in object:register_types.RLC_PERFCOUNTER0_SELECT.fields.0 14006 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"} array in object:register_types.RLC_PERFMON_CLK_CNTL.fields.0 14011 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.RLC_PERFMON_CNTL.fields.0 14012 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.RLC_PERFMON_CNTL.fields.1 14017 {"bits": [0, 0], "name": "StrobeResetPerfMonitors"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.0 14018 {"bits": [1, 1], "name": "StrobeStartAccumulation"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.1 14019 {"bits": [2, 2], "name": "StrobeRearmAccum"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.2 14020 {"bits": [3, 3], "name": "StrobeSpmDoneInt"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.3 14021 {"bits": [4, 4], "name": "StrobeAccumDoneInt"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.4 14022 {"bits": [5, 5], "name": "StrobeResetAccum"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.5 14023 {"bits": [6, 9], "name": "StrobeStartSpm"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.6 14024 {"bits": [10, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.7 14029 {"bits": [0, 8], "name": "addr"}, array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR.fields.0 14030 {"bits": [9, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR.fields.1 14035 {"bits": [0, 7], "name": "data"}, array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_DATA.fields.0 14036 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_DATA.fields.1 14041 {"bits": [0, 6], "name": "addr"}, array in object:register_types.RLC_SPM_ACCUM_DATARAM_ADDR.fields.0 14042 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_DATARAM_ADDR.fields.1 14047 {"bits": [0, 18], "name": "DataRamWrCount"}, array in object:register_types.RLC_SPM_ACCUM_DATARAM_WRCOUNT.fields.0 14048 {"bits": [19, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_DATARAM_WRCOUNT.fields.1 14053 {"bits": [0, 0], "name": "EnableAccum"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.0 14054 {"bits": [1, 1], "name": "AutoAccumEn"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.1 14055 {"bits": [2, 2], "name": "AutoSpmEn"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.2 14056 {"bits": [3, 3], "name": "Globals_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.3 14057 {"bits": [4, 4], "name": "SE0_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.4 14058 {"bits": [5, 5], "name": "SE1_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.5 14059 {"bits": [6, 6], "name": "AutoResetPerfmonDisable"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.6 14060 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_MODE.fields.7 14065 {"bits": [0, 7], "name": "SamplesRequested"}, array in object:register_types.RLC_SPM_ACCUM_SAMPLES_REQUESTED.fields.0 14066 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_SAMPLES_REQUESTED.fields.1 14071 {"bits": [0, 7], "name": "NumbSamplesCompleted"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.0 14072 {"bits": [8, 8], "name": "AccumDone"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.1 14073 {"bits": [9, 9], "name": "SpmDone"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.2 14074 {"bits": [10, 10], "name": "AccumOverflow"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.3 14075 {"bits": [11, 11], "name": "AccumArmed"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.4 14076 {"bits": [12, 12], "name": "SequenceInProgress"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.5 14077 {"bits": [13, 13], "name": "FinalSequenceInProgress"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.6 14078 {"bits": [14, 14], "name": "AllFifosEmpty"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.7 14079 {"bits": [15, 15], "name": "FSMIsIdle"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.8 14080 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.9 14085 {"bits": [0, 15], "name": "Threshold"}, array in object:register_types.RLC_SPM_ACCUM_THRESHOLD.fields.0 14086 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_THRESHOLD.fields.1 14091 {"bits": [0, 6], "name": "DESER_START_SKEW"}, array in object:register_types.RLC_SPM_DESER_START_SKEW.fields.0 14092 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_DESER_START_SKEW.fields.1 14097 {"bits": [0, 6], "name": "data"}, array in object:register_types.RLC_SPM_GLB_SAMPLEDELAY_IND_DATA.fields.0 14098 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLB_SAMPLEDELAY_IND_DATA.fields.1 14103 {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"}, array in object:register_types.RLC_SPM_GLOBALS_MUXSEL_SKEW.fields.0 14104 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLOBALS_MUXSEL_SKEW.fields.1 14109 {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"}, array in object:register_types.RLC_SPM_GLOBALS_SAMPLE_SKEW.fields.0 14110 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLOBALS_SAMPLE_SKEW.fields.1 14115 {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"}, array in object:register_types.RLC_SPM_GLOBAL_MUXSEL_ADDR.fields.0 14116 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLOBAL_MUXSEL_ADDR.fields.1 14121 {"bits": [0, 11], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.0 14122 {"bits": [12, 13], "name": "PERFMON_RING_MODE"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.1 14123 {"bits": [14, 15], "name": "RESERVED"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.2 14124 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"} array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.3 14129 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, array in object:register_types.RLC_SPM_PERFMON_GLB_SEGMENT_SIZE.fields.0 14130 {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_GLB_SEGMENT_SIZE.fields.1 14131 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_GLB_SEGMENT_SIZE.fields.2 14136 {"bits": [0, 15], "name": "RING_BASE_HI"}, array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.0 14137 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.1 14142 {"bits": [0, 7], "name": "SE0_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.0 14143 {"bits": [8, 15], "name": "SE1_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.1 14144 {"bits": [16, 23], "name": "SE2_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.2 14145 {"bits": [24, 31], "name": "SE3_NUM_LINE"} array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.3 14150 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.0 14151 {"bits": [8, 10], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.1 14152 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.2 14153 {"bits": [16, 20], "name": "SE0_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.3 14154 {"bits": [21, 25], "name": "SE1_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.4 14155 {"bits": [26, 30], "name": "SE2_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.5 14156 {"bits": [31, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.6 14161 {"bits": [0, 4], "name": "RESERVED"}, array in object:register_types.RLC_SPM_RING_WRPTR.fields.0 14162 {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"} array in object:register_types.RLC_SPM_RING_WRPTR.fields.1 14167 {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"}, array in object:register_types.RLC_SPM_SEGMENT_THRESHOLD.fields.0 14168 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SEGMENT_THRESHOLD.fields.1 14173 {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"}, array in object:register_types.RLC_SPM_SE_MUXSEL_ADDR.fields.0 14174 {"bits": [9, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SE_MUXSEL_ADDR.fields.1 14179 {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"}, array in object:register_types.RLC_SPM_SE_MUXSEL_SKEW.fields.0 14180 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SE_MUXSEL_SKEW.fields.1 14185 {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"}, array in object:register_types.RLC_SPM_SE_SAMPLE_SKEW.fields.0 14186 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SE_SAMPLE_SKEW.fields.1 14191 {"bits": [0, 0], "name": "PauseSpmSamplingRequest"} array in object:register_types.RLC_SPM_VIRT_CTRL.fields.0 14196 {"bits": [0, 0], "name": "SpmSamplingPaused"} array in object:register_types.RLC_SPM_VIRT_STATUS.fields.0 14201 {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.0 14202 {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.1 14203 {"bits": [4, 5], "name": "TC_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.2 14204 {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.3 14205 {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.4 14206 {"bits": [10, 13], "name": "PERF_COUNTER_CID"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.5 14207 {"bits": [14, 18], "name": "PERF_COUNTER_VMID"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.6 14208 {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.7 14209 {"bits": [25, 25], "name": "PERF_SOFT_RESET"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.8 14210 {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"} array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.9 14215 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, array in object:register_types.SCRATCH_UMSK.fields.0 14216 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} array in object:register_types.SCRATCH_UMSK.fields.1 14221 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.0 14222 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.1 14223 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.2 14224 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.3 14225 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, array in object:register_types.SPI_BARYC_CNTL.fields.4 14226 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, array in object:register_types.SPI_BARYC_CNTL.fields.5 14227 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} array in object:register_types.SPI_BARYC_CNTL.fields.6 14232 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, array in object:register_types.SPI_CONFIG_CNTL.fields.0 14233 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, array in object:register_types.SPI_CONFIG_CNTL.fields.1 14234 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.2 14235 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.3 14236 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, array in object:register_types.SPI_CONFIG_CNTL.fields.4 14237 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}, array in object:register_types.SPI_CONFIG_CNTL.fields.5 14238 {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"}, array in object:register_types.SPI_CONFIG_CNTL.fields.6 14239 {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"}, array in object:register_types.SPI_CONFIG_CNTL.fields.7 14240 {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"} array in object:register_types.SPI_CONFIG_CNTL.fields.8 14245 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.0 14246 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.1 14247 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.2 14248 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.3 14249 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.4 14250 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.5 14251 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} array in object:register_types.SPI_INTERP_CONTROL_0.fields.6 14256 {"bits": [0, 3], "name": "BIN0_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.0 14257 {"bits": [4, 7], "name": "BIN0_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.1 14258 {"bits": [8, 11], "name": "BIN1_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.2 14259 {"bits": [12, 15], "name": "BIN1_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.3 14260 {"bits": [16, 19], "name": "BIN2_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.4 14261 {"bits": [20, 23], "name": "BIN2_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.5 14262 {"bits": [24, 27], "name": "BIN3_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.6 14263 {"bits": [28, 31], "name": "BIN3_MAX"} array in object:register_types.SPI_PERFCOUNTER_BINS.fields.7 14268 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.0 14269 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.1 14270 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.2 14271 {"bits": [13, 16], "name": "CYL_WRAP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.3 14272 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.4 14273 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.5 14274 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.6 14275 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.7 14276 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.8 14277 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.9 14278 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.10 14279 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.11 14284 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.0 14285 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.1 14286 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.2 14287 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.3 14288 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.4 14289 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.5 14290 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.6 14291 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.7 14292 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.8 14297 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.0 14298 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.1 14299 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.2 14300 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.3 14301 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.4 14302 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.5 14303 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.6 14304 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.7 14305 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.8 14306 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.9 14307 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.10 14308 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.11 14309 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.12 14310 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.13 14311 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.14 14312 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} array in object:register_types.SPI_PS_INPUT_ENA.fields.15 14317 {"bits": [0, 5], "name": "NUM_INTERP"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.0 14318 {"bits": [6, 6], "name": "PARAM_GEN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.1 14319 {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.2 14320 {"bits": [8, 8], "name": "LATE_PC_DEALLOC"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.3 14321 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.4 14322 {"bits": [15, 15], "name": "PS_W32_EN"} array in object:register_types.SPI_PS_IN_CONTROL.fields.5 14327 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.0 14328 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.1 14329 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.2 14330 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.3 14331 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.4 14332 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.5 14333 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.6 14334 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_COL_FORMAT.fields.7 14339 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_IDX_FORMAT.fields.0 14344 {"bits": [0, 5], "name": "LIMIT"} array in object:register_types.SPI_SHADER_LATE_ALLOC_VS.fields.0 14349 {"bits": [0, 7], "name": "MEM_BASE"} array in object:register_types.SPI_SHADER_PGM_HI_PS.fields.0 14354 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.0 14355 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.1 14356 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.2 14357 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.3 14358 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.4 14359 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.5 14360 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.6 14361 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.7 14362 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.8 14363 {"bits": [31, 31], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.9 14368 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.0 14369 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.1 14370 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.2 14371 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3 14372 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.4 14373 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.5 14374 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.6 14375 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.7 14376 {"bits": [25, 25], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.8 14377 {"bits": [26, 26], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.9 14378 {"bits": [27, 27], "name": "WGP_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.10 14379 {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.11 14380 {"bits": [31, 31], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.12 14385 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.0 14386 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.1 14387 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.2 14388 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3 14389 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.4 14390 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.5 14391 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.6 14392 {"bits": [24, 24], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.7 14393 {"bits": [25, 25], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.8 14394 {"bits": [26, 26], "name": "WGP_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.9 14395 {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.10 14396 {"bits": [30, 30], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.11 14401 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.0 14402 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.1 14403 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.2 14404 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3 14405 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.4 14406 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.5 14407 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.6 14408 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.7 14409 {"bits": [30, 30], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.8 14414 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.0 14415 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.1 14416 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.2 14417 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3 14418 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.4 14419 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.5 14420 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.6 14421 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.7 14422 {"bits": [25, 25], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.8 14423 {"bits": [26, 26], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.9 14424 {"bits": [29, 29], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.10 14429 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.0 14430 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.1 14431 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.2 14432 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3 14433 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.4 14434 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.5 14435 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.6 14436 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.7 14437 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.8 14438 {"bits": [27, 27], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.9 14439 {"bits": [28, 28], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.10 14440 {"bits": [31, 31], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.11 14445 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.0 14446 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.1 14447 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.2 14448 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.3 14449 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.4 14450 {"bits": [20, 28], "name": "LDS_SIZE"} array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.5 14455 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.0 14456 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.1 14457 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.2 14458 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3 14459 {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.4 14460 {"bits": [18, 18], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.5 14461 {"bits": [19, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.6 14462 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.7 14463 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.8 14468 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.0 14469 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.1 14470 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.2 14471 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.3 14472 {"bits": [16, 17], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.4 14473 {"bits": [18, 18], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.5 14474 {"bits": [19, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.6 14475 {"bits": [27, 27], "name": "SKIP_USGPR0"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.7 14476 {"bits": [28, 28], "name": "USER_SGPR_MSB"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.8 14481 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.0 14482 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.1 14483 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.2 14484 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.3 14485 {"bits": [8, 8], "name": "TG_SIZE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.4 14486 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5 14487 {"bits": [18, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.6 14488 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.7 14489 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.8 14494 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.0 14495 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.1 14496 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.2 14497 {"bits": [7, 15], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.3 14498 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.4 14503 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.0 14504 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.1 14505 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.2 14506 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.3 14507 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.4 14508 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5 14509 {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.6 14510 {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.7 14511 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.8 14512 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.9 14517 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.0 14518 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.1 14519 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.2 14520 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.3 14521 {"bits": [8, 8], "name": "SO_BASE0_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.4 14522 {"bits": [9, 9], "name": "SO_BASE1_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.5 14523 {"bits": [10, 10], "name": "SO_BASE2_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.6 14524 {"bits": [11, 11], "name": "SO_BASE3_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.7 14525 {"bits": [12, 12], "name": "SO_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.8 14526 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9 14527 {"bits": [22, 22], "name": "PC_BASE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.10 14528 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.11 14529 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.12 14530 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.13 14535 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.0 14536 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.1 14537 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.2 14538 {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"} array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.3 14543 {"bits": [0, 5], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.0 14544 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.1 14545 {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.2 14546 {"bits": [16, 31], "name": "CU_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.3 14551 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.0 14552 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.1 14553 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"} array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.2 14558 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC4_GS.fields.0 14559 {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"} array in object:register_types.SPI_SHADER_PGM_RSRC4_GS.fields.1 14564 {"bits": [0, 15], "name": "CU_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC4_PS.fields.0 14569 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.0 14570 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.1 14571 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.2 14572 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.3 14573 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_POS_FORMAT.fields.4 14578 {"bits": [0, 2], "name": "TOTAL_WAVE_COUNT_HIER_SELECT"}, array in object:register_types.SPI_SHADER_PREF_PRI_CNTR_CTRL_PS.fields.0 14579 {"bits": [3, 5], "name": "PER_TYPE_WAVE_COUNT_HIER_SELECT"}, array in object:register_types.SPI_SHADER_PREF_PRI_CNTR_CTRL_PS.fields.1 14580 {"bits": [6, 6], "name": "GROUP_UPDATE_EN"}, array in object:register_types.SPI_SHADER_PREF_PRI_CNTR_CTRL_PS.fields.2 14581 {"bits": [8, 15], "name": "TOTAL_WAVE_COUNT_COEFFICIENT"}, array in object:register_types.SPI_SHADER_PREF_PRI_CNTR_CTRL_PS.fields.3 14582 {"bits": [16, 23], "name": "PER_TYPE_WAVE_COUNT_COEFFICIENT"} array in object:register_types.SPI_SHADER_PREF_PRI_CNTR_CTRL_PS.fields.4 14587 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.0 14588 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.1 14589 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.2 14590 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.3 14591 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.4 14592 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.5 14593 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.6 14594 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"} array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.7 14599 {"bits": [0, 6], "name": "CONTRIBUTION"} array in object:register_types.SPI_SHADER_USER_ACCUM_PS_0.fields.0 14604 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_Z_FORMAT.fields.0 14609 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.0 14610 {"bits": [6, 6], "name": "VS_HALF_PACK"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.1 14611 {"bits": [7, 7], "name": "NO_PC_EXPORT"} array in object:register_types.SPI_VS_OUT_CONFIG.fields.2 14616 {"bits": [0, 0], "name": "TARGET_INST"}, array in object:register_types.SQC_CACHES.fields.0 14617 {"bits": [1, 1], "name": "TARGET_DATA"}, array in object:register_types.SQC_CACHES.fields.1 14618 {"bits": [2, 2], "name": "INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.2 14619 {"bits": [3, 3], "name": "WRITEBACK"}, array in object:register_types.SQC_CACHES.fields.3 14620 {"bits": [4, 4], "name": "VOL"}, array in object:register_types.SQC_CACHES.fields.4 14621 {"bits": [16, 16], "name": "COMPLETE"}, array in object:register_types.SQC_CACHES.fields.5 14622 {"bits": [17, 18], "name": "L2_WB_POLICY"} array in object:register_types.SQC_CACHES.fields.6 14627 {"bits": [0, 0], "name": "DWB"}, array in object:register_types.SQC_WRITEBACK.fields.0 14628 {"bits": [1, 1], "name": "DIRTY"} array in object:register_types.SQC_WRITEBACK.fields.1 14633 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.0 14634 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.1 14635 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.2 14636 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.3 14641 {"bits": [0, 0], "name": "PS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.0 14642 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1 14643 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2 14644 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3 14645 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4 14646 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5 14647 {"bits": [6, 6], "name": "CS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.6 14648 {"bits": [8, 9], "name": "CNTR_RATE"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.7 14649 {"bits": [13, 13], "name": "DISABLE_FLUSH"} array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.8 14654 {"bits": [0, 0], "name": "FORCE_EN"} array in object:register_types.SQ_PERFCOUNTER_CTRL2.fields.0 14659 {"bits": [0, 3], "name": "BASE_HI"}, array in object:register_types.SQ_THREAD_TRACE_BUF0_SIZE.fields.0 14660 {"bits": [8, 29], "name": "SIZE"} array in object:register_types.SQ_THREAD_TRACE_BUF0_SIZE.fields.1 14665 {"bits": [0, 1], "name": "MODE"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.0 14666 {"bits": [2, 2], "name": "ALL_VMID"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.1 14667 {"bits": [3, 3], "name": "CH_PERF_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.2 14668 {"bits": [4, 4], "name": "INTERRUPT_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.3 14669 {"bits": [5, 5], "name": "DOUBLE_BUFFER"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.4 14670 {"bits": [6, 8], "name": "HIWATER"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.5 14671 {"bits": [9, 9], "name": "REG_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.6 14672 {"bits": [10, 10], "name": "SPI_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.7 14673 {"bits": [11, 11], "name": "SQ_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.8 14674 {"bits": [12, 12], "name": "REG_DROP_ON_STALL"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.9 14675 {"bits": [13, 13], "name": "UTIL_TIMER"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.10 14676 {"bits": [14, 15], "name": "WAVESTART_MODE"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.11 14677 {"bits": [16, 17], "name": "RT_FREQ"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.12 14678 {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.13 14679 {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.14 14680 {"bits": [30, 30], "name": "CAPTURE_ALL"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.15 14681 {"bits": [31, 31], "name": "DRAW_EVENT_EN"} array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.16 14686 {"bits": [0, 1], "name": "SIMD_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.0 14687 {"bits": [4, 7], "name": "WGP_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.1 14688 {"bits": [9, 9], "name": "SA_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.2 14689 {"bits": [10, 16], "name": "WTYPE_INCLUDE"} array in object:register_types.SQ_THREAD_TRACE_MASK.fields.3 14694 {"bits": [0, 11], "name": "FINISH_PENDING"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.0 14695 {"bits": [12, 23], "name": "FINISH_DONE"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.1 14696 {"bits": [24, 24], "name": "UTC_ERR"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.2 14697 {"bits": [25, 25], "name": "BUSY"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.3 14698 {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.4 14699 {"bits": [27, 27], "name": "EVENT_CNTR_STALL"} array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.5 14704 {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0 14705 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.1 14706 {"bits": [24, 25], "name": "INST_EXCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.2 14707 {"bits": [31, 31], "name": "REG_DETAIL_ALL"} array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.3 14712 {"bits": [0, 28], "name": "OFFSET"}, array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.0 14713 {"bits": [31, 31], "name": "BUFFER_ID"} array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.1 14718 {"bits": [0, 7], "name": "VGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.0 14719 {"bits": [8, 15], "name": "VGPR_SIZE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.1 14720 {"bits": [16, 23], "name": "SGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.2 14721 {"bits": [24, 27], "name": "SGPR_SIZE"} array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.3 14726 {"bits": [0, 4], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.0 14727 {"bits": [8, 9], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.1 14728 {"bits": [10, 13], "name": "WGP_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.2 14729 {"bits": [16, 16], "name": "SA_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.3 14730 {"bits": [18, 19], "name": "SE_ID"} array in object:register_types.SQ_WAVE_HW_ID1.fields.4 14735 {"bits": [0, 3], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.0 14736 {"bits": [4, 5], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.1 14737 {"bits": [8, 9], "name": "ME_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.2 14738 {"bits": [12, 14], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.3 14739 {"bits": [16, 20], "name": "WG_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.4 14740 {"bits": [24, 27], "name": "VM_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.5 14741 {"bits": [29, 30], "name": "COMPAT_LEVEL"} array in object:register_types.SQ_WAVE_HW_ID2.fields.6 14746 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.0 14747 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.1 14748 {"bits": [6, 7], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.2 14749 {"bits": [8, 11], "name": "CU_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.3 14750 {"bits": [12, 12], "name": "SH_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.4 14751 {"bits": [13, 14], "name": "SE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.5 14752 {"bits": [15, 15], "name": "WAVE_ID_MSB"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.6 14753 {"bits": [16, 19], "name": "TG_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.7 14754 {"bits": [20, 23], "name": "VM_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.8 14755 {"bits": [24, 26], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.9 14756 {"bits": [27, 29], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.10 14757 {"bits": [30, 31], "name": "ME_ID"} array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.11 14762 {"bits": [0, 0], "name": "XNACK_ERROR"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.0 14763 {"bits": [1, 1], "name": "XNACK"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.1 14764 {"bits": [2, 2], "name": "TA_NEED_RESET"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.2 14765 {"bits": [3, 3], "name": "XNACK_OVERRIDE"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.3 14766 {"bits": [4, 9], "name": "XCNT"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.4 14767 {"bits": [11, 16], "name": "QCNT"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.5 14768 {"bits": [18, 23], "name": "RCNT"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.6 14769 {"bits": [24, 24], "name": "WAVE_IDLE"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.7 14770 {"bits": [25, 31], "name": "MISC_CNT"} array in object:register_types.SQ_WAVE_IB_DBG1.fields.8 14775 {"bits": [0, 3], "name": "VM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.0 14776 {"bits": [4, 6], "name": "EXP_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.1 14777 {"bits": [7, 7], "name": "LGKM_CNT_BIT4"}, array in object:register_types.SQ_WAVE_IB_STS.fields.2 14778 {"bits": [8, 11], "name": "LGKM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.3 14779 {"bits": [12, 14], "name": "VALU_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.4 14780 {"bits": [15, 15], "name": "FIRST_REPLAY"}, array in object:register_types.SQ_WAVE_IB_STS.fields.5 14781 {"bits": [16, 21], "name": "RCNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.6 14782 {"bits": [22, 23], "name": "VM_CNT_HI"}, array in object:register_types.SQ_WAVE_IB_STS.fields.7 14783 {"bits": [24, 24], "name": "LGKM_CNT_BIT5"}, array in object:register_types.SQ_WAVE_IB_STS.fields.8 14784 {"bits": [25, 25], "name": "REPLAY_W64H"}, array in object:register_types.SQ_WAVE_IB_STS.fields.9 14785 {"bits": [26, 31], "name": "VS_CNT"} array in object:register_types.SQ_WAVE_IB_STS.fields.10 14790 {"bits": [0, 1], "name": "INST_PREFETCH"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.0 14791 {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.1 14792 {"bits": [8, 9], "name": "MEM_ORDER"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.2 14793 {"bits": [10, 10], "name": "FWD_PROGRESS"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.3 14794 {"bits": [11, 11], "name": "WAVE64"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.4 14795 {"bits": [12, 12], "name": "WAVE64HI"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.5 14796 {"bits": [13, 13], "name": "SUBV_LOOP"} array in object:register_types.SQ_WAVE_IB_STS2.fields.6 14801 {"bits": [0, 8], "name": "LDS_BASE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.0 14802 {"bits": [12, 20], "name": "LDS_SIZE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.1 14803 {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"} array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.2 14808 {"bits": [0, 3], "name": "FP_ROUND"}, array in object:register_types.SQ_WAVE_MODE.fields.0 14809 {"bits": [4, 7], "name": "FP_DENORM"}, array in object:register_types.SQ_WAVE_MODE.fields.1 14810 {"bits": [8, 8], "name": "DX10_CLAMP"}, array in object:register_types.SQ_WAVE_MODE.fields.2 14811 {"bits": [9, 9], "name": "IEEE"}, array in object:register_types.SQ_WAVE_MODE.fields.3 14812 {"bits": [10, 10], "name": "LOD_CLAMPED"}, array in object:register_types.SQ_WAVE_MODE.fields.4 14813 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.5 14814 {"bits": [23, 23], "name": "FP16_OVFL"}, array in object:register_types.SQ_WAVE_MODE.fields.6 14815 {"bits": [27, 27], "name": "DISABLE_PERF"}, array in object:register_types.SQ_WAVE_MODE.fields.7 14816 {"bits": [28, 28], "name": "VSKIP"}, array in object:register_types.SQ_WAVE_MODE.fields.8 14817 {"bits": [29, 31], "name": "CSP"} array in object:register_types.SQ_WAVE_MODE.fields.9 14822 {"bits": [0, 15], "name": "PC_HI"} array in object:register_types.SQ_WAVE_PC_HI.fields.0 14827 {"bits": [0, 0], "name": "POPS_EN"}, array in object:register_types.SQ_WAVE_POPS_PACKER.fields.0 14828 {"bits": [1, 2], "name": "POPS_PACKER_ID"} array in object:register_types.SQ_WAVE_POPS_PACKER.fields.1 14833 {"bits": [0, 1], "name": "DEP_MODE"} array in object:register_types.SQ_WAVE_SCHED_MODE.fields.0 14838 {"bits": [0, 0], "name": "SCC"}, array in object:register_types.SQ_WAVE_STATUS.fields.0 14839 {"bits": [1, 2], "name": "SPI_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.1 14840 {"bits": [3, 4], "name": "USER_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.2 14841 {"bits": [5, 5], "name": "PRIV"}, array in object:register_types.SQ_WAVE_STATUS.fields.3 14842 {"bits": [6, 6], "name": "TRAP_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.4 14843 {"bits": [7, 7], "name": "TTRACE_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.5 14844 {"bits": [8, 8], "name": "EXPORT_RDY"}, array in object:register_types.SQ_WAVE_STATUS.fields.6 14845 {"bits": [9, 9], "name": "EXECZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.7 14846 {"bits": [10, 10], "name": "VCCZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.8 14847 {"bits": [11, 11], "name": "IN_TG"}, array in object:register_types.SQ_WAVE_STATUS.fields.9 14848 {"bits": [12, 12], "name": "IN_BARRIER"}, array in object:register_types.SQ_WAVE_STATUS.fields.10 14849 {"bits": [13, 13], "name": "HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.11 14850 {"bits": [14, 14], "name": "TRAP"}, array in object:register_types.SQ_WAVE_STATUS.fields.12 14851 {"bits": [15, 15], "name": "TTRACE_SIMD_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.13 14852 {"bits": [16, 16], "name": "VALID"}, array in object:register_types.SQ_WAVE_STATUS.fields.14 14853 {"bits": [17, 17], "name": "ECC_ERR"}, array in object:register_types.SQ_WAVE_STATUS.fields.15 14854 {"bits": [18, 18], "name": "SKIP_EXPORT"}, array in object:register_types.SQ_WAVE_STATUS.fields.16 14855 {"bits": [19, 19], "name": "PERF_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.17 14856 {"bits": [23, 23], "name": "FATAL_HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.18 14857 {"bits": [27, 27], "name": "MUST_EXPORT"} array in object:register_types.SQ_WAVE_STATUS.fields.19 14862 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.0 14863 {"bits": [10, 10], "name": "SAVECTX"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.1 14864 {"bits": [11, 11], "name": "ILLEGAL_INST"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.2 14865 {"bits": [12, 14], "name": "EXCP_HI"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.3 14866 {"bits": [15, 15], "name": "BUFFER_OOB"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.4 14867 {"bits": [16, 19], "name": "EXCP_CYCLE"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.5 14868 {"bits": [20, 23], "name": "EXCP_GROUP_MASK"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.6 14869 {"bits": [24, 24], "name": "EXCP_WAVE64HI"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.7 14870 {"bits": [28, 28], "name": "XNACK_ERROR"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.8 14871 {"bits": [29, 31], "name": "DP_RATE"} array in object:register_types.SQ_WAVE_TRAPSTS.fields.9 14876 {"bits": [0, 5], "name": "SRC0"}, array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.0 14877 {"bits": [6, 11], "name": "SRC1"}, array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.1 14878 {"bits": [12, 17], "name": "SRC2"}, array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.2 14879 {"bits": [18, 23], "name": "DST"} array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.3 14884 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.0 14885 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.1 14886 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.2 14887 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.3 14888 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.4 14889 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.5 14890 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.6 14891 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.7 14892 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.8 14893 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.9 14894 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.10 14895 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.11 14896 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.12 14897 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.13 14898 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.14 14899 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.15 14900 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"} array in object:register_types.SX_BLEND_OPT_CONTROL.fields.16 14905 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.0 14906 {"bits": [4, 7], "name": "MRT1_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.1 14907 {"bits": [8, 11], "name": "MRT2_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.2 14908 {"bits": [12, 15], "name": "MRT3_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.3 14909 {"bits": [16, 19], "name": "MRT4_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.4 14910 {"bits": [20, 23], "name": "MRT5_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.5 14911 {"bits": [24, 27], "name": "MRT6_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.6 14912 {"bits": [28, 31], "name": "MRT7_EPSILON"} array in object:register_types.SX_BLEND_OPT_EPSILON.fields.7 14917 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.0 14918 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.1 14919 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.2 14920 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.3 14921 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.4 14922 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} array in object:register_types.SX_MRT0_BLEND_OPT.fields.5 14927 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"}, array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.0 14928 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"}, array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.1 14929 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.2 14934 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"}, array in object:register_types.SX_PERFCOUNTER0_SELECT1.fields.0 14935 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"} array in object:register_types.SX_PERFCOUNTER0_SELECT1.fields.1 14940 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.0 14941 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.1 14942 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.2 14943 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.3 14944 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.4 14945 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.5 14946 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.6 14947 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} array in object:register_types.SX_PS_DOWNCONVERT.fields.7 14952 {"bits": [0, 7], "name": "ADDRESS"} array in object:register_types.TA_BC_BASE_ADDR_HI.fields.0 14957 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.0 14958 {"bits": [10, 17], "name": "PERF_SEL1"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.1 14959 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.2 14960 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.3 14961 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.4 14966 {"bits": [0, 7], "name": "PERF_SEL2"}, array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.0 14967 {"bits": [10, 17], "name": "PERF_SEL3"}, array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.1 14968 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.2 14969 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.3 14974 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.TA_PERFCOUNTER1_SELECT.fields.0 14975 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TA_PERFCOUNTER1_SELECT.fields.1 14976 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TA_PERFCOUNTER1_SELECT.fields.2 14981 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.TCP_PERFCOUNTER2_SELECT.fields.0 14982 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TCP_PERFCOUNTER2_SELECT.fields.1 14983 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TCP_PERFCOUNTER2_SELECT.fields.2 14988 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.UTCL1_PERFCOUNTER0_SELECT.fields.0 14989 {"bits": [28, 31], "name": "COUNTER_MODE"} array in object:register_types.UTCL1_PERFCOUNTER0_SELECT.fields.1 14994 {"bits": [0, 15], "name": "BASE_ADDR"} array in object:register_types.VGT_DMA_BASE_HI.fields.0 14999 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.0 15000 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.1 15001 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.2 15002 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.3 15003 {"bits": [8, 8], "name": "ATC"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.4 15004 {"bits": [9, 9], "name": "NOT_EOP"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.5 15005 {"bits": [10, 10], "name": "REQ_PATH"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.6 15006 {"bits": [11, 13], "name": "MTYPE"} array in object:register_types.VGT_DMA_INDEX_TYPE.fields.7 15011 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.0 15012 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.1 15013 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.2 15014 {"bits": [5, 5], "name": "NOT_EOP"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.3 15015 {"bits": [6, 6], "name": "USE_OPAQUE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.4 15016 {"bits": [7, 7], "name": "UNROLLED_INST"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.5 15017 {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.6 15018 {"bits": [29, 31], "name": "REG_RT_INDEX"} array in object:register_types.VGT_DRAW_INITIATOR.fields.7 15023 {"bits": [0, 0], "name": "OBJPRIM_ID_EN"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.0 15024 {"bits": [1, 1], "name": "EN_REG_RT_INDEX"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.1 15025 {"bits": [2, 2], "name": "OBJECT_ID_INST_EN"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.2 15026 {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.3 15027 {"bits": [4, 4], "name": "EN_DRAW_VP"} array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.4 15032 {"bits": [0, 14], "name": "ITEMSIZE"} array in object:register_types.VGT_ESGS_RING_ITEMSIZE.fields.0 15037 {"bits": [0, 10], "name": "ES_PER_GS"} array in object:register_types.VGT_ES_PER_GS.fields.0 15042 {"bits": [0, 27], "name": "ADDRESS_LOW"} array in object:register_types.VGT_EVENT_ADDRESS_REG.fields.0 15047 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.0 15048 {"bits": [10, 26], "name": "ADDRESS_HI"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.1 15049 {"bits": [27, 27], "name": "EXTENDED_EVENT"} array in object:register_types.VGT_EVENT_INITIATOR.fields.2 15054 {"bits": [0, 3], "name": "DECR"} array in object:register_types.VGT_GROUP_DECR.fields.0 15059 {"bits": [0, 3], "name": "FIRST_DECR"} array in object:register_types.VGT_GROUP_FIRST_DECR.fields.0 15064 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0 15065 {"bits": [14, 14], "name": "RETAIN_ORDER"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.1 15066 {"bits": [15, 15], "name": "RETAIN_QUADS"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.2 15067 {"bits": [16, 18], "name": "PRIM_ORDER"} array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.3 15072 {"bits": [0, 0], "name": "COMP_X_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.0 15073 {"bits": [1, 1], "name": "COMP_Y_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.1 15074 {"bits": [2, 2], "name": "COMP_Z_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.2 15075 {"bits": [3, 3], "name": "COMP_W_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.3 15076 {"bits": [8, 15], "name": "STRIDE"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.4 15077 {"bits": [16, 23], "name": "SHIFT"} array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.5 15082 {"bits": [0, 3], "name": "X_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.0 15083 {"bits": [4, 7], "name": "X_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.1 15084 {"bits": [8, 11], "name": "Y_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.2 15085 {"bits": [12, 15], "name": "Y_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.3 15086 {"bits": [16, 19], "name": "Z_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.4 15087 {"bits": [20, 23], "name": "Z_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.5 15088 {"bits": [24, 27], "name": "W_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.6 15089 {"bits": [28, 31], "name": "W_OFFSET"} array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.7 15094 {"bits": [0, 14], "name": "OFFSET"} array in object:register_types.VGT_GSVS_RING_OFFSET_1.fields.0 15099 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.0 15100 {"bits": [2, 8], "name": "CNT"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.1 15101 {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"} array in object:register_types.VGT_GS_INSTANCE_CNT.fields.2 15106 {"bits": [0, 10], "name": "MAX_VERT_OUT"} array in object:register_types.VGT_GS_MAX_VERT_OUT.fields.0 15111 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, array in object:register_types.VGT_GS_MODE.fields.0 15112 {"bits": [3, 3], "name": "RESERVED_0"}, array in object:register_types.VGT_GS_MODE.fields.1 15113 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, array in object:register_types.VGT_GS_MODE.fields.2 15114 {"bits": [6, 10], "name": "RESERVED_1"}, array in object:register_types.VGT_GS_MODE.fields.3 15115 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, array in object:register_types.VGT_GS_MODE.fields.4 15116 {"bits": [12, 12], "name": "RESERVED_2"}, array in object:register_types.VGT_GS_MODE.fields.5 15117 {"bits": [13, 13], "name": "ES_PASSTHRU"}, array in object:register_types.VGT_GS_MODE.fields.6 15118 {"bits": [14, 14], "name": "COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.7 15119 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.8 15120 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, array in object:register_types.VGT_GS_MODE.fields.9 15121 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, array in object:register_types.VGT_GS_MODE.fields.10 15122 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, array in object:register_types.VGT_GS_MODE.fields.11 15123 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.12 15124 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.13 15125 {"bits": [21, 22], "name": "ONCHIP"} array in object:register_types.VGT_GS_MODE.fields.14 15130 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.0 15131 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.1 15132 {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"} array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.2 15137 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0 15138 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1 15139 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2 15140 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3 15141 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.4 15146 {"bits": [0, 10], "name": "GS_PER_ES"} array in object:register_types.VGT_GS_PER_ES.fields.0 15151 {"bits": [0, 3], "name": "GS_PER_VS"} array in object:register_types.VGT_GS_PER_VS.fields.0 15156 {"bits": [0, 1], "name": "TESS_MODE"} array in object:register_types.VGT_HOS_CNTL.fields.0 15161 {"bits": [0, 7], "name": "REUSE_DEPTH"} array in object:register_types.VGT_HOS_REUSE_DEPTH.fields.0 15166 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"}, array in object:register_types.VGT_HS_OFFCHIP_PARAM_UMD.fields.0 15167 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP array in object:register_types.VGT_HS_OFFCHIP_PARAM_UMD.fields.1 15172 {"bits": [0, 7], "name": "NUM_PATCHES"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.0 15173 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.1 15174 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} array in object:register_types.VGT_LS_HS_CONFIG.fields.2 15179 {"bits": [0, 0], "name": "RESET_EN"}, array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.0 15180 {"bits": [1, 1], "name": "MATCH_ALL_BITS"} array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.1 15185 {"bits": [0, 2], "name": "PATH_SELECT"} array in object:register_types.VGT_OUTPUT_PATH_CNTL.fields.0 15190 {"bits": [0, 6], "name": "DEALLOC_DIST"} array in object:register_types.VGT_OUT_DEALLOC_CNTL.fields.0 15195 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.0 15196 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.1 15197 {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"} array in object:register_types.VGT_PRIMITIVEID_EN.fields.2 15202 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} array in object:register_types.VGT_PRIMITIVE_TYPE.fields.0 15207 {"bits": [0, 0], "name": "REUSE_OFF"} array in object:register_types.VGT_REUSE_OFF.fields.0 15212 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.0 15213 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.1 15214 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.2 15215 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.3 15216 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.4 15217 {"bits": [8, 8], "name": "DYNAMIC_HS"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.5 15218 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.6 15219 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.7 15220 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.8 15221 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.9 15222 {"bits": [13, 13], "name": "PRIMGEN_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.10 15223 {"bits": [14, 14], "name": "ORDERED_ID_MODE"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.11 15224 {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.12 15225 {"bits": [19, 20], "name": "GS_FAST_LAUNCH"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.13 15226 {"bits": [21, 21], "name": "HS_W32_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.14 15227 {"bits": [22, 22], "name": "GS_W32_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.15 15228 {"bits": [23, 23], "name": "VS_W32_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.16 15229 {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.17 15230 {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"} array in object:register_types.VGT_SHADER_STAGES_EN.fields.18 15235 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.0 15236 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.1 15237 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.2 15238 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.3 15243 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.0 15244 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.1 15245 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.2 15246 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.3 15247 {"bits": [4, 6], "name": "RAST_STREAM"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.4 15248 {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.5 15249 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.6 15250 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} array in object:register_types.VGT_STRMOUT_CONFIG.fields.7 15255 {"bits": [0, 8], "name": "VERTEX_STRIDE"} array in object:register_types.VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE.fields.0 15260 {"bits": [0, 9], "name": "STRIDE"} array in object:register_types.VGT_STRMOUT_VTX_STRIDE_0.fields.0 15265 {"bits": [0, 7], "name": "ACCUM_ISOLINE"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.0 15266 {"bits": [8, 15], "name": "ACCUM_TRI"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.1 15267 {"bits": [16, 23], "name": "ACCUM_QUAD"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.2 15268 {"bits": [24, 28], "name": "DONUT_SPLIT"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.3 15269 {"bits": [29, 31], "name": "TRAP_SPLIT"} array in object:register_types.VGT_TESS_DISTRIBUTION.fields.4 15274 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, array in object:register_types.VGT_TF_PARAM.fields.0 15275 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, array in object:register_types.VGT_TF_PARAM.fields.1 15276 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, array in object:register_types.VGT_TF_PARAM.fields.2 15277 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, array in object:register_types.VGT_TF_PARAM.fields.3 15278 {"bits": [9, 9], "name": "DEPRECATED"}, array in object:register_types.VGT_TF_PARAM.fields.4 15279 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, array in object:register_types.VGT_TF_PARAM.fields.5 15280 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, array in object:register_types.VGT_TF_PARAM.fields.6 15281 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_TF_PARAM.fields.7 15282 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, array in object:register_types.VGT_TF_PARAM.fields.8 15283 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"}, array in object:register_types.VGT_TF_PARAM.fields.9 15284 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"}, array in object:register_types.VGT_TF_PARAM.fields.10 15285 {"bits": [23, 25], "name": "MTYPE"} array in object:register_types.VGT_TF_PARAM.fields.11 15290 {"bits": [0, 15], "name": "SIZE"} array in object:register_types.VGT_TF_RING_SIZE_UMD.fields.0 15295 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} array in object:register_types.VGT_VERTEX_REUSE_BLOCK_CNTL.fields.0 15300 {"bits": [0, 0], "name": "VTX_CNT_EN"} array in object:register_types.VGT_VTX_CNT_EN.fields.0 [all...]
H A D	gfx103.json	11474 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.0 11475 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.1 11476 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.2 11477 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.3 11478 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.4 11479 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.5 11480 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.6 11481 {"bits": [30, 30], "name": "ENABLE"}, array in object:register_types.CB_BLEND0_CONTROL.fields.7 11482 {"bits": [31, 31], "name": "DISABLE_ROP3"} array in object:register_types.CB_BLEND0_CONTROL.fields.8 11487 {"bits" array in object:register_types.CB_COLOR0_ATTRIB.fields.0 11488 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.1 11489 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.2 11490 {"bits": [12, 14], "name": "NUM_SAMPLES"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.3 11491 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.4 11492 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.5 11493 {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.6 11494 {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"} array in object:register_types.CB_COLOR0_ATTRIB.fields.7 11499 {"bits": [0, 13], "name": "MIP0_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB2.fields.0 11500 {"bits": [14, 27], "name": "MIP0_WIDTH"}, array in object:register_types.CB_COLOR0_ATTRIB2.fields.1 11501 {"bits": [28, 31], "name": "MAX_MIP"} array in object:register_types.CB_COLOR0_ATTRIB2.fields.2 11506 {"bits": [0, 12], "name": "MIP0_DEPTH"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.0 11507 {"bits": [13, 13], "name": "META_LINEAR"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.1 11508 {"bits": [14, 18], "name": "COLOR_SW_MODE"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.2 11509 {"bits": [19, 23], "name": "FMASK_SW_MODE"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.3 11510 {"bits": [24, 25], "name": "RESOURCE_TYPE"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.4 11511 {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.5 11512 {"bits": [27, 29], "name": "RESOURCE_LEVEL"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.6 11513 {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"}, array in object:register_types.CB_COLOR0_ATTRIB3.fields.7 11514 {"bits": [31, 31], "name": "VRS_RATE_HINT_ENABLE"} array in object:register_types.CB_COLOR0_ATTRIB3.fields.8 11519 {"bits": [0, 7], "name": "BASE_256B"} array in object:register_types.CB_COLOR0_BASE_EXT.fields.0 11524 {"bits": [0, 13], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_CMASK_SLICE.fields.0 11529 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.0 11530 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.1 11531 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": " array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2 11532 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MI array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3 11533 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.4 11534 {"bits": [7, 8], "name": "COLOR_TRANSFORM"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.5 11535 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.6 11536 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.7 11537 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.8 11538 {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.9 11539 {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.10 11540 {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.11 11541 {"bits": [21, 21], "name": "SKIP_LOW_COMP_RATIO"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.12 11542 {"bits": [22, 22], "name": "DCC_COMPRESS_DISABLE"} array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.13 11547 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, array in object:register_types.CB_COLOR0_INFO.fields.0 11548 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, array in object:register_types.CB_COLOR0_INFO.fields.1 11549 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, array in object:register_types.CB_COLOR0_INFO.fields.2 11550 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.3 11551 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, array in object:register_types.CB_COLOR0_INFO.fields.4 11552 {"bits": [13, 13], "name": "FAST_CLEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.5 11553 {"bits": [14, 14], "name": "COMPRESSION"}, array in object:register_types.CB_COLOR0_INFO.fields.6 11554 {"bits": [15, 15], "name": "BLEND_CLAMP"}, array in object:register_types.CB_COLOR0_INFO.fields.7 11555 {"bits": [16, 16], "name": "BLEND_BYPASS"}, array in object:register_types.CB_COLOR0_INFO.fields.8 11556 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, array in object:register_types.CB_COLOR0_INFO.fields.9 11557 {"bits": [18, 18], "name": "ROUND_MODE"}, array in object:register_types.CB_COLOR0_INFO.fields.10 11558 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.11 11559 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, array in object:register_types.CB_COLOR0_INFO.fields.12 11560 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, array in object:register_types.CB_COLOR0_INFO.fields.13 11561 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.14 11562 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"}, array in object:register_types.CB_COLOR0_INFO.fields.15 11563 {"bits": [28, 28], "name": "DCC_ENABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.16 11564 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.17 11565 {"bits": [31, 31], "name": "NBC_TILING"} array in object:register_types.CB_COLOR0_INFO.fields.18 11570 {"bits": [0, 10], "name": "TILE_MAX"}, array in object:register_types.CB_COLOR0_PITCH.fields.0 11571 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} array in object:register_types.CB_COLOR0_PITCH.fields.1 11576 {"bits": [0, 21], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_SLICE.fields.0 11581 {"bits": [0, 12], "name": "SLICE_START"}, array in object:register_types.CB_COLOR0_VIEW.fields.0 11582 {"bits": [13, 25], "name": "SLICE_MAX"}, array in object:register_types.CB_COLOR0_VIEW.fields.1 11583 {"bits": [26, 29], "name": "MIP_LEVEL"} array in object:register_types.CB_COLOR0_VIEW.fields.2 11588 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"}, array in object:register_types.CB_COLOR_CONTROL.fields.0 11589 {"bits": [1, 1], "name": "ENABLE_1FRAG_PS_INVOKE"}, array in object:register_types.CB_COLOR_CONTROL.fields.1 11590 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, array in object:register_types.CB_COLOR_CONTROL.fields.2 11591 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, array in object:register_types.CB_COLOR_CONTROL.fields.3 11592 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} array in object:register_types.CB_COLOR_CONTROL.fields.4 11597 {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"}, array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.0 11598 {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"}, array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.1 11599 {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"}, array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.2 11600 {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"} array in object:register_types.CB_COVERAGE_OUT_CONTROL.fields.3 11605 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_DCC_CONTROL.fields.0 11606 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}, array in object:register_types.CB_DCC_CONTROL.fields.1 11607 {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"}, array in object:register_types.CB_DCC_CONTROL.fields.2 11608 {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"}, array in object:register_types.CB_DCC_CONTROL.fields.3 11609 {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"}, array in object:register_types.CB_DCC_CONTROL.fields.4 11610 {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"}, array in object:register_types.CB_DCC_CONTROL.fields.5 11611 {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"}, array in object:register_types.CB_DCC_CONTROL.fields.6 11612 {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"} array in object:register_types.CB_DCC_CONTROL.fields.7 11617 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.0 11618 {"bits": [10, 18], "name": "PERF_SEL1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.1 11619 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.2 11620 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.3 11621 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.4 11626 {"bits": [0, 8], "name": "PERF_SEL2"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.0 11627 {"bits": [10, 18], "name": "PERF_SEL3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.1 11628 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.2 11629 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.3 11634 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.0 11635 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.1 11640 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.0 11641 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.1 11642 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.2 11643 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.3 11644 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.4 11645 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.5 11646 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.6 11647 {"bits": [13, 15], "name": "MRT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.7 11648 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.8 11649 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.9 11650 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.10 11651 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"} array in object:register_types.CB_PERFCOUNTER_FILTER.fields.11 11656 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.0 11657 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.1 11658 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.2 11659 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.3 11660 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.4 11661 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.5 11662 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.6 11663 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.7 11664 {"bits": [24, 24], "name": "CMASK_L3_BYPASS"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.8 11665 {"bits": [25, 25], "name": "FMASK_L3_BYPASS"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.9 11666 {"bits": [26, 26], "name": "DCC_L3_BYPASS"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.10 11667 {"bits": [27, 27], "name": "COLOR_L3_BYPASS"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.11 11668 {"bits": [30, 30], "name": "FMASK_BIG_PAGE"}, array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.12 11669 {"bits": [31, 31], "name": "COLOR_BIG_PAGE"} array in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.13 11674 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.0 11675 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.1 11676 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.2 11677 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.3 11678 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.4 11679 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.5 11680 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.6 11681 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} array in object:register_types.CB_SHADER_MASK.fields.7 11686 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.0 11687 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.1 11688 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.2 11689 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.3 11690 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.4 11691 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.5 11692 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.6 11693 {"bits": [28, 31], "name": "TARGET7_ENABLE"} array in object:register_types.CB_TARGET_MASK.fields.7 11698 {"bits": [0, 7], "name": "DEST_BASE_HI_256B"} array in object:register_types.COHER_DEST_BASE_HI_0.fields.0 11703 {"bits": [0, 10], "name": "INDEX"} array in object:register_types.COMPUTE_DDID_INDEX.fields.0 11708 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.0 11709 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.1 11710 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.2 11711 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.3 11712 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.4 11713 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.5 11714 {"bits": [6, 6], "name": "ORDER_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.6 11715 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.7 11716 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.8 11717 {"bits": [12, 12], "name": "RESERVED"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.9 11718 {"bits": [13, 13], "name": "TUNNEL_ENABLE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.10 11719 {"bits": [14, 14], "name": "RESTORE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.11 11720 {"bits": [15, 15], "name": "CS_W32_EN"} array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.12 11725 {"bits": [0, 9], "name": "OFF_DELAY"}, array in object:register_types.COMPUTE_DISPATCH_TUNNEL.fields.0 11726 {"bits": [10, 10], "name": "IMMEDIATE"} array in object:register_types.COMPUTE_DISPATCH_TUNNEL.fields.1 11731 {"bits": [0, 1], "name": "SEND_SEID"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.0 11732 {"bits": [2, 2], "name": "RESERVED2"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.1 11733 {"bits": [3, 3], "name": "RESERVED3"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.2 11734 {"bits": [4, 4], "name": "RESERVED4"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.3 11735 {"bits": [5, 16], "name": "WAVE_ID_BASE"} array in object:register_types.COMPUTE_MISC_RESERVED.fields.4 11740 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, array in object:register_types.COMPUTE_NUM_THREAD_X.fields.0 11741 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} array in object:register_types.COMPUTE_NUM_THREAD_X.fields.1 11746 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"} array in object:register_types.COMPUTE_PERFCOUNT_ENABLE.fields.0 11751 {"bits": [0, 7], "name": "DATA"} array in object:register_types.COMPUTE_PGM_HI.fields.0 11756 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.0 11757 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.1 11758 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.2 11759 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.3 11760 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.4 11761 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.5 11762 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.6 11763 {"bits": [24, 24], "name": "BULKY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.7 11764 {"bits": [26, 26], "name": "FP16_OVFL"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.8 11765 {"bits": [29, 29], "name": "WGP_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.9 11766 {"bits": [30, 30], "name": "MEM_ORDERED"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.10 11767 {"bits": [31, 31], "name": "FWD_PROGRESS"} array in object:register_types.COMPUTE_PGM_RSRC1.fields.11 11772 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.0 11773 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.1 11774 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.2 11775 {"bits": [7, 7], "name": "TGID_X_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.3 11776 {"bits": [8, 8], "name": "TGID_Y_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.4 11777 {"bits": [9, 9], "name": "TGID_Z_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.5 11778 {"bits": [10, 10], "name": "TG_SIZE_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.6 11779 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.7 11780 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.8 11781 {"bits": [15, 23], "name": "LDS_SIZE"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.9 11782 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.COMPUTE_PGM_RSRC2.fields.10 11787 {"bits": [0, 3], "name": "SHARED_VGPR_CNT"} array in object:register_types.COMPUTE_PGM_RSRC3.fields.0 11792 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"} array in object:register_types.COMPUTE_PIPELINESTAT_ENABLE.fields.0 11797 {"bits": [0, 29], "name": "PAYLOAD"}, array in object:register_types.COMPUTE_RELAUNCH.fields.0 11798 {"bits": [30, 30], "name": "IS_EVENT"}, array in object:register_types.COMPUTE_RELAUNCH.fields.1 11799 {"bits": [31, 31], "name": "IS_STATE"} array in object:register_types.COMPUTE_RELAUNCH.fields.2 11804 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.0 11805 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.1 11806 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.2 11807 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.3 11808 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.4 11809 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.5 11810 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.6 11811 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}, array in object:register_types.COMPUTE_REQ_CTRL.fields.7 11812 {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"} array in object:register_types.COMPUTE_REQ_CTRL.fields.8 11817 {"bits": [0, 9], "name": "WAVES_PER_SH"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.0 11818 {"bits": [12, 15], "name": "TG_PER_CU"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.1 11819 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.2 11820 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.3 11821 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.4 11822 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.5 11827 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"} array in object:register_types.COMPUTE_THREAD_TRACE_ENABLE.fields.0 11832 {"bits": [0, 11], "name": "WAVES"}, array in object:register_types.COMPUTE_TMPRING_SIZE.fields.0 11833 {"bits": [12, 24], "name": "WAVESIZE"} array in object:register_types.COMPUTE_TMPRING_SIZE.fields.1 11838 {"bits": [0, 3], "name": "DATA"} array in object:register_types.COMPUTE_VMID.fields.0 11843 {"bits": [0, 15], "name": "ADDR"} array in object:register_types.COMPUTE_WAVE_RESTORE_ADDR_HI.fields.0 11848 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.0 11849 {"bits": [30, 30], "name": "CLEAR"}, array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.1 11850 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.2 11855 {"bits": [0, 2], "name": "INDEX"}, array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.0 11856 {"bits": [30, 30], "name": "ALWAYS"}, array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.1 11857 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.2 11862 {"bits": [0, 4], "name": "INDEX"}, array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.0 11863 {"bits": [30, 30], "name": "CLEAR"}, array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.1 11864 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.2 11869 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.0 11870 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.1 11871 {"bits": [24, 27], "name": "CNTR_MODE3"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.2 11872 {"bits": [28, 31], "name": "CNTR_MODE2"} array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.3 11877 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.0 11878 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.1 11879 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.2 11880 {"bits": [24, 27], "name": "CNTR_MODE1"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.3 11881 {"bits": [28, 31], "name": "CNTR_MODE0"} array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.4 11886 {"bits": [0, 4], "name": "INDEX"}, array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.0 11887 {"bits": [30, 30], "name": "ALWAYS"}, array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.1 11888 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.2 11893 {"bits": [0, 15], "name": "MEM_ADDR_HI"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.0 11894 {"bits": [16, 16], "name": "CS_PS_SEL"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.1 11895 {"bits": [25, 26], "name": "CACHE_POLICY"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.2 11896 {"bits": [29, 31], "name": "COMMAND"} array in object:register_types.CP_APPEND_ADDR_HI.fields.3 11901 {"bits": [2, 31], "name": "MEM_ADDR_LO"} array in object:register_types.CP_APPEND_ADDR_LO.fields.0 11906 {"bits": [0, 15], "name": "IB1_BASE_HI"} array in object:register_types.CP_CE_IB1_BASE_HI.fields.0 11911 {"bits": [2, 31], "name": "IB1_BASE_LO"} array in object:register_types.CP_CE_IB1_BASE_LO.fields.0 11916 {"bits": [0, 19], "name": "IB1_BUFSZ"} array in object:register_types.CP_CE_IB1_BUFSZ.fields.0 11921 {"bits": [0, 19], "name": "IB1_CMD_REQSZ"} array in object:register_types.CP_CE_IB1_CMD_BUFSZ.fields.0 11926 {"bits": [0, 19], "name": "IB1_OFFSET"} array in object:register_types.CP_CE_IB1_OFFSET.fields.0 11931 {"bits": [0, 15], "name": "IB2_BASE_HI"} array in object:register_types.CP_CE_IB2_BASE_HI.fields.0 11936 {"bits": [2, 31], "name": "IB2_BASE_LO"} array in object:register_types.CP_CE_IB2_BASE_LO.fields.0 11941 {"bits": [0, 19], "name": "IB2_BUFSZ"} array in object:register_types.CP_CE_IB2_BUFSZ.fields.0 11946 {"bits": [0, 19], "name": "IB2_CMD_REQSZ"} array in object:register_types.CP_CE_IB2_CMD_BUFSZ.fields.0 11951 {"bits": [0, 15], "name": "INIT_BASE_HI"} array in object:register_types.CP_CE_INIT_BASE_HI.fields.0 11956 {"bits": [5, 31], "name": "INIT_BASE_LO"} array in object:register_types.CP_CE_INIT_BASE_LO.fields.0 11961 {"bits": [0, 11], "name": "INIT_BUFSZ"} array in object:register_types.CP_CE_INIT_BUFSZ.fields.0 11966 {"bits": [0, 11], "name": "INIT_CMD_REQSZ"} array in object:register_types.CP_CE_INIT_CMD_BUFSZ.fields.0 11971 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"} array in object:register_types.CP_COHER_BASE_HI.fields.0 11976 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.0 11977 {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.1 11978 {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.2 11979 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.3 11980 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.4 11981 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.5 11982 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.6 11983 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.7 11984 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.8 11985 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.9 11986 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.10 11987 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.11 11988 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"} array in object:register_types.CP_COHER_CNTL.fields.12 11993 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"} array in object:register_types.CP_COHER_SIZE_HI.fields.0 11998 {"bits": [0, 5], "name": "START_DELAY_COUNT"} array in object:register_types.CP_COHER_START_DELAY.fields.0 12003 {"bits": [24, 25], "name": "MEID"}, array in object:register_types.CP_COHER_STATUS.fields.0 12004 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_COHER_STATUS.fields.1 12009 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.0 12010 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.1 12011 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.2 12012 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.3 12013 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.4 12014 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.5 12015 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.6 12016 {"bits": [7, 7], "name": "MEC1_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.7 12017 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.8 12018 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.9 12019 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.10 12020 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.11 12021 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.12 12022 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.13 12023 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.14 12024 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.15 12025 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.16 12026 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.17 12027 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.18 12028 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.19 12029 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.20 12030 {"bits": [23, 23], "name": "MEC2_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.21 12031 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.22 12032 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.23 12033 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.24 12034 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.25 12035 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.26 12036 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"} array in object:register_types.CP_CPC_BUSY_STAT.fields.27 12041 {"bits": [0, 0], "name": "MES_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.0 12042 {"bits": [2, 2], "name": "MES_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.1 12043 {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.2 12044 {"bits": [7, 7], "name": "MES_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.3 12045 {"bits": [8, 8], "name": "MES_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.4 12046 {"bits": [10, 10], "name": "MES_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.5 12047 {"bits": [11, 11], "name": "MES_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.6 12048 {"bits": [12, 12], "name": "MES_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT2.fields.7 12049 {"bits": [13, 13], "name": "MES_PIPE3_BUSY"} array in object:register_types.CP_CPC_BUSY_STAT2.fields.8 12054 {"bits": [0, 5], "name": "FREE_COUNT"} array in object:register_types.CP_CPC_GRBM_FREE_COUNT.fields.0 12059 {"bits": [0, 3], "name": "COUNT"} array in object:register_types.CP_CPC_HALT_HYST_COUNT.fields.0 12064 {"bits": [0, 15], "name": "PRIV_VIOLATION_ADDR"} array in object:register_types.CP_CPC_PRIV_VIOLATION_ADDR.fields.0 12069 {"bits": [0, 8], "name": "SCRATCH_INDEX"}, array in object:register_types.CP_CPC_SCRATCH_INDEX.fields.0 12070 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"} array in object:register_types.CP_CPC_SCRATCH_INDEX.fields.1 12075 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.0 12076 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.1 12077 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.2 12078 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.3 12079 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.4 12080 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.5 12081 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.6 12082 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.7 12083 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.8 12084 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.9 12085 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.10 12086 {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.11 12087 {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.12 12088 {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.13 12089 {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"} array in object:register_types.CP_CPC_STALLED_STAT1.fields.14 12094 {"bits": [0, 0], "name": "MEC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.0 12095 {"bits": [1, 1], "name": "MEC2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.1 12096 {"bits": [2, 2], "name": "DC0_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.2 12097 {"bits": [3, 3], "name": "DC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.3 12098 {"bits": [4, 4], "name": "RCIU1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.4 12099 {"bits": [5, 5], "name": "RCIU2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.5 12100 {"bits": [6, 6], "name": "ROQ1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.6 12101 {"bits": [7, 7], "name": "ROQ2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.7 12102 {"bits": [10, 10], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.8 12103 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.9 12104 {"bits": [12, 12], "name": "QU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.10 12105 {"bits": [13, 13], "name": "UTCL2IU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.11 12106 {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.12 12107 {"bits": [15, 15], "name": "GCRIU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.13 12108 {"bits": [16, 16], "name": "MES_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.14 12109 {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.15 12110 {"bits": [18, 18], "name": "RCIU3_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.16 12111 {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.17 12112 {"bits": [29, 29], "name": "CPG_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.18 12113 {"bits": [30, 30], "name": "CPF_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.19 12114 {"bits": [31, 31], "name": "CPC_BUSY"} array in object:register_types.CP_CPC_STATUS.fields.20 12119 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.0 12120 {"bits": [1, 1], "name": "CSF_RING_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.1 12121 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.2 12122 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.3 12123 {"bits": [4, 4], "name": "CSF_STATE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.4 12124 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.5 12125 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.6 12126 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.7 12127 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.8 12128 {"bits": [9, 9], "name": "CSF_DATA_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.9 12129 {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.10 12130 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.11 12131 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.12 12132 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.13 12133 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.14 12134 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.15 12135 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.16 12136 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.17 12137 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.18 12138 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.19 12139 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.20 12140 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.21 12141 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.22 12142 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.23 12143 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.24 12144 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.25 12145 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.26 12146 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.27 12147 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.28 12148 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.29 12149 {"bits": [30, 30], "name": "HQD_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.30 12150 {"bits": [31, 31], "name": "HQD_IB_BUSY"} array in object:register_types.CP_CPF_BUSY_STAT.fields.31 12155 {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.0 12156 {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.1 12157 {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.2 12158 {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.3 12159 {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.4 12160 {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.5 12161 {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.6 12162 {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT2.fields.7 12163 {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"} array in object:register_types.CP_CPF_BUSY_STAT2.fields.8 12168 {"bits": [0, 2], "name": "FREE_COUNT"} array in object:register_types.CP_CPF_GRBM_FREE_COUNT.fields.0 12173 {"bits": [0, 0], "name": "RING_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.0 12174 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.1 12175 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.2 12176 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.3 12177 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.4 12178 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.5 12179 {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.6 12180 {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.7 12181 {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.8 12182 {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.9 12183 {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.10 12184 {"bits": [12, 12], "name": "DATA_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.11 12185 {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"} array in object:register_types.CP_CPF_STALLED_STAT1.fields.12 12190 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.0 12191 {"bits": [1, 1], "name": "CSF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.1 12192 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.2 12193 {"bits": [5, 5], "name": "ROQ_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.3 12194 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.4 12195 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.5 12196 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.6 12197 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.7 12198 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.8 12199 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.9 12200 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.10 12201 {"bits": [13, 13], "name": "INTERRUPT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.11 12202 {"bits": [14, 14], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.12 12203 {"bits": [15, 15], "name": "HQD_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.13 12204 {"bits": [16, 16], "name": "PRT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.14 12205 {"bits": [17, 17], "name": "UTCL2IU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.15 12206 {"bits": [18, 18], "name": "RCIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.16 12207 {"bits": [19, 19], "name": "RCIU_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.17 12208 {"bits": [20, 20], "name": "RCIU_CMP_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.18 12209 {"bits": [21, 21], "name": "ROQ_DATA_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.19 12210 {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.20 12211 {"bits": [23, 23], "name": "GCRIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.21 12212 {"bits": [24, 24], "name": "MES_HQD_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.22 12213 {"bits": [26, 26], "name": "CPF_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.23 12214 {"bits": [27, 27], "name": "CPF_CMP_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.24 12215 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.25 12216 {"bits": [30, 30], "name": "CPC_CPF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.26 12217 {"bits": [31, 31], "name": "CPF_BUSY"} array in object:register_types.CP_CPF_STATUS.fields.27 12222 {"bits": [0, 15], "name": "DB_BASE_HI"} array in object:register_types.CP_DB_BASE_HI.fields.0 12227 {"bits": [2, 31], "name": "DB_BASE_LO"} array in object:register_types.CP_DB_BASE_LO.fields.0 12232 {"bits": [0, 19], "name": "DB_BUFSZ"} array in object:register_types.CP_DB_BUFSZ.fields.0 12237 {"bits": [0, 19], "name": "DB_CMD_REQSZ"} array in object:register_types.CP_DB_CMD_BUFSZ.fields.0 12242 {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"}, array in object:register_types.CP_DMA_CNTL.fields.0 12243 {"bits": [1, 1], "name": "WATCH_CONTROL"}, array in object:register_types.CP_DMA_CNTL.fields.1 12244 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, array in object:register_types.CP_DMA_CNTL.fields.2 12245 {"bits": [16, 24], "name": "BUFFER_DEPTH"}, array in object:register_types.CP_DMA_CNTL.fields.3 12246 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, array in object:register_types.CP_DMA_CNTL.fields.4 12247 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, array in object:register_types.CP_DMA_CNTL.fields.5 12248 {"bits": [30, 31], "name": "PIO_COUNT"} array in object:register_types.CP_DMA_CNTL.fields.6 12253 {"bits": [0, 15], "name": "ADDR_HI"}, array in object:register_types.CP_DMA_ME_CMD_ADDR_HI.fields.0 12254 {"bits": [16, 31], "name": "RSVD"} array in object:register_types.CP_DMA_ME_CMD_ADDR_HI.fields.1 12259 {"bits": [0, 1], "name": "RSVD"}, array in object:register_types.CP_DMA_ME_CMD_ADDR_LO.fields.0 12260 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_DMA_ME_CMD_ADDR_LO.fields.1 12265 {"bits": [0, 25], "name": "BYTE_COUNT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.0 12266 {"bits": [26, 26], "name": "SAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.1 12267 {"bits": [27, 27], "name": "DAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.2 12268 {"bits": [28, 28], "name": "SAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.3 12269 {"bits": [29, 29], "name": "DAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.4 12270 {"bits": [30, 30], "name": "RAW_WAIT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.5 12271 {"bits": [31, 31], "name": "DIS_WC"} array in object:register_types.CP_DMA_ME_COMMAND.fields.6 12276 {"bits": [0, 15], "name": "DST_ADDR_HI"} array in object:register_types.CP_DMA_ME_DST_ADDR_HI.fields.0 12281 {"bits": [0, 15], "name": "SRC_ADDR_HI"} array in object:register_types.CP_DMA_ME_SRC_ADDR_HI.fields.0 12286 {"bits": [10, 10], "name": "MEMLOG_CLEAR"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.0 12287 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.1 12288 {"bits": [15, 15], "name": "SRC_VOLATLE"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.2 12289 {"bits": [20, 21], "name": "DST_SELECT"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.3 12290 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.4 12291 {"bits": [27, 27], "name": "DST_VOLATLE"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.5 12292 {"bits": [29, 30], "name": "SRC_SELECT"} array in object:register_types.CP_DMA_PFP_CONTROL.fields.6 12297 {"bits": [0, 25], "name": "DMA_READ_TAG"}, array in object:register_types.CP_DMA_READ_TAGS.fields.0 12298 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} array in object:register_types.CP_DMA_READ_TAGS.fields.1 12303 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.0 12304 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.1 12305 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.2 12306 {"bits": [8, 8], "name": "MODE"} array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.3 12311 {"bits": [0, 15], "name": "MIN"}, array in object:register_types.CP_DRAW_WINDOW_LO.fields.0 12312 {"bits": [16, 31], "name": "MAX"} array in object:register_types.CP_DRAW_WINDOW_LO.fields.1 12317 {"bits": [0, 15], "name": "ADDR_HI"} array in object:register_types.CP_EOP_DONE_ADDR_HI.fields.0 12322 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.0 12327 {"bits": [16, 17], "name": "DST_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.0 12328 {"bits": [20, 21], "name": "ACTION_PIPE_ID"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.1 12329 {"bits": [22, 23], "name": "ACTION_ID"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.2 12330 {"bits": [24, 26], "name": "INT_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.3 12331 {"bits": [29, 31], "name": "DATA_SEL"} array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.4 12336 {"bits": [12, 23], "name": "GCR_CNTL"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.0 12337 {"bits": [25, 26], "name": "CACHE_POLICY"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.1 12338 {"bits": [27, 27], "name": "EOP_VOLATILE"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.2 12339 {"bits": [28, 28], "name": "EXECUTE"} array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.3 12344 {"bits": [0, 19], "name": "IB2_OFFSET"} array in object:register_types.CP_IB2_OFFSET.fields.0 12349 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} array in object:register_types.CP_IB2_PREAMBLE_BEGIN.fields.0 12354 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} array in object:register_types.CP_IB2_PREAMBLE_END.fields.0 12359 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} array in object:register_types.CP_INDEX_TYPE.fields.0 12364 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.0 12365 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.1 12366 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.2 12367 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.3 12368 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.4 12369 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.5 12370 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.6 12371 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.7 12372 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.8 12373 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.9 12374 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.10 12375 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.11 12376 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"} array in object:register_types.CP_ME_COHER_CNTL.fields.12 12381 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, array in object:register_types.CP_ME_COHER_STATUS.fields.0 12382 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_ME_COHER_STATUS.fields.1 12387 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"}, array in object:register_types.CP_ME_MC_RADDR_HI.fields.0 12388 {"bits": [22, 23], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_RADDR_HI.fields.1 12393 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} array in object:register_types.CP_ME_MC_RADDR_LO.fields.0 12398 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"}, array in object:register_types.CP_ME_MC_WADDR_HI.fields.0 12399 {"bits": [22, 23], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_WADDR_HI.fields.1 12404 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} array in object:register_types.CP_ME_MC_WADDR_LO.fields.0 12409 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.0 12410 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.1 12411 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, array in object:register_types.CP_PERFMON_CNTL.fields.2 12412 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.CP_PERFMON_CNTL.fields.3 12417 {"bits": [31, 31], "name": "PERFMON_ENABLE"} array in object:register_types.CP_PERFMON_CNTX_CNTL.fields.0 12422 {"bits": [0, 1], "name": "STATUS"} array in object:register_types.CP_PFP_COMPLETION_STATUS.fields.0 12427 {"bits": [0, 7], "name": "IB_EN"} array in object:register_types.CP_PFP_IB_CONTROL.fields.0 12432 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.0 12433 {"bits": [1, 1], "name": "CNTX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.1 12434 {"bits": [15, 15], "name": "UCONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.2 12435 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.3 12436 {"bits": [24, 24], "name": "SH_CS_REG_EN"} array in object:register_types.CP_PFP_LOAD_CONTROL.fields.4 12441 {"bits": [0, 1], "name": "PIPE_ID"} array in object:register_types.CP_PIPEID.fields.0 12446 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"} array in object:register_types.CP_PIPE_STATS_ADDR_HI.fields.0 12451 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.0 12456 {"bits": [25, 26], "name": "CACHE_POLICY"} array in object:register_types.CP_PIPE_STATS_CONTROL.fields.0 12461 {"bits": [0, 0], "name": "NOT_VISIBLE"} array in object:register_types.CP_PRED_NOT_VISIBLE.fields.0 12466 {"bits": [0, 19], "name": "RB_OFFSET"} array in object:register_types.CP_RB_OFFSET.fields.0 12471 {"bits": [0, 0], "name": "Z_PASS_ACITVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.0 12472 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.1 12473 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.2 12474 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.3 12475 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.4 12476 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.5 12477 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.6 12478 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"} array in object:register_types.CP_SAMPLE_STATUS.fields.7 12483 {"bits": [0, 15], "name": "SEM_ADDR_HI"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.0 12484 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.1 12485 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.2 12486 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.3 12487 {"bits": [29, 31], "name": "SEM_SELECT"} array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.4 12492 {"bits": [0, 0], "name": "SEM_PRIV"}, array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.0 12493 {"bits": [3, 31], "name": "SEM_ADDR_LO"} array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.1 12498 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"} array in object:register_types.CP_STREAM_OUT_ADDR_HI.fields.0 12503 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.0 12508 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} array in object:register_types.CP_STRMOUT_CNTL.fields.0 12513 {"bits": [0, 15], "name": "ST_BASE_HI"} array in object:register_types.CP_ST_BASE_HI.fields.0 12518 {"bits": [2, 31], "name": "ST_BASE_LO"} array in object:register_types.CP_ST_BASE_LO.fields.0 12523 {"bits": [0, 19], "name": "ST_BUFSZ"} array in object:register_types.CP_ST_BUFSZ.fields.0 12528 {"bits": [0, 19], "name": "ST_CMD_REQSZ"} array in object:register_types.CP_ST_CMD_BUFSZ.fields.0 12533 {"bits": [0, 3], "name": "VMID"} array in object:register_types.CP_VMID.fields.0 12538 {"bits": [0, 2], "name": "SRC_STATE_ID"} array in object:register_types.CS_COPY_STATE.fields.0 12543 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.0 12544 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.1 12545 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.2 12546 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.3 12547 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.4 12548 {"bits": [16, 16], "name": "OFFSET_ROUND"} array in object:register_types.DB_ALPHA_TO_MASK.fields.5 12553 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.0 12554 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.1 12555 {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.2 12556 {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.3 12557 {"bits": [4, 6], "name": "SAMPLE_RATE"}, array in object:register_types.DB_COUNT_CONTROL.fields.4 12558 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.5 12559 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.6 12560 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.7 12561 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.8 12562 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.9 12563 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} array in object:register_types.DB_COUNT_CONTROL.fields.10 12568 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.0 12569 {"bits": [1, 1], "name": "Z_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.1 12570 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.2 12571 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.3 12572 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.4 12573 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.5 12574 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.6 12575 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, array in object:register_types.DB_DEPTH_CONTROL.fields.7 12576 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, array in object:register_types.DB_DEPTH_CONTROL.fields.8 12577 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} array in object:register_types.DB_DEPTH_CONTROL.fields.9 12582 {"bits": [0, 13], "name": "X_MAX"}, array in object:register_types.DB_DEPTH_SIZE_XY.fields.0 12583 {"bits": [16, 29], "name": "Y_MAX"} array in object:register_types.DB_DEPTH_SIZE_XY.fields.1 12588 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.DB_DEPTH_VIEW.fields.0 12589 {"bits": [11, 12], "name": "SLICE_START_HI"}, array in object:register_types.DB_DEPTH_VIEW.fields.1 12590 {"bits": [13, 23], "name": "SLICE_MAX"}, array in object:register_types.DB_DEPTH_VIEW.fields.2 12591 {"bits": [24, 24], "name": "Z_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.3 12592 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.4 12593 {"bits": [26, 29], "name": "MIPID"}, array in object:register_types.DB_DEPTH_VIEW.fields.5 12594 {"bits": [30, 31], "name": "SLICE_MAX_HI"} array in object:register_types.DB_DEPTH_VIEW.fields.6 12599 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, array in object:register_types.DB_DFSM_CONTROL.fields.0 12600 {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"}, array in object:register_types.DB_DFSM_CONTROL.fields.1 12601 {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"} array in object:register_types.DB_DFSM_CONTROL.fields.2 12606 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, array in object:register_types.DB_EQAA.fields.0 12607 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, array in object:register_types.DB_EQAA.fields.1 12608 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.2 12609 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.3 12610 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, array in object:register_types.DB_EQAA.fields.4 12611 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, array in object:register_types.DB_EQAA.fields.5 12612 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, array in object:register_types.DB_EQAA.fields.6 12613 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, array in object:register_types.DB_EQAA.fields.7 12614 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, array in object:register_types.DB_EQAA.fields.8 12615 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, array in object:register_types.DB_EQAA.fields.9 12616 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, array in object:register_types.DB_EQAA.fields.10 12617 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} array in object:register_types.DB_EQAA.fields.11 12622 {"bits": [0, 0], "name": "RESERVED_FIELD_1"}, array in object:register_types.DB_HTILE_SURFACE.fields.0 12623 {"bits": [1, 1], "name": "FULL_CACHE"}, array in object:register_types.DB_HTILE_SURFACE.fields.1 12624 {"bits": [2, 2], "name": "RESERVED_FIELD_2"}, array in object:register_types.DB_HTILE_SURFACE.fields.2 12625 {"bits": [3, 3], "name": "RESERVED_FIELD_3"}, array in object:register_types.DB_HTILE_SURFACE.fields.3 12626 {"bits": [4, 9], "name": "RESERVED_FIELD_4"}, array in object:register_types.DB_HTILE_SURFACE.fields.4 12627 {"bits": [10, 15], "name": "RESERVED_FIELD_5"}, array in object:register_types.DB_HTILE_SURFACE.fields.5 12628 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}, array in object:register_types.DB_HTILE_SURFACE.fields.6 12629 {"bits": [17, 17], "name": "RESERVED_FIELD_6"}, array in object:register_types.DB_HTILE_SURFACE.fields.7 12630 {"bits": [18, 18], "name": "PIPE_ALIGNED"}, array in object:register_types.DB_HTILE_SURFACE.fields.8 12631 {"bits": [19, 20], "enum_ref": "VRSHtileEncoding", "name": "VRS_HTILE_ENCODING"} array in object:register_types.DB_HTILE_SURFACE.fields.9 12636 {"bits": [0, 30], "name": "COUNT_HI"} array in object:register_types.DB_OCCLUSION_COUNT0_HI.fields.0 12641 {"bits": [0, 7], "name": "START_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.0 12642 {"bits": [8, 15], "name": "START_Y"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.1 12643 {"bits": [16, 23], "name": "MAX_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.2 12644 {"bits": [24, 31], "name": "MAX_Y"} array in object:register_types.DB_PRELOAD_CONTROL.fields.3 12649 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.0 12650 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.1 12651 {"bits": [2, 2], "name": "DEPTH_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.2 12652 {"bits": [3, 3], "name": "STENCIL_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.3 12653 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.4 12654 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.5 12655 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.6 12656 {"bits": [7, 7], "name": "COPY_CENTROID"}, array in object:register_types.DB_RENDER_CONTROL.fields.7 12657 {"bits": [8, 11], "name": "COPY_SAMPLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.8 12658 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.9 12659 {"bits": [13, 13], "name": "PS_INVOKE_DISABLE"} array in object:register_types.DB_RENDER_CONTROL.fields.10 12664 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.0 12665 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.1 12666 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.2 12667 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.3 12668 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.4 12669 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.5 12670 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.6 12671 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.7 12672 {"bits": [11, 11], "name": "FORCE_Z_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.8 12673 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.9 12674 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.10 12675 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.11 12676 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.12 12677 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.13 12678 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.14 12679 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.15 12680 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.16 12681 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.17 12682 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.18 12683 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.19 12684 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.20 12685 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.21 12686 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} array in object:register_types.DB_RENDER_OVERRIDE.fields.22 12691 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.0 12692 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.1 12693 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.2 12694 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.3 12695 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.4 12696 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.5 12697 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.6 12698 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.7 12699 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.8 12700 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.9 12701 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.10 12702 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.11 12703 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.12 12704 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.13 12705 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.14 12706 {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.15 12707 {"bits": [26, 26], "name": "FORCE_VRS_RATE_FINE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.16 12708 {"bits": [27, 28], "name": "CENTROID_COMPUTATION_MODE"} array in object:register_types.DB_RENDER_OVERRIDE2.fields.17 12713 {"bits": [0, 10], "name": "FIELD_1"}, array in object:register_types.DB_RESERVED_REG_1.fields.0 12714 {"bits": [11, 21], "name": "FIELD_2"} array in object:register_types.DB_RESERVED_REG_1.fields.1 12719 {"bits": [0, 3], "name": "FIELD_1"}, array in object:register_types.DB_RESERVED_REG_2.fields.0 12720 {"bits": [4, 7], "name": "FIELD_2"}, array in object:register_types.DB_RESERVED_REG_2.fields.1 12721 {"bits": [8, 12], "name": "FIELD_3"}, array in object:register_types.DB_RESERVED_REG_2.fields.2 12722 {"bits": [13, 14], "name": "FIELD_4"}, array in object:register_types.DB_RESERVED_REG_2.fields.3 12723 {"bits": [15, 16], "name": "FIELD_5"}, array in object:register_types.DB_RESERVED_REG_2.fields.4 12724 {"bits": [17, 18], "name": "FIELD_6"}, array in object:register_types.DB_RESERVED_REG_2.fields.5 12725 {"bits": [19, 20], "name": "FIELD_7"}, array in object:register_types.DB_RESERVED_REG_2.fields.6 12726 {"bits": [28, 31], "name": "RESOURCE_LEVEL"} array in object:register_types.DB_RESERVED_REG_2.fields.7 12731 {"bits": [0, 21], "name": "FIELD_1"} array in object:register_types.DB_RESERVED_REG_3.fields.0 12736 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.0 12737 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.1 12738 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.2 12739 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.3 12740 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.4 12741 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.5 12742 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.6 12743 {"bits": [24, 24], "name": "Z_BIG_PAGE"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.7 12744 {"bits": [25, 25], "name": "S_BIG_PAGE"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.8 12745 {"bits": [26, 26], "name": "Z_NOALLOC"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.9 12746 {"bits": [27, 27], "name": "S_NOALLOC"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.10 12747 {"bits": [28, 28], "name": "HTILE_NOALLOC"}, array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.11 12748 {"bits": [29, 29], "name": "ZPCPSD_NOALLOC"} array in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.12 12753 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.0 12754 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.1 12755 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.2 12756 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, array in object:register_types.DB_SHADER_CONTROL.fields.3 12757 {"bits": [6, 6], "name": "KILL_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.4 12758 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.5 12759 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.6 12760 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, array in object:register_types.DB_SHADER_CONTROL.fields.7 12761 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, array in object:register_types.DB_SHADER_CONTROL.fields.8 12762 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.9 12763 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.10 12764 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, array in object:register_types.DB_SHADER_CONTROL.fields.11 12765 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.12 12766 {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.13 12767 {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"}, array in object:register_types.DB_SHADER_CONTROL.fields.14 12768 {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"}, array in object:register_types.DB_SHADER_CONTROL.fields.15 12769 {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"} array in object:register_types.DB_SHADER_CONTROL.fields.16 12774 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0 12775 {"bits": [4, 11], "name": "COMPAREVALUE0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.1 12776 {"bits": [12, 19], "name": "COMPAREMASK0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.2 12777 {"bits": [24, 24], "name": "ENABLE0"} array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.3 12782 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0 12783 {"bits": [4, 11], "name": "COMPAREVALUE1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.1 12784 {"bits": [12, 19], "name": "COMPAREMASK1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.2 12785 {"bits": [24, 24], "name": "ENABLE1"} array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.3 12790 {"bits": [0, 7], "name": "STENCILTESTVAL"}, array in object:register_types.DB_STENCILREFMASK.fields.0 12791 {"bits": [8, 15], "name": "STENCILMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.1 12792 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.2 12793 {"bits": [24, 31], "name": "STENCILOPVAL"} array in object:register_types.DB_STENCILREFMASK.fields.3 12798 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.0 12799 {"bits": [8, 15], "name": "STENCILMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.1 12800 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.2 12801 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} array in object:register_types.DB_STENCILREFMASK_BF.fields.3 12806 {"bits": [0, 7], "name": "CLEAR"} array in object:register_types.DB_STENCIL_CLEAR.fields.0 12811 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.0 12812 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, array in object:register_types.DB_STENCIL_CONTROL.fields.1 12813 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.2 12814 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.3 12815 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.4 12816 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} array in object:register_types.DB_STENCIL_CONTROL.fields.5 12821 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, array in object:register_types.DB_STENCIL_INFO.fields.0 12822 {"bits": [4, 8], "name": "SW_MODE"}, array in object:register_types.DB_STENCIL_INFO.fields.1 12823 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, array in object:register_types.DB_STENCIL_INFO.fields.2 12824 {"bits": [11, 11], "name": "ITERATE_FLUSH"}, array in object:register_types.DB_STENCIL_INFO.fields.3 12825 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, array in object:register_types.DB_STENCIL_INFO.fields.4 12826 {"bits": [13, 15], "name": "RESERVED_FIELD_1"}, array in object:register_types.DB_STENCIL_INFO.fields.5 12827 {"bits": [20, 20], "name": "ITERATE_256"}, array in object:register_types.DB_STENCIL_INFO.fields.6 12828 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_STENCIL_INFO.fields.7 12829 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} array in object:register_types.DB_STENCIL_INFO.fields.8 12834 {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VRS_OVERRIDE_RATE_COMBINER_MODE"}, array in object:register_types.DB_VRS_OVERRIDE_CNTL.fields.0 12835 {"bits": [4, 5], "name": "VRS_OVERRIDE_RATE_X"}, array in object:register_types.DB_VRS_OVERRIDE_CNTL.fields.1 12836 {"bits": [6, 7], "name": "VRS_OVERRIDE_RATE_Y"} array in object:register_types.DB_VRS_OVERRIDE_CNTL.fields.2 12841 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, array in object:register_types.DB_Z_INFO.fields.0 12842 {"bits": [2, 3], "name": "NUM_SAMPLES"}, array in object:register_types.DB_Z_INFO.fields.1 12843 {"bits": [4, 8], "name": "SW_MODE"}, array in object:register_types.DB_Z_INFO.fields.2 12844 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, array in object:register_types.DB_Z_INFO.fields.3 12845 {"bits": [11, 11], "name": "ITERATE_FLUSH"}, array in object:register_types.DB_Z_INFO.fields.4 12846 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, array in object:register_types.DB_Z_INFO.fields.5 12847 {"bits": [13, 15], "name": "RESERVED_FIELD_1"}, array in object:register_types.DB_Z_INFO.fields.6 12848 {"bits": [16, 19], "name": "MAXMIP"}, array in object:register_types.DB_Z_INFO.fields.7 12849 {"bits": [20, 20], "name": "ITERATE_256"}, array in object:register_types.DB_Z_INFO.fields.8 12850 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"}, array in object:register_types.DB_Z_INFO.fields.9 12851 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_Z_INFO.fields.10 12852 {"bits": [28, 28], "name": "READ_SIZE"}, array in object:register_types.DB_Z_INFO.fields.11 12853 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, array in object:register_types.DB_Z_INFO.fields.12 12854 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} array in object:register_types.DB_Z_INFO.fields.13 12859 {"bits": [0, 7], "name": "BASE_HI"} array in object:register_types.DB_Z_READ_BASE_HI.fields.0 12864 {"bits": [0, 2], "name": "NUM_PIPES"}, array in object:register_types.GB_ADDR_CONFIG.fields.0 12865 {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.1 12866 {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"}, array in object:register_types.GB_ADDR_CONFIG.fields.2 12867 {"bits": [8, 10], "name": "NUM_PKRS"}, array in object:register_types.GB_ADDR_CONFIG.fields.3 12868 {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"}, array in object:register_types.GB_ADDR_CONFIG.fields.4 12869 {"bits": [26, 27], "name": "NUM_RB_PER_SE"} array in object:register_types.GB_ADDR_CONFIG.fields.5 12874 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.GCEA_PERFCOUNTER0_CFG.fields.0 12875 {"bits": [8, 15], "name": "PERF_SEL_END"}, array in object:register_types.GCEA_PERFCOUNTER0_CFG.fields.1 12876 {"bits": [24, 27], "name": "PERF_MODE"}, array in object:register_types.GCEA_PERFCOUNTER0_CFG.fields.2 12877 {"bits": [28, 28], "name": "ENABLE"}, array in object:register_types.GCEA_PERFCOUNTER0_CFG.fields.3 12878 {"bits": [29, 29], "name": "CLEAR"} array in object:register_types.GCEA_PERFCOUNTER0_CFG.fields.4 12883 {"bits": [0, 1], "name": "COMPARE_MODE0"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.0 12884 {"bits": [2, 3], "name": "COMPARE_MODE1"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.1 12885 {"bits": [4, 5], "name": "COMPARE_MODE2"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.2 12886 {"bits": [6, 7], "name": "COMPARE_MODE3"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.3 12887 {"bits": [8, 11], "name": "COMPARE_VALUE0"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.4 12888 {"bits": [12, 15], "name": "COMPARE_VALUE1"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.5 12889 {"bits": [16, 19], "name": "COMPARE_VALUE2"}, array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.6 12890 {"bits": [20, 23], "name": "COMPARE_VALUE3"} array in object:register_types.GCEA_PERFCOUNTER2_MODE.fields.7 12895 {"bits": [0, 15], "name": "COUNTER_HI"}, array in object:register_types.GCEA_PERFCOUNTER_HI.fields.0 12896 {"bits": [16, 31], "name": "COMPARE_VALUE"} array in object:register_types.GCEA_PERFCOUNTER_HI.fields.1 12901 {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"}, array in object:register_types.GCEA_PERFCOUNTER_RSLT_CNTL.fields.0 12902 {"bits": [8, 15], "name": "START_TRIGGER"}, array in object:register_types.GCEA_PERFCOUNTER_RSLT_CNTL.fields.1 12903 {"bits": [16, 23], "name": "STOP_TRIGGER"}, array in object:register_types.GCEA_PERFCOUNTER_RSLT_CNTL.fields.2 12904 {"bits": [24, 24], "name": "ENABLE_ANY"}, array in object:register_types.GCEA_PERFCOUNTER_RSLT_CNTL.fields.3 12905 {"bits": [25, 25], "name": "CLEAR_ALL"}, array in object:register_types.GCEA_PERFCOUNTER_RSLT_CNTL.fields.4 12906 {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"} array in object:register_types.GCEA_PERFCOUNTER_RSLT_CNTL.fields.5 12911 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.GCR_PERFCOUNTER1_SELECT.fields.0 12912 {"bits": [24, 27], "name": "PERF_MODE"}, array in object:register_types.GCR_PERFCOUNTER1_SELECT.fields.1 12913 {"bits": [28, 31], "name": "CNTL_MODE"} array in object:register_types.GCR_PERFCOUNTER1_SELECT.fields.2 12918 {"bits": [0, 15], "name": "BASE"}, array in object:register_types.GDS_ATOM_BASE.fields.0 12919 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_BASE.fields.1 12924 {"bits": [0, 5], "name": "AINC"}, array in object:register_types.GDS_ATOM_CNTL.fields.0 12925 {"bits": [6, 7], "name": "UNUSED1"}, array in object:register_types.GDS_ATOM_CNTL.fields.1 12926 {"bits": [8, 9], "name": "DMODE"}, array in object:register_types.GDS_ATOM_CNTL.fields.2 12927 {"bits": [10, 31], "name": "UNUSED2"} array in object:register_types.GDS_ATOM_CNTL.fields.3 12932 {"bits": [0, 0], "name": "COMPLETE"}, array in object:register_types.GDS_ATOM_COMPLETE.fields.0 12933 {"bits": [1, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_COMPLETE.fields.1 12938 {"bits": [0, 7], "name": "OFFSET0"}, array in object:register_types.GDS_ATOM_OFFSET0.fields.0 12939 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET0.fields.1 12944 {"bits": [0, 7], "name": "OFFSET1"}, array in object:register_types.GDS_ATOM_OFFSET1.fields.0 12945 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET1.fields.1 12950 {"bits": [0, 7], "name": "OP"}, array in object:register_types.GDS_ATOM_OP.fields.0 12951 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OP.fields.1 12956 {"bits": [0, 15], "name": "SIZE"}, array in object:register_types.GDS_ATOM_SIZE.fields.0 12957 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_SIZE.fields.1 12962 {"bits": [0, 0], "name": "FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.0 12963 {"bits": [1, 12], "name": "COUNTER"}, array in object:register_types.GDS_GWS_RESOURCE.fields.1 12964 {"bits": [13, 13], "name": "TYPE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.2 12965 {"bits": [14, 14], "name": "DED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.3 12966 {"bits": [15, 15], "name": "RELEASE_ALL"}, array in object:register_types.GDS_GWS_RESOURCE.fields.4 12967 {"bits": [16, 26], "name": "HEAD_QUEUE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.5 12968 {"bits": [27, 27], "name": "HEAD_VALID"}, array in object:register_types.GDS_GWS_RESOURCE.fields.6 12969 {"bits": [28, 28], "name": "HEAD_FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.7 12970 {"bits": [29, 29], "name": "HALTED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.8 12971 {"bits": [30, 30], "name": "HEAD_QUEUE1"}, array in object:register_types.GDS_GWS_RESOURCE.fields.9 12972 {"bits": [31, 31], "name": "UNUSED1"} array in object:register_types.GDS_GWS_RESOURCE.fields.10 12977 {"bits": [0, 15], "name": "RESOURCE_CNT"}, array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.0 12978 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.1 12983 {"bits": [0, 5], "name": "INDEX"}, array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.0 12984 {"bits": [6, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.1 12989 {"bits": [0, 15], "name": "DS_ADDRESS"}, array in object:register_types.GDS_OA_ADDRESS.fields.0 12990 {"bits": [16, 19], "name": "CRAWLER_TYPE"}, array in object:register_types.GDS_OA_ADDRESS.fields.1 12991 {"bits": [20, 23], "name": "CRAWLER"}, array in object:register_types.GDS_OA_ADDRESS.fields.2 12992 {"bits": [24, 29], "name": "UNUSED"}, array in object:register_types.GDS_OA_ADDRESS.fields.3 12993 {"bits": [30, 30], "name": "NO_ALLOC"}, array in object:register_types.GDS_OA_ADDRESS.fields.4 12994 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.GDS_OA_ADDRESS.fields.5 12999 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.GDS_OA_CNTL.fields.0 13000 {"bits": [4, 31], "name": "UNUSED"} array in object:register_types.GDS_OA_CNTL.fields.1 13005 {"bits": [0, 30], "name": "VALUE"}, array in object:register_types.GDS_OA_INCDEC.fields.0 13006 {"bits": [31, 31], "name": "INCDEC"} array in object:register_types.GDS_OA_INCDEC.fields.1 13011 {"bits": [0, 9], "name": "PERF_SEL0"}, array in object:register_types.GE1_PERFCOUNTER0_SELECT.fields.0 13012 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.GE1_PERFCOUNTER0_SELECT.fields.1 13013 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.GE1_PERFCOUNTER0_SELECT.fields.2 13014 {"bits": [24, 27], "name": "PERF_MODE0"}, array in object:register_types.GE1_PERFCOUNTER0_SELECT.fields.3 13015 {"bits": [28, 31], "name": "PERF_MODE1"} array in object:register_types.GE1_PERFCOUNTER0_SELECT.fields.4 13020 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.GE1_PERFCOUNTER0_SELECT1.fields.0 13021 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.GE1_PERFCOUNTER0_SELECT1.fields.1 13022 {"bits": [24, 27], "name": "PERF_MODE2"}, array in object:register_types.GE1_PERFCOUNTER0_SELECT1.fields.2 13023 {"bits": [28, 31], "name": "PERF_MODE3"} array in object:register_types.GE1_PERFCOUNTER0_SELECT1.fields.3 13028 {"bits": [0, 8], "name": "PRIM_GRP_SIZE"}, array in object:register_types.GE_CNTL.fields.0 13029 {"bits": [9, 17], "name": "VERT_GRP_SIZE"}, array in object:register_types.GE_CNTL.fields.1 13030 {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"}, array in object:register_types.GE_CNTL.fields.2 13031 {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"} array in object:register_types.GE_CNTL.fields.3 13036 {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"} array in object:register_types.GE_MAX_OUTPUT_PER_SUBGROUP.fields.0 13041 {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"}, array in object:register_types.GE_NGG_SUBGRP_CNTL.fields.0 13042 {"bits": [9, 17], "name": "THDS_PER_SUBGRP"} array in object:register_types.GE_NGG_SUBGRP_CNTL.fields.1 13047 {"bits": [0, 0], "name": "OVERSUB_EN"}, array in object:register_types.GE_PC_ALLOC.fields.0 13048 {"bits": [1, 10], "name": "NUM_PC_LINES"} array in object:register_types.GE_PC_ALLOC.fields.1 13053 {"bits": [0, 2], "name": "RT_SLICE"}, array in object:register_types.GE_STEREO_CNTL.fields.0 13054 {"bits": [3, 6], "name": "VIEWPORT"}, array in object:register_types.GE_STEREO_CNTL.fields.1 13055 {"bits": [8, 8], "name": "EN_STEREO"} array in object:register_types.GE_STEREO_CNTL.fields.2 13060 {"bits": [0, 0], "name": "EN_USER_VGPR1"}, array in object:register_types.GE_USER_VGPR_EN.fields.0 13061 {"bits": [1, 1], "name": "EN_USER_VGPR2"}, array in object:register_types.GE_USER_VGPR_EN.fields.1 13062 {"bits": [2, 2], "name": "EN_USER_VGPR3"} array in object:register_types.GE_USER_VGPR_EN.fields.2 13067 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.0 13068 {"bits": [8, 15], "name": "SA_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.1 13069 {"bits": [16, 23], "name": "SE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.2 13070 {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.3 13071 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.4 13072 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} array in object:register_types.GRBM_GFX_INDEX.fields.5 13077 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.0 13078 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.1 13079 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.2 13080 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.3 13081 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.4 13082 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.5 13083 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.6 13084 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.7 13085 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.8 13086 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.9 13087 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.10 13088 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.11 13089 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.12 13090 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.13 13091 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.14 13092 {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.15 13093 {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.16 13094 {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.17 13095 {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.18 13096 {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.19 13101 {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.0 13102 {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.1 13103 {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.2 13104 {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.3 13105 {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.4 13106 {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.5 13107 {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.6 13108 {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT_HI.fields.7 13113 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.0 13114 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.1 13115 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.2 13116 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.3 13117 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.4 13118 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.5 13119 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.6 13120 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.7 13121 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.8 13122 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.9 13123 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.10 13124 {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.11 13125 {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.12 13126 {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.13 13127 {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.14 13132 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS.fields.0 13133 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.1 13134 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.2 13135 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.3 13136 {"bits": [12, 12], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.4 13137 {"bits": [13, 13], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.5 13138 {"bits": [14, 14], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.6 13139 {"bits": [15, 15], "name": "GDS_BUSY"}, array in object:register_types.GRBM_STATUS.fields.7 13140 {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.8 13141 {"bits": [20, 20], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS.fields.9 13142 {"bits": [21, 21], "name": "GE_BUSY"}, array in object:register_types.GRBM_STATUS.fields.10 13143 {"bits": [22, 22], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.11 13144 {"bits": [23, 23], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.12 13145 {"bits": [24, 24], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS.fields.13 13146 {"bits": [25, 25], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.14 13147 {"bits": [26, 26], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.15 13148 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, array in object:register_types.GRBM_STATUS.fields.16 13149 {"bits": [29, 29], "name": "CP_BUSY"}, array in object:register_types.GRBM_STATUS.fields.17 13150 {"bits": [30, 30], "name": "CB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.18 13151 {"bits": [31, 31], "name": "GUI_ACTIVE"} array in object:register_types.GRBM_STATUS.fields.19 13156 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS2.fields.0 13157 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.1 13158 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.2 13159 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.3 13160 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.4 13161 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.5 13162 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.6 13163 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.7 13164 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.8 13165 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.9 13166 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.10 13167 {"bits": [14, 14], "name": "RLC_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.11 13168 {"bits": [15, 15], "name": "UTCL2_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.12 13169 {"bits": [16, 16], "name": "EA_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.13 13170 {"bits": [17, 17], "name": "RMI_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.14 13171 {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.15 13172 {"bits": [19, 19], "name": "SDMA_SCH_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.16 13173 {"bits": [20, 20], "name": "EA_LINK_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.17 13174 {"bits": [21, 21], "name": "SDMA_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.18 13175 {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.19 13176 {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.20 13177 {"bits": [24, 24], "name": "SDMA2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.21 13178 {"bits": [25, 25], "name": "SDMA3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.22 13179 {"bits": [26, 26], "name": "RLC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.23 13180 {"bits": [27, 27], "name": "TCP_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.24 13181 {"bits": [28, 28], "name": "CPF_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.25 13182 {"bits": [29, 29], "name": "CPC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.26 13183 {"bits": [30, 30], "name": "CPG_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.27 13184 {"bits": [31, 31], "name": "CPAXI_BUSY"} array in object:register_types.GRBM_STATUS2.fields.28 13189 {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.0 13190 {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.1 13191 {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.2 13192 {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.3 13193 {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.4 13194 {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.5 13195 {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS3.fields.6 13196 {"bits": [13, 13], "name": "PH_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.7 13197 {"bits": [14, 14], "name": "CH_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.8 13198 {"bits": [15, 15], "name": "GL2CC_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.9 13199 {"bits": [16, 16], "name": "GL1CC_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.10 13200 {"bits": [28, 28], "name": "GUS_LINK_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.11 13201 {"bits": [29, 29], "name": "GUS_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.12 13202 {"bits": [30, 30], "name": "UTCL1_BUSY"}, array in object:register_types.GRBM_STATUS3.fields.13 13203 {"bits": [31, 31], "name": "PMM_BUSY"} array in object:register_types.GRBM_STATUS3.fields.14 13208 {"bits": [1, 1], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.0 13209 {"bits": [2, 2], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.1 13210 {"bits": [3, 3], "name": "UTCL1_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.2 13211 {"bits": [4, 4], "name": "TCP_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.3 13212 {"bits": [5, 5], "name": "GL1CC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.4 13213 {"bits": [21, 21], "name": "RMI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.5 13214 {"bits": [22, 22], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.6 13215 {"bits": [24, 24], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.7 13216 {"bits": [25, 25], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.8 13217 {"bits": [26, 26], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.9 13218 {"bits": [27, 27], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.10 13219 {"bits": [29, 29], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.11 13220 {"bits": [30, 30], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.12 13221 {"bits": [31, 31], "name": "CB_BUSY"} array in object:register_types.GRBM_STATUS_SE0.fields.13 13226 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.0 13227 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.1 13228 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.2 13229 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.3 13230 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.4 13231 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} array in object:register_types.IA_MULTI_VGT_PARAM.fields.5 13236 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.0 13237 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.1 13238 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.2 13239 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.3 13240 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.4 13241 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.5 13242 {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.6 13243 {"bits": [22, 22], "name": "EN_INST_OPT_ADV"}, array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.7 13244 {"bits": [23, 23], "name": "HW_USE_ONLY"} array in object:register_types.IA_MULTI_VGT_PARAM_PIPED.fields.8 13249 {"bits": [0, 0], "name": "UCP_ENA_0"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.0 13250 {"bits": [1, 1], "name": "UCP_ENA_1"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.1 13251 {"bits": [2, 2], "name": "UCP_ENA_2"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.2 13252 {"bits": [3, 3], "name": "UCP_ENA_3"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.3 13253 {"bits": [4, 4], "name": "UCP_ENA_4"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.4 13254 {"bits": [5, 5], "name": "UCP_ENA_5"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.5 13255 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.6 13256 {"bits": [14, 15], "name": "PS_UCP_MODE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.7 13257 {"bits": [16, 16], "name": "CLIP_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.8 13258 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.9 13259 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.10 13260 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.11 13261 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.12 13262 {"bits": [21, 21], "name": "VTX_KILL_OR"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.13 13263 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.14 13264 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.15 13265 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.16 13266 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.17 13267 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.18 13268 {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"} array in object:register_types.PA_CL_CLIP_CNTL.fields.19 13273 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.0 13274 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.1 13275 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.2 13276 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.3 13277 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.4 13278 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.5 13279 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.6 13280 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.7 13281 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.8 13282 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.9 13283 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.10 13284 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.11 13285 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.12 13286 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.13 13287 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.14 13288 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} array in object:register_types.PA_CL_NANINF_CNTL.fields.15 13293 {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"}, array in object:register_types.PA_CL_NGG_CNTL.fields.0 13294 {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"}, array in object:register_types.PA_CL_NGG_CNTL.fields.1 13295 {"bits": [2, 9], "name": "VERTEX_REUSE_DEPTH"} array in object:register_types.PA_CL_NGG_CNTL.fields.2 13300 {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VERTEX_RATE_COMBINER_MODE"}, array in object:register_types.PA_CL_VRS_CNTL.fields.0 13301 {"bits": [3, 5], "enum_ref": "VRSCombinerMode", "name": "PRIMITIVE_RATE_COMBINER_MODE"}, array in object:register_types.PA_CL_VRS_CNTL.fields.1 13302 {"bits": [6, 8], "enum_ref": "VRSCombinerMode", "name": "HTILE_RATE_COMBINER_MODE"}, array in object:register_types.PA_CL_VRS_CNTL.fields.2 13303 {"bits": [9, 11], "enum_ref": "VRSCombinerMode", "name": "SAMPLE_ITER_COMBINER_MODE"}, array in object:register_types.PA_CL_VRS_CNTL.fields.3 13304 {"bits": [13, 13], "name": "EXPOSE_VRS_PIXELS_MASK"}, array in object:register_types.PA_CL_VRS_CNTL.fields.4 13305 {"bits": [14, 14], "name": "CMASK_RATE_HINT_FORCE_ZERO"} array in object:register_types.PA_CL_VRS_CNTL.fields.5 13310 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.0 13311 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.1 13312 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.2 13313 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.3 13314 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.4 13315 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.5 13316 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.6 13317 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.7 13318 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.8 13319 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.9 13320 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.10 13321 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.11 13322 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.12 13323 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.13 13324 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.14 13325 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.15 13326 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.16 13327 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.17 13328 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.18 13329 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.19 13330 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.20 13331 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.21 13332 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.22 13333 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.23 13334 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.24 13335 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.25 13336 {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.26 13337 {"bits": [28, 28], "name": "USE_VTX_VRS_RATE"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.27 13338 {"bits": [29, 29], "name": "BYPASS_VTX_RATE_COMBINER"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.28 13339 {"bits": [30, 30], "name": "BYPASS_PRIM_RATE_COMBINER"} array in object:register_types.PA_CL_VS_OUT_CNTL.fields.29 13344 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.0 13345 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.1 13346 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.2 13347 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.3 13348 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.4 13349 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.5 13350 {"bits": [8, 8], "name": "VTX_XY_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.6 13351 {"bits": [9, 9], "name": "VTX_Z_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.7 13352 {"bits": [10, 10], "name": "VTX_W0_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.8 13353 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} array in object:register_types.PA_CL_VTE_CNTL.fields.9 13358 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.0 13359 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, array in object:register_types.PA_SC_AA_CONFIG.fields.1 13360 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, array in object:register_types.PA_SC_AA_CONFIG.fields.2 13361 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.3 13362 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}, array in object:register_types.PA_SC_AA_CONFIG.fields.4 13363 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}, array in object:register_types.PA_SC_AA_CONFIG.fields.5 13364 {"bits": [28, 28], "name": "SAMPLE_COVERAGE_ENCODING"}, array in object:register_types.PA_SC_AA_CONFIG.fields.6 13365 {"bits": [29, 29], "name": "COVERED_CENTROID_IS_CENTER"} array in object:register_types.PA_SC_AA_CONFIG.fields.7 13370 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.0 13371 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.1 13376 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.0 13377 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.1 13382 {"bits": [0, 3], "name": "S0_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.0 13383 {"bits": [4, 7], "name": "S0_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.1 13384 {"bits": [8, 11], "name": "S1_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.2 13385 {"bits": [12, 15], "name": "S1_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.3 13386 {"bits": [16, 19], "name": "S2_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.4 13387 {"bits": [20, 23], "name": "S2_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.5 13388 {"bits": [24, 27], "name": "S3_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.6 13389 {"bits": [28, 31], "name": "S3_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.7 13394 {"bits": [0, 3], "name": "S4_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.0 13395 {"bits": [4, 7], "name": "S4_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.1 13396 {"bits": [8, 11], "name": "S5_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.2 13397 {"bits": [12, 15], "name": "S5_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.3 13398 {"bits": [16, 19], "name": "S6_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.4 13399 {"bits": [20, 23], "name": "S6_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.5 13400 {"bits": [24, 27], "name": "S7_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.6 13401 {"bits": [28, 31], "name": "S7_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.7 13406 {"bits": [0, 3], "name": "S8_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.0 13407 {"bits": [4, 7], "name": "S8_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.1 13408 {"bits": [8, 11], "name": "S9_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.2 13409 {"bits": [12, 15], "name": "S9_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.3 13410 {"bits": [16, 19], "name": "S10_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.4 13411 {"bits": [20, 23], "name": "S10_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.5 13412 {"bits": [24, 27], "name": "S11_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.6 13413 {"bits": [28, 31], "name": "S11_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.7 13418 {"bits": [0, 3], "name": "S12_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.0 13419 {"bits": [4, 7], "name": "S12_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.1 13420 {"bits": [8, 11], "name": "S13_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.2 13421 {"bits": [12, 15], "name": "S13_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.3 13422 {"bits": [16, 19], "name": "S14_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.4 13423 {"bits": [20, 23], "name": "S14_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.5 13424 {"bits": [24, 27], "name": "S15_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.6 13425 {"bits": [28, 31], "name": "S15_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.7 13430 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.0 13431 {"bits": [2, 2], "name": "BIN_SIZE_X"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.1 13432 {"bits": [3, 3], "name": "BIN_SIZE_Y"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.2 13433 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.3 13434 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.4 13435 {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.5 13436 {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.6 13437 {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.7 13438 {"bits": [19, 26], "name": "FPOVS_PER_BATCH"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.8 13439 {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.9 13440 {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.10 13441 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"} array in object:register_types.PA_SC_BINNER_CNTL_0.fields.11 13446 {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"}, array in object:register_types.PA_SC_BINNER_CNTL_1.fields.0 13447 {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"} array in object:register_types.PA_SC_BINNER_CNTL_1.fields.1 13452 {"bits": [0, 3], "name": "DISTANCE_0"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.0 13453 {"bits": [4, 7], "name": "DISTANCE_1"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.1 13454 {"bits": [8, 11], "name": "DISTANCE_2"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.2 13455 {"bits": [12, 15], "name": "DISTANCE_3"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.3 13456 {"bits": [16, 19], "name": "DISTANCE_4"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.4 13457 {"bits": [20, 23], "name": "DISTANCE_5"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.5 13458 {"bits": [24, 27], "name": "DISTANCE_6"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.6 13459 {"bits": [28, 31], "name": "DISTANCE_7"} array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.7 13464 {"bits": [0, 3], "name": "DISTANCE_8"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.0 13465 {"bits": [4, 7], "name": "DISTANCE_9"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.1 13466 {"bits": [8, 11], "name": "DISTANCE_10"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.2 13467 {"bits": [12, 15], "name": "DISTANCE_11"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.3 13468 {"bits": [16, 19], "name": "DISTANCE_12"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.4 13469 {"bits": [20, 23], "name": "DISTANCE_13"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.5 13470 {"bits": [24, 27], "name": "DISTANCE_14"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.6 13471 {"bits": [28, 31], "name": "DISTANCE_15"} array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.7 13476 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.0 13477 {"bits": [16, 30], "name": "TL_Y"} array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.1 13482 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} array in object:register_types.PA_SC_CLIPRECT_RULE.fields.0 13487 {"bits": [0, 0], "name": "OVER_RAST_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.0 13488 {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.1 13489 {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.2 13490 {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.3 13491 {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.4 13492 {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.5 13493 {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.6 13494 {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.7 13495 {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.8 13496 {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.9 13497 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE" array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.10 13498 {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.11 13499 {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.12 13500 {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.13 13501 {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.14 13502 {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.15 13503 {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.16 13504 {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.17 13505 {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.18 13506 {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"} array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.19 13511 {"bits": [0, 3], "name": "ER_TRI"}, array in object:register_types.PA_SC_EDGERULE.fields.0 13512 {"bits": [4, 7], "name": "ER_POINT"}, array in object:register_types.PA_SC_EDGERULE.fields.1 13513 {"bits": [8, 11], "name": "ER_RECT"}, array in object:register_types.PA_SC_EDGERULE.fields.2 13514 {"bits": [12, 17], "name": "ER_LINE_LR"}, array in object:register_types.PA_SC_EDGERULE.fields.3 13515 {"bits": [18, 23], "name": "ER_LINE_RL"}, array in object:register_types.PA_SC_EDGERULE.fields.4 13516 {"bits": [24, 27], "name": "ER_LINE_TB"}, array in object:register_types.PA_SC_EDGERULE.fields.5 13517 {"bits": [28, 31], "name": "ER_LINE_BT"} array in object:register_types.PA_SC_EDGERULE.fields.6 13522 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, array in object:register_types.PA_SC_LINE_CNTL.fields.0 13523 {"bits": [10, 10], "name": "LAST_PIXEL"}, array in object:register_types.PA_SC_LINE_CNTL.fields.1 13524 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.2 13525 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.3 13526 {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"} array in object:register_types.PA_SC_LINE_CNTL.fields.4 13531 {"bits": [0, 15], "name": "LINE_PATTERN"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.0 13532 {"bits": [16, 23], "name": "REPEAT_COUNT"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.1 13533 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.2 13534 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} array in object:register_types.PA_SC_LINE_STIPPLE.fields.3 13539 {"bits": [0, 3], "name": "CURRENT_PTR"}, array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.0 13540 {"bits": [8, 15], "name": "CURRENT_COUNT"} array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.1 13545 {"bits": [0, 0], "name": "MSAA_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.0 13546 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.1 13547 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.2 13548 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.3 13549 {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.4 13550 {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"} array in object:register_types.PA_SC_MODE_CNTL_0.fields.5 13555 {"bits": [0, 0], "name": "WALK_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.0 13556 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.1 13557 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.2 13558 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.3 13559 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.4 13560 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.5 13561 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.6 13562 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.7 13563 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.8 13564 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.9 13565 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.10 13566 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.11 13567 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.12 13568 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.13 13569 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.14 13570 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.15 13571 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.16 13572 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.17 13573 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.18 13574 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.19 13575 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.20 13576 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.21 13577 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.22 13578 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} array in object:register_types.PA_SC_MODE_CNTL_1.fields.23 13583 {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"}, array in object:register_types.PA_SC_NGG_MODE_CNTL.fields.0 13584 {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"} array in object:register_types.PA_SC_NGG_MODE_CNTL.fields.1 13589 {"bits": [0, 13], "name": "X_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_H.fields.0 13594 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"}, array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.0 13595 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.1 13600 {"bits": [0, 15], "name": "COUNT"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_OCCURRENCE.fields.0 13605 {"bits": [0, 13], "name": "Y_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_V.fields.0 13610 {"bits": [0, 9], "name": "PERF_SEL"} array in object:register_types.PA_SC_PERFCOUNTER1_SELECT.fields.0 13615 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.0 13616 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.1 13617 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.2 13618 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.3 13619 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.4 13620 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.5 13621 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.6 13622 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.7 13623 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.8 13624 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.9 13625 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.10 13626 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.11 13627 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.12 13628 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.13 13629 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG.fields.14 13634 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0 13635 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1 13636 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2 13641 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.0 13642 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"} array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.1 13647 {"bits": [0, 15], "name": "X"}, array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.0 13648 {"bits": [16, 31], "name": "Y"} array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.1 13653 {"bits": [0, 15], "name": "BR_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.0 13654 {"bits": [16, 31], "name": "BR_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.1 13659 {"bits": [0, 15], "name": "TL_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.0 13660 {"bits": [16, 31], "name": "TL_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.1 13665 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.0 13666 {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.1 13667 {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.2 13668 {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"} array in object:register_types.PA_SC_SHADER_CONTROL.fields.3 13673 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.0 13674 {"bits": [1, 2], "name": "NUM_SE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.1 13675 {"bits": [5, 6], "name": "NUM_RB_PER_SE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.2 13676 {"bits": [12, 13], "name": "NUM_SC"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.3 13677 {"bits": [16, 17], "name": "NUM_RB_PER_SC"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.4 13678 {"bits": [20, 21], "name": "NUM_PACKER_PER_SC"} array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.5 13683 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, array in object:register_types.PA_SC_WINDOW_OFFSET.fields.0 13684 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} array in object:register_types.PA_SC_WINDOW_OFFSET.fields.1 13689 {"bits": [0, 14], "name": "BR_X"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_BR.fields.0 13690 {"bits": [16, 30], "name": "BR_Y"} array in object:register_types.PA_SC_WINDOW_SCISSOR_BR.fields.1 13695 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.0 13696 {"bits": [16, 30], "name": "TL_Y"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.1 13697 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.2 13702 {"bits": [1, 4], "name": "STEREO_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.0 13703 {"bits": [5, 7], "name": "RT_SLICE_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.1 13704 {"bits": [8, 11], "name": "RT_SLICE_OFFSET"}, array in object:register_types.PA_STEREO_CNTL.fields.2 13705 {"bits": [16, 18], "name": "VP_ID_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.3 13706 {"bits": [19, 22], "name": "VP_ID_OFFSET"} array in object:register_types.PA_STEREO_CNTL.fields.4 13711 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.0 13712 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.1 13717 {"bits": [0, 15], "name": "WIDTH"} array in object:register_types.PA_SU_LINE_CNTL.fields.0 13722 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.0 13723 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.1 13724 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.2 13725 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.3 13730 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} array in object:register_types.PA_SU_LINE_STIPPLE_VALUE.fields.0 13735 {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.0 13736 {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.1 13737 {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.2 13738 {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.3 13739 {"bits": [4, 4], "name": "USE_PROVOKING_ZW"} array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.4 13744 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.0 13745 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.1 13746 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.2 13747 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.3 13748 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.4 13753 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.0 13754 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.1 13755 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.2 13756 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.3 13761 {"bits": [0, 15], "name": "MIN_SIZE"}, array in object:register_types.PA_SU_POINT_MINMAX.fields.0 13762 {"bits": [16, 31], "name": "MAX_SIZE"} array in object:register_types.PA_SU_POINT_MINMAX.fields.1 13767 {"bits": [0, 15], "name": "HEIGHT"}, array in object:register_types.PA_SU_POINT_SIZE.fields.0 13768 {"bits": [16, 31], "name": "WIDTH"} array in object:register_types.PA_SU_POINT_SIZE.fields.1 13773 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.0 13774 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.1 13779 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.0 13780 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.1 13781 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.2 13782 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.3 13783 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.4 13784 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.5 13785 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.6 13786 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.7 13787 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.8 13788 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.9 13789 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.10 13794 {"bits": [0, 0], "name": "CULL_FRONT"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.0 13795 {"bits": [1, 1], "name": "CULL_BACK"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.1 13796 {"bits": [2, 2], "name": "FACE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.2 13797 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.3 13798 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ array in object:register_types.PA_SU_SC_MODE_CNTL.fields.4 13799 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE array in object:register_types.PA_SU_SC_MODE_CNTL.fields.5 13800 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.6 13801 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.7 13802 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.8 13803 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.9 13804 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.10 13805 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.11 13806 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.12 13807 {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.13 13808 {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.14 13809 {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"} array in object:register_types.PA_SU_SC_MODE_CNTL.fields.15 13814 {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.0 13815 {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.1 13816 {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.2 13817 {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.3 13818 {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"} array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.4 13823 {"bits": [0, 0], "name": "PIX_CENTER"}, array in object:register_types.PA_SU_VTX_CNTL.fields.0 13824 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, array in object:register_types.PA_SU_VTX_CNTL.fields.1 13825 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} array in object:register_types.PA_SU_VTX_CNTL.fields.2 13830 {"bits": [0, 3], "name": "FEATURE_SEL"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.0 13831 {"bits": [4, 7], "name": "SE_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.1 13832 {"bits": [8, 11], "name": "SA_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.2 13833 {"bits": [12, 15], "name": "WGP_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.3 13834 {"bits": [16, 17], "name": "EVENT_SEL"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.4 13835 {"bits": [18, 19], "name": "UNUSED"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.5 13836 {"bits": [20, 20], "name": "ENABLE"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.6 13837 {"bits": [21, 31], "name": "RESERVED"} array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.7 13842 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.0 13843 {"bits": [1, 1], "name": "MODE_SELECT"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.1 13844 {"bits": [2, 2], "name": "RESET"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.2 13845 {"bits": [3, 31], "name": "RESERVED"} array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.3 13850 {"bits": [0, 3], "name": "VFID"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.0 13851 {"bits": [4, 5], "name": "CNT_ID"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.1 13852 {"bits": [6, 31], "name": "RESERVED"} array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.2 13857 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"} array in object:register_types.RLC_PERFCOUNTER0_SELECT.fields.0 13862 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"} array in object:register_types.RLC_PERFMON_CLK_CNTL.fields.0 13867 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.RLC_PERFMON_CNTL.fields.0 13868 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.RLC_PERFMON_CNTL.fields.1 13873 {"bits": [0, 0], "name": "StrobeResetPerfMonitors"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.0 13874 {"bits": [1, 1], "name": "StrobeStartAccumulation"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.1 13875 {"bits": [2, 2], "name": "StrobeRearmAccum"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.2 13876 {"bits": [3, 3], "name": "StrobeResetSpmBlock"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.3 13877 {"bits": [4, 7], "name": "StrobeStartSpm"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.4 13878 {"bits": [8, 8], "name": "StrobeRearmSwaAccum"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.5 13879 {"bits": [9, 9], "name": "StrobeStartSwa"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.6 13880 {"bits": [10, 10], "name": "StrobePerfmonSampleWires"}, array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.7 13881 {"bits": [11, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_CTRL.fields.8 13886 {"bits": [0, 10], "name": "addr"}, array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR.fields.0 13887 {"bits": [11, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR.fields.1 13892 {"bits": [0, 7], "name": "global_offset"}, array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET.fields.0 13893 {"bits": [8, 15], "name": "spmwithaccum_se_offset"}, array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET.fields.1 13894 {"bits": [16, 23], "name": "spmwithaccum_global_offset"}, array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET.fields.2 13895 {"bits": [24, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET.fields.3 13900 {"bits": [0, 7], "name": "data"}, array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_DATA.fields.0 13901 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_CTRLRAM_DATA.fields.1 13906 {"bits": [0, 7], "name": "spp_addr_region"}, array in object:register_types.RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS.fields.0 13907 {"bits": [8, 15], "name": "swa_addr_region"}, array in object:register_types.RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS.fields.1 13908 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS.fields.2 13913 {"bits": [0, 6], "name": "addr"}, array in object:register_types.RLC_SPM_ACCUM_DATARAM_ADDR.fields.0 13914 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_DATARAM_ADDR.fields.1 13919 {"bits": [0, 18], "name": "DataRamWrCount"}, array in object:register_types.RLC_SPM_ACCUM_DATARAM_WRCOUNT.fields.0 13920 {"bits": [19, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_DATARAM_WRCOUNT.fields.1 13925 {"bits": [0, 0], "name": "EnableAccum"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.0 13926 {"bits": [1, 1], "name": "EnableSpmWithAccumMode"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.1 13927 {"bits": [2, 2], "name": "EnableSPPMode"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.2 13928 {"bits": [3, 3], "name": "AutoResetPerfmonDisable"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.3 13929 {"bits": [4, 4], "name": "SwaAutoResetPerfmonDisable"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.4 13930 {"bits": [5, 5], "name": "AutoAccumEn"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.5 13931 {"bits": [6, 6], "name": "SwaAutoAccumEn"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.6 13932 {"bits": [7, 7], "name": "AutoSpmEn"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.7 13933 {"bits": [8, 8], "name": "SwaAutoSpmEn"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.8 13934 {"bits": [9, 9], "name": "Globals_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.9 13935 {"bits": [10, 10], "name": "Globals_SwaLoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.10 13936 {"bits": [11, 11], "name": "SE0_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.11 13937 {"bits": [12, 12], "name": "SE0_SwaLoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.12 13938 {"bits": [13, 13], "name": "SE1_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.13 13939 {"bits": [14, 14], "name": "SE1_SwaLoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.14 13940 {"bits": [15, 15], "name": "SE2_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.15 13941 {"bits": [16, 16], "name": "SE2_SwaLoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.16 13942 {"bits": [17, 17], "name": "SE3_LoadOverride"}, array in object:register_types.RLC_SPM_ACCUM_MODE.fields.17 13943 {"bits": [18, 18], "name": "SE3_SwaLoadOverride"} array in object:register_types.RLC_SPM_ACCUM_MODE.fields.18 13948 {"bits": [0, 7], "name": "SamplesRequested"} array in object:register_types.RLC_SPM_ACCUM_SAMPLES_REQUESTED.fields.0 13953 {"bits": [0, 7], "name": "NumbSamplesCompleted"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.0 13954 {"bits": [8, 8], "name": "AccumDone"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.1 13955 {"bits": [9, 9], "name": "SpmDone"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.2 13956 {"bits": [10, 10], "name": "AccumOverflow"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.3 13957 {"bits": [11, 11], "name": "AccumArmed"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.4 13958 {"bits": [12, 12], "name": "SequenceInProgress"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.5 13959 {"bits": [13, 13], "name": "FinalSequenceInProgress"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.6 13960 {"bits": [14, 14], "name": "AllFifosEmpty"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.7 13961 {"bits": [15, 15], "name": "FSMIsIdle"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.8 13962 {"bits": [16, 16], "name": "SwaAccumDone"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.9 13963 {"bits": [17, 17], "name": "SwaSpmDone"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.10 13964 {"bits": [18, 18], "name": "SwaAccumOverflow"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.11 13965 {"bits": [19, 19], "name": "SwaAccumArmed"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.12 13966 {"bits": [20, 20], "name": "AllSegsDone"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.13 13967 {"bits": [21, 21], "name": "RearmSwaPending"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.14 13968 {"bits": [22, 22], "name": "RearmSppPending"}, array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.15 13969 {"bits": [23, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_ACCUM_STATUS.fields.16 13974 {"bits": [0, 15], "name": "Threshold"} array in object:register_types.RLC_SPM_ACCUM_THRESHOLD.fields.0 13979 {"bits": [0, 6], "name": "DESER_START_SKEW"}, array in object:register_types.RLC_SPM_DESER_START_SKEW.fields.0 13980 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_DESER_START_SKEW.fields.1 13985 {"bits": [0, 6], "name": "data"}, array in object:register_types.RLC_SPM_GLB_SAMPLEDELAY_IND_DATA.fields.0 13986 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLB_SAMPLEDELAY_IND_DATA.fields.1 13991 {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"}, array in object:register_types.RLC_SPM_GLOBALS_MUXSEL_SKEW.fields.0 13992 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLOBALS_MUXSEL_SKEW.fields.1 13997 {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"}, array in object:register_types.RLC_SPM_GLOBALS_SAMPLE_SKEW.fields.0 13998 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLOBALS_SAMPLE_SKEW.fields.1 14003 {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"}, array in object:register_types.RLC_SPM_GLOBAL_MUXSEL_ADDR.fields.0 14004 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLOBAL_MUXSEL_ADDR.fields.1 14009 {"bits": [0, 15], "name": "OFFSET"}, array in object:register_types.RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET.fields.0 14010 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET.fields.1 14015 {"bits": [0, 11], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.0 14016 {"bits": [12, 13], "name": "PERFMON_RING_MODE"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.1 14017 {"bits": [14, 15], "name": "RESERVED"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.2 14018 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"} array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.3 14023 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, array in object:register_types.RLC_SPM_PERFMON_GLB_SEGMENT_SIZE.fields.0 14024 {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_GLB_SEGMENT_SIZE.fields.1 14025 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_GLB_SEGMENT_SIZE.fields.2 14030 {"bits": [0, 15], "name": "RING_BASE_HI"}, array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.0 14031 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.1 14036 {"bits": [0, 7], "name": "SE0_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.0 14037 {"bits": [8, 15], "name": "SE1_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.1 14038 {"bits": [16, 23], "name": "SE2_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.2 14039 {"bits": [24, 31], "name": "SE3_NUM_LINE"} array in object:register_types.RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE.fields.3 14044 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.0 14045 {"bits": [8, 10], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.1 14046 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.2 14047 {"bits": [16, 20], "name": "SE0_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.3 14048 {"bits": [21, 25], "name": "SE1_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.4 14049 {"bits": [26, 30], "name": "SE2_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.5 14050 {"bits": [31, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.6 14055 {"bits": [0, 4], "name": "RESERVED"}, array in object:register_types.RLC_SPM_RING_WRPTR.fields.0 14056 {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"} array in object:register_types.RLC_SPM_RING_WRPTR.fields.1 14061 {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"}, array in object:register_types.RLC_SPM_SEGMENT_THRESHOLD.fields.0 14062 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SEGMENT_THRESHOLD.fields.1 14067 {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"}, array in object:register_types.RLC_SPM_SE_MUXSEL_ADDR.fields.0 14068 {"bits": [9, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SE_MUXSEL_ADDR.fields.1 14073 {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"}, array in object:register_types.RLC_SPM_SE_MUXSEL_SKEW.fields.0 14074 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SE_MUXSEL_SKEW.fields.1 14079 {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"}, array in object:register_types.RLC_SPM_SE_SAMPLE_SKEW.fields.0 14080 {"bits": [7, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_SE_SAMPLE_SKEW.fields.1 14085 {"bits": [0, 0], "name": "PauseSpmSamplingRequest"} array in object:register_types.RLC_SPM_VIRT_CTRL.fields.0 14090 {"bits": [0, 0], "name": "SpmSamplingPaused"} array in object:register_types.RLC_SPM_VIRT_STATUS.fields.0 14095 {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.0 14096 {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.1 14097 {"bits": [4, 5], "name": "TC_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.2 14098 {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.3 14099 {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.4 14100 {"bits": [10, 13], "name": "PERF_COUNTER_CID"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.5 14101 {"bits": [14, 18], "name": "PERF_COUNTER_VMID"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.6 14102 {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.7 14103 {"bits": [25, 25], "name": "PERF_SOFT_RESET"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.8 14104 {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"} array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.9 14109 {"bits": [0, 23], "name": "IMMED"}, array in object:register_types.SCRATCH_REG_ATOMIC.fields.0 14110 {"bits": [24, 26], "name": "ID"}, array in object:register_types.SCRATCH_REG_ATOMIC.fields.1 14111 {"bits": [27, 27], "name": "reserved27"}, array in object:register_types.SCRATCH_REG_ATOMIC.fields.2 14112 {"bits": [28, 30], "name": "OP"}, array in object:register_types.SCRATCH_REG_ATOMIC.fields.3 14113 {"bits": [31, 31], "name": "reserved31"} array in object:register_types.SCRATCH_REG_ATOMIC.fields.4 14118 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, array in object:register_types.SCRATCH_UMSK.fields.0 14119 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} array in object:register_types.SCRATCH_UMSK.fields.1 14124 {"bits": [0, 15], "name": "CMD_OP"} array in object:register_types.SDMA0_PERFCNT_MISC_CNTL.fields.0 14129 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.0 14130 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.1 14131 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.2 14132 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.3 14133 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, array in object:register_types.SPI_BARYC_CNTL.fields.4 14134 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, array in object:register_types.SPI_BARYC_CNTL.fields.5 14135 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} array in object:register_types.SPI_BARYC_CNTL.fields.6 14140 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, array in object:register_types.SPI_CONFIG_CNTL.fields.0 14141 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, array in object:register_types.SPI_CONFIG_CNTL.fields.1 14142 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.2 14143 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.3 14144 {"bits": [26, 26], "name": "FORCE_HALF_RATE_PC_EXP"}, array in object:register_types.SPI_CONFIG_CNTL.fields.4 14145 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}, array in object:register_types.SPI_CONFIG_CNTL.fields.5 14146 {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"}, array in object:register_types.SPI_CONFIG_CNTL.fields.6 14147 {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"}, array in object:register_types.SPI_CONFIG_CNTL.fields.7 14148 {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"} array in object:register_types.SPI_CONFIG_CNTL.fields.8 14153 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.0 14154 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.1 14155 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.2 14156 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.3 14157 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.4 14158 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.5 14159 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} array in object:register_types.SPI_INTERP_CONTROL_0.fields.6 14164 {"bits": [0, 3], "name": "BIN0_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.0 14165 {"bits": [4, 7], "name": "BIN0_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.1 14166 {"bits": [8, 11], "name": "BIN1_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.2 14167 {"bits": [12, 15], "name": "BIN1_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.3 14168 {"bits": [16, 19], "name": "BIN2_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.4 14169 {"bits": [20, 23], "name": "BIN2_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.5 14170 {"bits": [24, 27], "name": "BIN3_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.6 14171 {"bits": [28, 31], "name": "BIN3_MAX"} array in object:register_types.SPI_PERFCOUNTER_BINS.fields.7 14176 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.0 14177 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.1 14178 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.2 14179 {"bits": [11, 11], "name": "ROTATE_PC_PTR"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.3 14180 {"bits": [13, 16], "name": "CYL_WRAP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.4 14181 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.5 14182 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.6 14183 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.7 14184 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.8 14185 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.9 14186 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.10 14187 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.11 14188 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.12 14193 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.0 14194 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.1 14195 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.2 14196 {"bits": [11, 11], "name": "ROTATE_PC_PTR"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.3 14197 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.4 14198 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.5 14199 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.6 14200 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.7 14201 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.8 14202 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.9 14207 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.0 14208 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.1 14209 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.2 14210 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.3 14211 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.4 14212 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.5 14213 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.6 14214 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.7 14215 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.8 14216 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.9 14217 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.10 14218 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.11 14219 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.12 14220 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.13 14221 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.14 14222 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} array in object:register_types.SPI_PS_INPUT_ENA.fields.15 14227 {"bits": [0, 5], "name": "NUM_INTERP"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.0 14228 {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.1 14229 {"bits": [8, 8], "name": "LATE_PC_DEALLOC"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.2 14230 {"bits": [9, 13], "name": "NUM_PRIM_INTERP"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.3 14231 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.4 14232 {"bits": [15, 15], "name": "PS_W32_EN"} array in object:register_types.SPI_PS_IN_CONTROL.fields.5 14237 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.0 14238 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.1 14239 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.2 14240 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.3 14241 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.4 14242 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.5 14243 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.6 14244 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_COL_FORMAT.fields.7 14249 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_IDX_FORMAT.fields.0 14254 {"bits": [0, 5], "name": "LIMIT"} array in object:register_types.SPI_SHADER_LATE_ALLOC_VS.fields.0 14259 {"bits": [0, 7], "name": "MEM_BASE"} array in object:register_types.SPI_SHADER_PGM_HI_PS.fields.0 14264 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.0 14265 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.1 14266 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.2 14267 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3 14268 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.4 14269 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.5 14270 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.6 14271 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.7 14272 {"bits": [25, 25], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.8 14273 {"bits": [26, 26], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.9 14274 {"bits": [27, 27], "name": "WGP_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.10 14275 {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.11 14276 {"bits": [31, 31], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.12 14281 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.0 14282 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.1 14283 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.2 14284 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3 14285 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.4 14286 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.5 14287 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.6 14288 {"bits": [24, 24], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.7 14289 {"bits": [25, 25], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.8 14290 {"bits": [26, 26], "name": "WGP_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.9 14291 {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.10 14292 {"bits": [30, 30], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.11 14297 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.0 14298 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.1 14299 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.2 14300 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3 14301 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.4 14302 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.5 14303 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.6 14304 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.7 14305 {"bits": [25, 25], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.8 14306 {"bits": [26, 26], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.9 14307 {"bits": [27, 27], "name": "LOAD_PROVOKING_VTX"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.10 14308 {"bits": [29, 29], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.11 14313 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.0 14314 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.1 14315 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.2 14316 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3 14317 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.4 14318 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.5 14319 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.6 14320 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.7 14321 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.8 14322 {"bits": [27, 27], "name": "MEM_ORDERED"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.9 14323 {"bits": [28, 28], "name": "FWD_PROGRESS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.10 14324 {"bits": [31, 31], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.11 14329 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.0 14330 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.1 14331 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.2 14332 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3 14333 {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.4 14334 {"bits": [18, 18], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.5 14335 {"bits": [19, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.6 14336 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.7 14337 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.8 14342 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.0 14343 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.1 14344 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.2 14345 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.3 14346 {"bits": [16, 17], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.4 14347 {"bits": [18, 18], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.5 14348 {"bits": [19, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.6 14349 {"bits": [27, 27], "name": "SKIP_USGPR0"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.7 14350 {"bits": [28, 28], "name": "USER_SGPR_MSB"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.8 14355 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.0 14356 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.1 14357 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.2 14358 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.3 14359 {"bits": [8, 8], "name": "TG_SIZE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.4 14360 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5 14361 {"bits": [18, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.6 14362 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.7 14363 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.8 14368 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.0 14369 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.1 14370 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.2 14371 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.3 14372 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.4 14373 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5 14374 {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.6 14375 {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.7 14376 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.8 14377 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.9 14382 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.0 14383 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.1 14384 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.2 14385 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.3 14386 {"bits": [8, 8], "name": "SO_BASE0_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.4 14387 {"bits": [9, 9], "name": "SO_BASE1_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.5 14388 {"bits": [10, 10], "name": "SO_BASE2_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.6 14389 {"bits": [11, 11], "name": "SO_BASE3_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.7 14390 {"bits": [12, 12], "name": "SO_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.8 14391 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9 14392 {"bits": [22, 22], "name": "PC_BASE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.10 14393 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.11 14394 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.12 14395 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.13 14400 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.0 14401 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.1 14402 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.2 14403 {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"} array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.3 14408 {"bits": [0, 5], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.0 14409 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.1 14410 {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.2 14411 {"bits": [16, 31], "name": "CU_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.3 14416 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.0 14417 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.1 14418 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"} array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.2 14423 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC4_GS.fields.0 14424 {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"} array in object:register_types.SPI_SHADER_PGM_RSRC4_GS.fields.1 14429 {"bits": [0, 15], "name": "CU_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC4_PS.fields.0 14434 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.0 14435 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.1 14436 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.2 14437 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.3 14438 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_POS_FORMAT.fields.4 14443 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.0 14444 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.1 14445 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.2 14446 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.3 14447 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.4 14448 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.5 14449 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"}, array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.6 14450 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"} array in object:register_types.SPI_SHADER_REQ_CTRL_PS.fields.7 14455 {"bits": [0, 6], "name": "CONTRIBUTION"} array in object:register_types.SPI_SHADER_USER_ACCUM_PS_0.fields.0 14460 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_Z_FORMAT.fields.0 14465 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.0 14466 {"bits": [6, 6], "name": "VS_HALF_PACK"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.1 14467 {"bits": [7, 7], "name": "NO_PC_EXPORT"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.2 14468 {"bits": [8, 12], "name": "PRIM_EXPORT_COUNT"} array in object:register_types.SPI_VS_OUT_CONFIG.fields.3 14473 {"bits": [0, 0], "name": "TARGET_INST"}, array in object:register_types.SQC_CACHES.fields.0 14474 {"bits": [1, 1], "name": "TARGET_DATA"}, array in object:register_types.SQC_CACHES.fields.1 14475 {"bits": [2, 2], "name": "INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.2 14476 {"bits": [16, 16], "name": "COMPLETE"}, array in object:register_types.SQC_CACHES.fields.3 14477 {"bits": [17, 18], "name": "L2_WB_POLICY"} array in object:register_types.SQC_CACHES.fields.4 14482 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.0 14483 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.1 14484 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.2 14489 {"bits": [0, 0], "name": "PS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.0 14490 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1 14491 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2 14492 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3 14493 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4 14494 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5 14495 {"bits": [6, 6], "name": "CS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.6 14496 {"bits": [8, 9], "name": "CNTR_RATE"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.7 14497 {"bits": [13, 13], "name": "DISABLE_FLUSH"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.8 14498 {"bits": [14, 14], "name": "DISABLE_ME0PIPE0_PERF"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.9 14499 {"bits": [15, 15], "name": "DISABLE_ME0PIPE1_PERF"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.10 14500 {"bits": [16, 16], "name": "DISABLE_ME1PIPE0_PERF"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.11 14501 {"bits": [17, 17], "name": "DISABLE_ME1PIPE1_PERF"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.12 14502 {"bits": [18, 18], "name": "DISABLE_ME1PIPE2_PERF"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.13 14503 {"bits": [19, 19], "name": "DISABLE_ME1PIPE3_PERF"} array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.14 14508 {"bits": [0, 0], "name": "FORCE_EN"} array in object:register_types.SQ_PERFCOUNTER_CTRL2.fields.0 14513 {"bits": [0, 3], "name": "BASE_HI"}, array in object:register_types.SQ_THREAD_TRACE_BUF0_SIZE.fields.0 14514 {"bits": [8, 29], "name": "SIZE"} array in object:register_types.SQ_THREAD_TRACE_BUF0_SIZE.fields.1 14519 {"bits": [0, 1], "name": "MODE"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.0 14520 {"bits": [2, 2], "name": "ALL_VMID"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.1 14521 {"bits": [3, 3], "name": "CH_PERF_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.2 14522 {"bits": [4, 4], "name": "INTERRUPT_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.3 14523 {"bits": [5, 5], "name": "DOUBLE_BUFFER"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.4 14524 {"bits": [6, 8], "name": "HIWATER"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.5 14525 {"bits": [9, 9], "name": "REG_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.6 14526 {"bits": [10, 10], "name": "SPI_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.7 14527 {"bits": [11, 11], "name": "SQ_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.8 14528 {"bits": [12, 12], "name": "REG_DROP_ON_STALL"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.9 14529 {"bits": [13, 13], "name": "UTIL_TIMER"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.10 14530 {"bits": [14, 15], "name": "WAVESTART_MODE"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.11 14531 {"bits": [16, 17], "name": "RT_FREQ"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.12 14532 {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.13 14533 {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.14 14534 {"bits": [20, 22], "name": "LOWATER_OFFSET"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.15 14535 {"bits": [28, 28], "name": "AUTO_FLUSH_PADDING_DIS"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.16 14536 {"bits": [29, 29], "name": "AUTO_FLUSH_MODE"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.17 14537 {"bits": [30, 30], "name": "CAPTURE_ALL"}, array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.18 14538 {"bits": [31, 31], "name": "DRAW_EVENT_EN"} array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.19 14543 {"bits": [0, 1], "name": "SIMD_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.0 14544 {"bits": [4, 7], "name": "WGP_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.1 14545 {"bits": [9, 9], "name": "SA_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.2 14546 {"bits": [10, 16], "name": "WTYPE_INCLUDE"} array in object:register_types.SQ_THREAD_TRACE_MASK.fields.3 14551 {"bits": [0, 11], "name": "FINISH_PENDING"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.0 14552 {"bits": [12, 23], "name": "FINISH_DONE"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.1 14553 {"bits": [24, 24], "name": "UTC_ERR"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.2 14554 {"bits": [25, 25], "name": "BUSY"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.3 14555 {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.4 14556 {"bits": [27, 27], "name": "EVENT_CNTR_STALL"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.5 14557 {"bits": [28, 31], "name": "OWNER_VMID"} array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.6 14562 {"bits": [0, 0], "name": "BUF0_FULL"}, array in object:register_types.SQ_THREAD_TRACE_STATUS2.fields.0 14563 {"bits": [1, 1], "name": "BUF1_FULL"}, array in object:register_types.SQ_THREAD_TRACE_STATUS2.fields.1 14564 {"bits": [4, 4], "name": "PACKET_LOST_BUF_NO_LOCKDOWN"} array in object:register_types.SQ_THREAD_TRACE_STATUS2.fields.2 14569 {"bits": [0, 10], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0 14570 {"bits": [12, 12], "name": "BOP_EVENTS_TOKEN_INCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.1 14571 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.2 14572 {"bits": [24, 25], "name": "INST_EXCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.3 14573 {"bits": [26, 28], "name": "REG_EXCLUDE"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.4 14574 {"bits": [31, 31], "name": "REG_DETAIL_ALL"} array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.5 14579 {"bits": [0, 28], "name": "OFFSET"}, array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.0 14580 {"bits": [31, 31], "name": "BUFFER_ID"} array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.1 14585 {"bits": [0, 19], "name": "WAVE_SLOT"} array in object:register_types.SQ_WAVE_ACTIVE.fields.0 14590 {"bits": [0, 7], "name": "VGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.0 14591 {"bits": [8, 15], "name": "VGPR_SIZE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.1 14592 {"bits": [16, 23], "name": "SGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.2 14593 {"bits": [24, 27], "name": "SGPR_SIZE"} array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.3 14598 {"bits": [0, 4], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.0 14599 {"bits": [8, 9], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.1 14600 {"bits": [10, 13], "name": "WGP_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.2 14601 {"bits": [16, 16], "name": "SA_ID"}, array in object:register_types.SQ_WAVE_HW_ID1.fields.3 14602 {"bits": [18, 19], "name": "SE_ID"} array in object:register_types.SQ_WAVE_HW_ID1.fields.4 14607 {"bits": [0, 3], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.0 14608 {"bits": [4, 5], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.1 14609 {"bits": [8, 9], "name": "ME_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.2 14610 {"bits": [12, 14], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.3 14611 {"bits": [16, 20], "name": "WG_ID"}, array in object:register_types.SQ_WAVE_HW_ID2.fields.4 14612 {"bits": [24, 27], "name": "VM_ID"} array in object:register_types.SQ_WAVE_HW_ID2.fields.5 14617 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.0 14618 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.1 14619 {"bits": [6, 7], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.2 14620 {"bits": [8, 11], "name": "CU_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.3 14621 {"bits": [12, 12], "name": "SH_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.4 14622 {"bits": [13, 14], "name": "SE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.5 14623 {"bits": [15, 15], "name": "WAVE_ID_MSB"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.6 14624 {"bits": [16, 19], "name": "TG_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.7 14625 {"bits": [20, 23], "name": "VM_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.8 14626 {"bits": [24, 26], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.9 14627 {"bits": [27, 29], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.10 14628 {"bits": [30, 31], "name": "ME_ID"} array in object:register_types.SQ_WAVE_HW_ID_LEGACY.fields.11 14633 {"bits": [24, 24], "name": "WAVE_IDLE"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.0 14634 {"bits": [25, 31], "name": "MISC_CNT"} array in object:register_types.SQ_WAVE_IB_DBG1.fields.1 14639 {"bits": [0, 3], "name": "VM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.0 14640 {"bits": [4, 6], "name": "EXP_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.1 14641 {"bits": [7, 7], "name": "LGKM_CNT_BIT4"}, array in object:register_types.SQ_WAVE_IB_STS.fields.2 14642 {"bits": [8, 11], "name": "LGKM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.3 14643 {"bits": [12, 14], "name": "VALU_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.4 14644 {"bits": [22, 23], "name": "VM_CNT_HI"}, array in object:register_types.SQ_WAVE_IB_STS.fields.5 14645 {"bits": [24, 24], "name": "LGKM_CNT_BIT5"}, array in object:register_types.SQ_WAVE_IB_STS.fields.6 14646 {"bits": [26, 31], "name": "VS_CNT"} array in object:register_types.SQ_WAVE_IB_STS.fields.7 14651 {"bits": [0, 1], "name": "INST_PREFETCH"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.0 14652 {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.1 14653 {"bits": [8, 9], "name": "MEM_ORDER"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.2 14654 {"bits": [10, 10], "name": "FWD_PROGRESS"}, array in object:register_types.SQ_WAVE_IB_STS2.fields.3 14655 {"bits": [11, 11], "name": "WAVE64"} array in object:register_types.SQ_WAVE_IB_STS2.fields.4 14660 {"bits": [0, 8], "name": "LDS_BASE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.0 14661 {"bits": [12, 20], "name": "LDS_SIZE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.1 14662 {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"} array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.2 14667 {"bits": [0, 3], "name": "FP_ROUND"}, array in object:register_types.SQ_WAVE_MODE.fields.0 14668 {"bits": [4, 7], "name": "FP_DENORM"}, array in object:register_types.SQ_WAVE_MODE.fields.1 14669 {"bits": [8, 8], "name": "DX10_CLAMP"}, array in object:register_types.SQ_WAVE_MODE.fields.2 14670 {"bits": [9, 9], "name": "IEEE"}, array in object:register_types.SQ_WAVE_MODE.fields.3 14671 {"bits": [10, 10], "name": "LOD_CLAMPED"}, array in object:register_types.SQ_WAVE_MODE.fields.4 14672 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.5 14673 {"bits": [23, 23], "name": "FP16_OVFL"}, array in object:register_types.SQ_WAVE_MODE.fields.6 14674 {"bits": [27, 27], "name": "DISABLE_PERF"} array in object:register_types.SQ_WAVE_MODE.fields.7 14679 {"bits": [0, 15], "name": "PC_HI"} array in object:register_types.SQ_WAVE_PC_HI.fields.0 14684 {"bits": [0, 0], "name": "POPS_EN"}, array in object:register_types.SQ_WAVE_POPS_PACKER.fields.0 14685 {"bits": [1, 2], "name": "POPS_PACKER_ID"} array in object:register_types.SQ_WAVE_POPS_PACKER.fields.1 14690 {"bits": [0, 1], "name": "DEP_MODE"} array in object:register_types.SQ_WAVE_SCHED_MODE.fields.0 14695 {"bits": [0, 19], "name": "CYCLES"} array in object:register_types.SQ_WAVE_SHADER_CYCLES.fields.0 14700 {"bits": [0, 0], "name": "SCC"}, array in object:register_types.SQ_WAVE_STATUS.fields.0 14701 {"bits": [1, 2], "name": "SPI_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.1 14702 {"bits": [3, 4], "name": "USER_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.2 14703 {"bits": [5, 5], "name": "PRIV"}, array in object:register_types.SQ_WAVE_STATUS.fields.3 14704 {"bits": [6, 6], "name": "TRAP_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.4 14705 {"bits": [7, 7], "name": "TTRACE_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.5 14706 {"bits": [8, 8], "name": "EXPORT_RDY"}, array in object:register_types.SQ_WAVE_STATUS.fields.6 14707 {"bits": [9, 9], "name": "EXECZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.7 14708 {"bits": [10, 10], "name": "VCCZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.8 14709 {"bits": [11, 11], "name": "IN_TG"}, array in object:register_types.SQ_WAVE_STATUS.fields.9 14710 {"bits": [12, 12], "name": "IN_BARRIER"}, array in object:register_types.SQ_WAVE_STATUS.fields.10 14711 {"bits": [13, 13], "name": "HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.11 14712 {"bits": [14, 14], "name": "TRAP"}, array in object:register_types.SQ_WAVE_STATUS.fields.12 14713 {"bits": [15, 15], "name": "TTRACE_SIMD_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.13 14714 {"bits": [16, 16], "name": "VALID"}, array in object:register_types.SQ_WAVE_STATUS.fields.14 14715 {"bits": [17, 17], "name": "ECC_ERR"}, array in object:register_types.SQ_WAVE_STATUS.fields.15 14716 {"bits": [18, 18], "name": "SKIP_EXPORT"}, array in object:register_types.SQ_WAVE_STATUS.fields.16 14717 {"bits": [19, 19], "name": "PERF_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.17 14718 {"bits": [23, 23], "name": "FATAL_HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.18 14719 {"bits": [27, 27], "name": "MUST_EXPORT"} array in object:register_types.SQ_WAVE_STATUS.fields.19 14724 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.0 14725 {"bits": [10, 10], "name": "SAVECTX"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.1 14726 {"bits": [11, 11], "name": "ILLEGAL_INST"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.2 14727 {"bits": [12, 14], "name": "EXCP_HI"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.3 14728 {"bits": [15, 15], "name": "BUFFER_OOB"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.4 14729 {"bits": [16, 19], "name": "EXCP_CYCLE"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.5 14730 {"bits": [20, 23], "name": "EXCP_GROUP_MASK"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.6 14731 {"bits": [24, 24], "name": "EXCP_WAVE64HI"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.7 14732 {"bits": [28, 28], "name": "UTC_ERROR"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.8 14733 {"bits": [29, 31], "name": "DP_RATE"} array in object:register_types.SQ_WAVE_TRAPSTS.fields.9 14738 {"bits": [0, 5], "name": "SRC0"}, array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.0 14739 {"bits": [6, 11], "name": "SRC1"}, array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.1 14740 {"bits": [12, 17], "name": "SRC2"}, array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.2 14741 {"bits": [18, 23], "name": "DST"} array in object:register_types.SQ_WAVE_VGPR_OFFSET.fields.3 14746 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.0 14747 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.1 14748 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.2 14749 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.3 14750 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.4 14751 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.5 14752 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.6 14753 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.7 14754 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.8 14755 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.9 14756 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.10 14757 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.11 14758 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.12 14759 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.13 14760 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.14 14761 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.15 14762 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"} array in object:register_types.SX_BLEND_OPT_CONTROL.fields.16 14767 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.0 14768 {"bits": [4, 7], "name": "MRT1_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.1 14769 {"bits": [8, 11], "name": "MRT2_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.2 14770 {"bits": [12, 15], "name": "MRT3_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.3 14771 {"bits": [16, 19], "name": "MRT4_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.4 14772 {"bits": [20, 23], "name": "MRT5_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.5 14773 {"bits": [24, 27], "name": "MRT6_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.6 14774 {"bits": [28, 31], "name": "MRT7_EPSILON"} array in object:register_types.SX_BLEND_OPT_EPSILON.fields.7 14779 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.0 14780 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.1 14781 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.2 14782 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.3 14783 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.4 14784 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} array in object:register_types.SX_MRT0_BLEND_OPT.fields.5 14789 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.SX_PERFCOUNTER2_SELECT.fields.0 14790 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.SX_PERFCOUNTER2_SELECT.fields.1 14791 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.SX_PERFCOUNTER2_SELECT.fields.2 14796 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.0 14797 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.1 14798 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.2 14799 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.3 14800 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.4 14801 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.5 14802 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.6 14803 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} array in object:register_types.SX_PS_DOWNCONVERT.fields.7 14808 {"bits": [0, 0], "name": "MRT0_FMT_MAPPING_DISABLE"}, array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.0 14809 {"bits": [1, 1], "name": "MRT1_FMT_MAPPING_DISABLE"}, array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.1 14810 {"bits": [2, 2], "name": "MRT2_FMT_MAPPING_DISABLE"}, array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.2 14811 {"bits": [3, 3], "name": "MRT3_FMT_MAPPING_DISABLE"}, array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.3 14812 {"bits": [4, 4], "name": "MRT4_FMT_MAPPING_DISABLE"}, array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.4 14813 {"bits": [5, 5], "name": "MRT5_FMT_MAPPING_DISABLE"}, array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.5 14814 {"bits": [6, 6], "name": "MRT6_FMT_MAPPING_DISABLE"}, array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.6 14815 {"bits": [7, 7], "name": "MRT7_FMT_MAPPING_DISABLE"} array in object:register_types.SX_PS_DOWNCONVERT_CONTROL.fields.7 14820 {"bits": [0, 7], "name": "ADDRESS"} array in object:register_types.TA_BC_BASE_ADDR_HI.fields.0 14825 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.UTCL1_PERFCOUNTER0_SELECT.fields.0 14826 {"bits": [28, 31], "name": "COUNTER_MODE"} array in object:register_types.UTCL1_PERFCOUNTER0_SELECT.fields.1 14831 {"bits": [0, 15], "name": "BASE_ADDR"} array in object:register_types.VGT_DMA_BASE_HI.fields.0 14836 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.0 14837 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.1 14838 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.2 14839 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.3 14840 {"bits": [8, 8], "name": "ATC"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.4 14841 {"bits": [9, 9], "name": "NOT_EOP"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.5 14842 {"bits": [10, 10], "name": "REQ_PATH"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.6 14843 {"bits": [11, 13], "name": "MTYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.7 14844 {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"} array in object:register_types.VGT_DMA_INDEX_TYPE.fields.8 14849 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.0 14850 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.1 14851 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.2 14852 {"bits": [5, 5], "name": "NOT_EOP"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.3 14853 {"bits": [6, 6], "name": "USE_OPAQUE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.4 14854 {"bits": [29, 31], "name": "REG_RT_INDEX"} array in object:register_types.VGT_DRAW_INITIATOR.fields.5 14859 {"bits": [1, 1], "name": "EN_REG_RT_INDEX"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.0 14860 {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.1 14861 {"bits": [4, 4], "name": "EN_DRAW_VP"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.2 14862 {"bits": [6, 6], "name": "EN_VRS_RATE"} array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.3 14867 {"bits": [0, 14], "name": "ITEMSIZE"} array in object:register_types.VGT_ESGS_RING_ITEMSIZE.fields.0 14872 {"bits": [0, 10], "name": "ES_PER_GS"} array in object:register_types.VGT_ES_PER_GS.fields.0 14877 {"bits": [0, 27], "name": "ADDRESS_LOW"} array in object:register_types.VGT_EVENT_ADDRESS_REG.fields.0 14882 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.0 14883 {"bits": [10, 26], "name": "ADDRESS_HI"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.1 14884 {"bits": [27, 27], "name": "EXTENDED_EVENT"} array in object:register_types.VGT_EVENT_INITIATOR.fields.2 14889 {"bits": [0, 3], "name": "DECR"} array in object:register_types.VGT_GROUP_DECR.fields.0 14894 {"bits": [0, 3], "name": "FIRST_DECR"} array in object:register_types.VGT_GROUP_FIRST_DECR.fields.0 14899 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0 14900 {"bits": [14, 14], "name": "RETAIN_ORDER"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.1 14901 {"bits": [15, 15], "name": "RETAIN_QUADS"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.2 14902 {"bits": [16, 18], "name": "PRIM_ORDER"} array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.3 14907 {"bits": [0, 0], "name": "COMP_X_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.0 14908 {"bits": [1, 1], "name": "COMP_Y_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.1 14909 {"bits": [2, 2], "name": "COMP_Z_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.2 14910 {"bits": [3, 3], "name": "COMP_W_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.3 14911 {"bits": [8, 15], "name": "STRIDE"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.4 14912 {"bits": [16, 23], "name": "SHIFT"} array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.5 14917 {"bits": [0, 3], "name": "X_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.0 14918 {"bits": [4, 7], "name": "X_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.1 14919 {"bits": [8, 11], "name": "Y_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.2 14920 {"bits": [12, 15], "name": "Y_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.3 14921 {"bits": [16, 19], "name": "Z_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.4 14922 {"bits": [20, 23], "name": "Z_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.5 14923 {"bits": [24, 27], "name": "W_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.6 14924 {"bits": [28, 31], "name": "W_OFFSET"} array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.7 14929 {"bits": [0, 14], "name": "OFFSET"} array in object:register_types.VGT_GSVS_RING_OFFSET_1.fields.0 14934 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.0 14935 {"bits": [2, 8], "name": "CNT"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.1 14936 {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"} array in object:register_types.VGT_GS_INSTANCE_CNT.fields.2 14941 {"bits": [0, 10], "name": "MAX_VERT_OUT"} array in object:register_types.VGT_GS_MAX_VERT_OUT.fields.0 14946 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, array in object:register_types.VGT_GS_MODE.fields.0 14947 {"bits": [3, 3], "name": "RESERVED_0"}, array in object:register_types.VGT_GS_MODE.fields.1 14948 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, array in object:register_types.VGT_GS_MODE.fields.2 14949 {"bits": [6, 10], "name": "RESERVED_1"}, array in object:register_types.VGT_GS_MODE.fields.3 14950 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, array in object:register_types.VGT_GS_MODE.fields.4 14951 {"bits": [12, 12], "name": "RESERVED_2"}, array in object:register_types.VGT_GS_MODE.fields.5 14952 {"bits": [13, 13], "name": "ES_PASSTHRU"}, array in object:register_types.VGT_GS_MODE.fields.6 14953 {"bits": [14, 14], "name": "COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.7 14954 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.8 14955 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, array in object:register_types.VGT_GS_MODE.fields.9 14956 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, array in object:register_types.VGT_GS_MODE.fields.10 14957 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, array in object:register_types.VGT_GS_MODE.fields.11 14958 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.12 14959 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.13 14960 {"bits": [21, 22], "name": "ONCHIP"} array in object:register_types.VGT_GS_MODE.fields.14 14965 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.0 14966 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.1 14967 {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"} array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.2 14972 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0 14973 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1 14974 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2 14975 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3 14976 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.4 14981 {"bits": [0, 10], "name": "GS_PER_ES"} array in object:register_types.VGT_GS_PER_ES.fields.0 14986 {"bits": [0, 3], "name": "GS_PER_VS"} array in object:register_types.VGT_GS_PER_VS.fields.0 14991 {"bits": [0, 1], "name": "TESS_MODE"} array in object:register_types.VGT_HOS_CNTL.fields.0 14996 {"bits": [0, 7], "name": "REUSE_DEPTH"} array in object:register_types.VGT_HOS_REUSE_DEPTH.fields.0 15001 {"bits": [0, 9], "name": "OFFCHIP_BUFFERING"}, array in object:register_types.VGT_HS_OFFCHIP_PARAM_UMD.fields.0 15002 {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHI array in object:register_types.VGT_HS_OFFCHIP_PARAM_UMD.fields.1 15007 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_INDEX_TYPE.fields.0 15008 {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"} array in object:register_types.VGT_INDEX_TYPE.fields.1 15013 {"bits": [0, 7], "name": "NUM_PATCHES"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.0 15014 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.1 15015 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} array in object:register_types.VGT_LS_HS_CONFIG.fields.2 15020 {"bits": [0, 0], "name": "RESET_EN"}, array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.0 15021 {"bits": [1, 1], "name": "MATCH_ALL_BITS"} array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.1 15026 {"bits": [0, 2], "name": "PATH_SELECT"} array in object:register_types.VGT_OUTPUT_PATH_CNTL.fields.0 15031 {"bits": [0, 6], "name": "DEALLOC_DIST"} array in object:register_types.VGT_OUT_DEALLOC_CNTL.fields.0 15036 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.0 15037 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.1 15038 {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"} array in object:register_types.VGT_PRIMITIVEID_EN.fields.2 15043 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} array in object:register_types.VGT_PRIMITIVE_TYPE.fields.0 15048 {"bits": [0, 0], "name": "REUSE_OFF"} array in object:register_types.VGT_REUSE_OFF.fields.0 15053 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.0 15054 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.1 15055 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.2 15056 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.3 15057 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.4 15058 {"bits": [8, 8], "name": "DYNAMIC_HS"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.5 15059 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.6 15060 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.7 15061 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.8 15062 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.9 15063 {"bits": [13, 13], "name": "PRIMGEN_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.10 15064 {"bits": [14, 14], "name": "ORDERED_ID_MODE"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.11 15065 {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.12 15066 {"bits": [19, 20], "name": "GS_FAST_LAUNCH"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.13 15067 {"bits": [21, 21], "name": "HS_W32_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.14 15068 {"bits": [22, 22], "name": "GS_W32_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.15 15069 {"bits": [23, 23], "name": "VS_W32_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.16 15070 {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.17 15071 {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.18 15072 {"bits": [26, 26], "name": "PRIMGEN_PASSTHRU_NO_MSG"} array in object:register_types.VGT_SHADER_STAGES_EN.fields.19 15077 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.0 15078 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.1 15079 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.2 15080 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.3 15085 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.0 15086 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.1 15087 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.2 15088 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.3 15089 {"bits": [4, 6], "name": "RAST_STREAM"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.4 15090 {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.5 15091 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.6 15092 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} array in object:register_types.VGT_STRMOUT_CONFIG.fields.7 15097 {"bits": [0, 8], "name": "VERTEX_STRIDE"} array in object:register_types.VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE.fields.0 15102 {"bits": [0, 9], "name": "STRIDE"} array in object:register_types.VGT_STRMOUT_VTX_STRIDE_0.fields.0 15107 {"bits": [0, 7], "name": "ACCUM_ISOLINE"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.0 15108 {"bits": [8, 15], "name": "ACCUM_TRI"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.1 15109 {"bits": [16, 23], "name": "ACCUM_QUAD"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.2 15110 {"bits": [24, 28], "name": "DONUT_SPLIT"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.3 15111 {"bits": [29, 31], "name": "TRAP_SPLIT"} array in object:register_types.VGT_TESS_DISTRIBUTION.fields.4 15116 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, array in object:register_types.VGT_TF_PARAM.fields.0 15117 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, array in object:register_types.VGT_TF_PARAM.fields.1 15118 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, array in object:register_types.VGT_TF_PARAM.fields.2 15119 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, array in object:register_types.VGT_TF_PARAM.fields.3 15120 {"bits": [9, 9], "name": "DEPRECATED"}, array in object:register_types.VGT_TF_PARAM.fields.4 15121 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, array in object:register_types.VGT_TF_PARAM.fields.5 15122 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, array in object:register_types.VGT_TF_PARAM.fields.6 15123 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_TF_PARAM.fields.7 15124 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, array in object:register_types.VGT_TF_PARAM.fields.8 15125 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"}, array in object:register_types.VGT_TF_PARAM.fields.9 15126 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"}, array in object:register_types.VGT_TF_PARAM.fields.10 15127 {"bits": [23, 25], "name": "MTYPE"} array in object:register_types.VGT_TF_PARAM.fields.11 15132 {"bits": [0, 15], "name": "SIZE"} array in object:register_types.VGT_TF_RING_SIZE_UMD.fields.0 15137 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} array in object:register_types.VGT_VERTEX_REUSE_BLOCK_CNTL.fields.0 15142 {"bits": [0, 0], "name": "VTX_CNT_EN"} array in object:register_types.VGT_VTX_CNT_EN.fields.0 [all...]
H A D	gfx7.json	9066 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.0 9067 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.1 9068 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.2 9069 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.3 9070 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.4 9071 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.5 9072 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.6 9073 {"bits": [30, 30], "name": "ENABLE"}, array in object:register_types.CB_BLEND0_CONTROL.fields.7 9074 {"bits": [31, 31], "name": "DISABLE_ROP3"} array in object:register_types.CB_BLEND0_CONTROL.fields.8 9079 {"bits" array in object:register_types.CB_COLOR0_ATTRIB.fields.0 9080 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.1 9081 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.2 9082 {"bits": [12, 14], "name": "NUM_SAMPLES"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.3 9083 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.4 9084 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"} array in object:register_types.CB_COLOR0_ATTRIB.fields.5 9089 {"bits": [0, 13], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_CMASK_SLICE.fields.0 9094 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, array in object:register_types.CB_COLOR0_INFO.fields.0 9095 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, array in object:register_types.CB_COLOR0_INFO.fields.1 9096 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, array in object:register_types.CB_COLOR0_INFO.fields.2 9097 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.3 9098 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, array in object:register_types.CB_COLOR0_INFO.fields.4 9099 {"bits": [13, 13], "name": "FAST_CLEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.5 9100 {"bits": [14, 14], "name": "COMPRESSION"}, array in object:register_types.CB_COLOR0_INFO.fields.6 9101 {"bits": [15, 15], "name": "BLEND_CLAMP"}, array in object:register_types.CB_COLOR0_INFO.fields.7 9102 {"bits": [16, 16], "name": "BLEND_BYPASS"}, array in object:register_types.CB_COLOR0_INFO.fields.8 9103 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, array in object:register_types.CB_COLOR0_INFO.fields.9 9104 {"bits": [18, 18], "name": "ROUND_MODE"}, array in object:register_types.CB_COLOR0_INFO.fields.10 9105 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.11 9106 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, array in object:register_types.CB_COLOR0_INFO.fields.12 9107 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, array in object:register_types.CB_COLOR0_INFO.fields.13 9108 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"} array in object:register_types.CB_COLOR0_INFO.fields.14 9113 {"bits": [0, 10], "name": "TILE_MAX"}, array in object:register_types.CB_COLOR0_PITCH.fields.0 9114 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} array in object:register_types.CB_COLOR0_PITCH.fields.1 9119 {"bits": [0, 21], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_SLICE.fields.0 9124 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.CB_COLOR0_VIEW.fields.0 9125 {"bits": [13, 23], "name": "SLICE_MAX"} array in object:register_types.CB_COLOR0_VIEW.fields.1 9130 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, array in object:register_types.CB_COLOR_CONTROL.fields.0 9131 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, array in object:register_types.CB_COLOR_CONTROL.fields.1 9132 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} array in object:register_types.CB_COLOR_CONTROL.fields.2 9137 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.0 9138 {"bits": [10, 18], "name": "PERF_SEL1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.1 9139 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.2 9140 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.3 9141 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.4 9146 {"bits": [0, 8], "name": "PERF_SEL2"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.0 9147 {"bits": [10, 18], "name": "PERF_SEL3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.1 9148 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.2 9149 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.3 9154 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.0 9155 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.1 9160 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.0 9161 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.1 9162 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.2 9163 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.3 9164 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.4 9165 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.5 9166 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.6 9167 {"bits": [13, 15], "name": "MRT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.7 9168 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.8 9169 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.9 9170 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.10 9171 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"} array in object:register_types.CB_PERFCOUNTER_FILTER.fields.11 9176 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.0 9177 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.1 9178 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.2 9179 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.3 9180 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.4 9181 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.5 9182 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.6 9183 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} array in object:register_types.CB_SHADER_MASK.fields.7 9188 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.0 9189 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.1 9190 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.2 9191 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.3 9192 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.4 9193 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.5 9194 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.6 9195 {"bits": [28, 31], "name": "TARGET7_ENABLE"} array in object:register_types.CB_TARGET_MASK.fields.7 9200 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.0 9201 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.1 9202 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.2 9203 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.3 9204 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.4 9205 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.5 9206 {"bits": [6, 6], "name": "ORDER_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.6 9207 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.7 9208 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.8 9209 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.9 9210 {"bits": [12, 12], "name": "DATA_ATC"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.10 9211 {"bits": [14, 14], "name": "RESTORE"} array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.11 9216 {"bits": [0, 1], "name": "SEND_SEID"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.0 9217 {"bits": [2, 2], "name": "RESERVED2"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.1 9218 {"bits": [3, 3], "name": "RESERVED3"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.2 9219 {"bits": [4, 4], "name": "RESERVED4"} array in object:register_types.COMPUTE_MISC_RESERVED.fields.3 9224 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, array in object:register_types.COMPUTE_NUM_THREAD_X.fields.0 9225 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} array in object:register_types.COMPUTE_NUM_THREAD_X.fields.1 9230 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"} array in object:register_types.COMPUTE_PERFCOUNT_ENABLE.fields.0 9235 {"bits": [0, 7], "name": "DATA"}, array in object:register_types.COMPUTE_PGM_HI.fields.0 9236 {"bits": [8, 8], "name": "INST_ATC"} array in object:register_types.COMPUTE_PGM_HI.fields.1 9241 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.0 9242 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.1 9243 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.2 9244 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.3 9245 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.4 9246 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.5 9247 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.6 9248 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.7 9249 {"bits": [24, 24], "name": "BULKY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.8 9250 {"bits": [25, 25], "name": "CDBG_USER"} array in object:register_types.COMPUTE_PGM_RSRC1.fields.9 9255 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.0 9256 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.1 9257 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.2 9258 {"bits": [7, 7], "name": "TGID_X_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.3 9259 {"bits": [8, 8], "name": "TGID_Y_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.4 9260 {"bits": [9, 9], "name": "TGID_Z_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.5 9261 {"bits": [10, 10], "name": "TG_SIZE_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.6 9262 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.7 9263 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.8 9264 {"bits": [15, 23], "name": "LDS_SIZE"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.9 9265 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.COMPUTE_PGM_RSRC2.fields.10 9270 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"} array in object:register_types.COMPUTE_PIPELINESTAT_ENABLE.fields.0 9275 {"bits": [0, 9], "name": "WAVES_PER_SH"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.0 9276 {"bits": [12, 15], "name": "TG_PER_CU"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.1 9277 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.2 9278 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.3 9279 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.4 9280 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.5 9285 {"bits": [0, 15], "name": "SH0_CU_EN"}, array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.0 9286 {"bits": [16, 31], "name": "SH1_CU_EN"} array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.1 9291 {"bits": [0, 7], "name": "DATA"} array in object:register_types.COMPUTE_TBA_HI.fields.0 9296 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"} array in object:register_types.COMPUTE_THREAD_TRACE_ENABLE.fields.0 9301 {"bits": [0, 11], "name": "WAVES"}, array in object:register_types.COMPUTE_TMPRING_SIZE.fields.0 9302 {"bits": [12, 24], "name": "WAVESIZE"} array in object:register_types.COMPUTE_TMPRING_SIZE.fields.1 9307 {"bits": [0, 3], "name": "DATA"} array in object:register_types.COMPUTE_VMID.fields.0 9312 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT.fields.0 9313 {"bits": [10, 15], "name": "PERF_SEL1"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT.fields.1 9314 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.CPG_PERFCOUNTER0_SELECT.fields.2 9319 {"bits": [0, 5], "name": "PERF_SEL2"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.0 9320 {"bits": [10, 15], "name": "PERF_SEL3"} array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.1 9325 {"bits": [0, 5], "name": "PERF_SEL"} array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.0 9330 {"bits": [0, 15], "name": "MEM_ADDR_HI"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.0 9331 {"bits": [16, 16], "name": "CS_PS_SEL"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.1 9332 {"bits": [29, 31], "name": "COMMAND"} array in object:register_types.CP_APPEND_ADDR_HI.fields.2 9337 {"bits": [2, 31], "name": "MEM_ADDR_LO"} array in object:register_types.CP_APPEND_ADDR_LO.fields.0 9342 {"bits": [0, 15], "name": "IB1_BASE_HI"} array in object:register_types.CP_CE_IB1_BASE_HI.fields.0 9347 {"bits": [2, 31], "name": "IB1_BASE_LO"} array in object:register_types.CP_CE_IB1_BASE_LO.fields.0 9352 {"bits": [0, 19], "name": "IB1_BUFSZ"} array in object:register_types.CP_CE_IB1_BUFSZ.fields.0 9357 {"bits": [0, 15], "name": "IB2_BASE_HI"} array in object:register_types.CP_CE_IB2_BASE_HI.fields.0 9362 {"bits": [2, 31], "name": "IB2_BASE_LO"} array in object:register_types.CP_CE_IB2_BASE_LO.fields.0 9367 {"bits": [0, 19], "name": "IB2_BUFSZ"} array in object:register_types.CP_CE_IB2_BUFSZ.fields.0 9372 {"bits": [0, 15], "name": "INIT_BASE_HI"} array in object:register_types.CP_CE_INIT_BASE_HI.fields.0 9377 {"bits": [5, 31], "name": "INIT_BASE_LO"} array in object:register_types.CP_CE_INIT_BASE_LO.fields.0 9382 {"bits": [0, 11], "name": "INIT_BUFSZ"} array in object:register_types.CP_CE_INIT_BUFSZ.fields.0 9387 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"} array in object:register_types.CP_COHER_BASE_HI.fields.0 9392 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.0 9393 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.1 9394 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.2 9395 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.3 9396 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.4 9397 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.5 9398 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.6 9399 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.7 9400 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.8 9401 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.9 9402 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.10 9403 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.11 9404 {"bits": [16, 16], "name": "TC_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.12 9405 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.13 9406 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.14 9407 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.15 9408 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.16 9409 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.17 9410 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.18 9411 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.19 9412 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.20 9413 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.21 9414 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"} array in object:register_types.CP_COHER_CNTL.fields.22 9419 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"} array in object:register_types.CP_COHER_SIZE_HI.fields.0 9424 {"bits": [0, 5], "name": "START_DELAY_COUNT"} array in object:register_types.CP_COHER_START_DELAY.fields.0 9429 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, array in object:register_types.CP_COHER_STATUS.fields.0 9430 {"bits": [24, 25], "name": "MEID"}, array in object:register_types.CP_COHER_STATUS.fields.1 9431 {"bits": [30, 30], "name": "PHASE1_STATUS"}, array in object:register_types.CP_COHER_STATUS.fields.2 9432 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_COHER_STATUS.fields.3 9437 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.0 9438 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.1 9439 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.2 9440 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.3 9441 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.4 9442 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.5 9443 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.6 9444 {"bits": [7, 7], "name": "MEC1_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.7 9445 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.8 9446 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.9 9447 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.10 9448 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.11 9449 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.12 9450 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.13 9451 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.14 9452 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.15 9453 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.16 9454 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.17 9455 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.18 9456 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.19 9457 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.20 9458 {"bits": [23, 23], "name": "MEC2_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.21 9459 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.22 9460 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.23 9461 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.24 9462 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.25 9463 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.26 9464 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"} array in object:register_types.CP_CPC_BUSY_STAT.fields.27 9469 {"bits": [0, 5], "name": "FREE_COUNT"} array in object:register_types.CP_CPC_GRBM_FREE_COUNT.fields.0 9474 {"bits": [0, 3], "name": "COUNT"} array in object:register_types.CP_CPC_HALT_HYST_COUNT.fields.0 9479 {"bits": [0, 4], "name": "PACK_DELAY_CNT"} array in object:register_types.CP_CPC_MC_CNTL.fields.0 9484 {"bits": [0, 7], "name": "SCRATCH_INDEX"} array in object:register_types.CP_CPC_SCRATCH_INDEX.fields.0 9489 {"bits": [0, 0], "name": "MIU_RDREQ_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.0 9490 {"bits": [1, 1], "name": "MIU_WRREQ_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.1 9491 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.2 9492 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.3 9493 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.4 9494 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.5 9495 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.6 9496 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.7 9497 {"bits": [11, 11], "name": "MEC1_WAIT_ON_MC_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.8 9498 {"bits": [12, 12], "name": "MEC1_WAIT_ON_MC_WR_ACK"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.9 9499 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.10 9500 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.11 9501 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.12 9502 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.13 9503 {"bits": [19, 19], "name": "MEC2_WAIT_ON_MC_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.14 9504 {"bits": [20, 20], "name": "MEC2_WAIT_ON_MC_WR_ACK"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.15 9505 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"} array in object:register_types.CP_CPC_STALLED_STAT1.fields.16 9510 {"bits": [0, 0], "name": "MEC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.0 9511 {"bits": [1, 1], "name": "MEC2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.1 9512 {"bits": [2, 2], "name": "DC0_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.2 9513 {"bits": [3, 3], "name": "DC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.3 9514 {"bits": [4, 4], "name": "RCIU1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.4 9515 {"bits": [5, 5], "name": "RCIU2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.5 9516 {"bits": [6, 6], "name": "ROQ1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.6 9517 {"bits": [7, 7], "name": "ROQ2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.7 9518 {"bits": [8, 8], "name": "MIU_RDREQ_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.8 9519 {"bits": [9, 9], "name": "MIU_WRREQ_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.9 9520 {"bits": [10, 10], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.10 9521 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.11 9522 {"bits": [12, 12], "name": "QU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.12 9523 {"bits": [29, 29], "name": "CPG_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.13 9524 {"bits": [30, 30], "name": "CPF_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.14 9525 {"bits": [31, 31], "name": "CPC_BUSY"} array in object:register_types.CP_CPC_STATUS.fields.15 9530 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.0 9531 {"bits": [1, 1], "name": "CSF_RING_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.1 9532 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.2 9533 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.3 9534 {"bits": [4, 4], "name": "CSF_STATE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.4 9535 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.5 9536 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.6 9537 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.7 9538 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.8 9539 {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.9 9540 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.10 9541 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.11 9542 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.12 9543 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.13 9544 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.14 9545 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.15 9546 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.16 9547 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.17 9548 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.18 9549 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.19 9550 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.20 9551 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.21 9552 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.22 9553 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.23 9554 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.24 9555 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.25 9556 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.26 9557 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.27 9558 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.28 9559 {"bits": [30, 30], "name": "HQD_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.29 9560 {"bits": [31, 31], "name": "HQD_IB_BUSY"} array in object:register_types.CP_CPF_BUSY_STAT.fields.30 9565 {"bits": [0, 0], "name": "RING_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.0 9566 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.1 9567 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.2 9568 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.3 9569 {"bits": [4, 4], "name": "MIU_WAITING_ON_RDREQ_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.4 9570 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.5 9571 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"} array in object:register_types.CP_CPF_STALLED_STAT1.fields.6 9576 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.0 9577 {"bits": [1, 1], "name": "CSF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.1 9578 {"bits": [2, 2], "name": "MIU_RDREQ_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.2 9579 {"bits": [3, 3], "name": "MIU_WRREQ_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.3 9580 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.4 9581 {"bits": [5, 5], "name": "ROQ_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.5 9582 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.6 9583 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.7 9584 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.8 9585 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.9 9586 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.10 9587 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.11 9588 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.12 9589 {"bits": [13, 13], "name": "INTERRUPT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.13 9590 {"bits": [14, 14], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.14 9591 {"bits": [15, 15], "name": "HQD_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.15 9592 {"bits": [30, 30], "name": "CPC_CPF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.16 9593 {"bits": [31, 31], "name": "CPF_BUSY"} array in object:register_types.CP_CPF_STATUS.fields.17 9598 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, array in object:register_types.CP_DMA_CNTL.fields.0 9599 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, array in object:register_types.CP_DMA_CNTL.fields.1 9600 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, array in object:register_types.CP_DMA_CNTL.fields.2 9601 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, array in object:register_types.CP_DMA_CNTL.fields.3 9602 {"bits": [30, 31], "name": "PIO_COUNT"} array in object:register_types.CP_DMA_CNTL.fields.4 9607 {"bits": [0, 20], "name": "BYTE_COUNT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.0 9608 {"bits": [21, 21], "name": "DIS_WC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.1 9609 {"bits": [22, 23], "name": "SRC_SWAP"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.2 9610 {"bits": [24, 25], "name": "DST_SWAP"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.3 9611 {"bits": [26, 26], "name": "SAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.4 9612 {"bits": [27, 27], "name": "DAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.5 9613 {"bits": [28, 28], "name": "SAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.6 9614 {"bits": [29, 29], "name": "DAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.7 9615 {"bits": [30, 30], "name": "RAW_WAIT"} array in object:register_types.CP_DMA_ME_COMMAND.fields.8 9620 {"bits": [12, 12], "name": "SRC_ATC"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.0 9621 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.1 9622 {"bits": [15, 15], "name": "SRC_VOLATILE"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.2 9623 {"bits": [20, 21], "name": "DST_SELECT"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.3 9624 {"bits": [24, 24], "name": "DST_ATC"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.4 9625 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.5 9626 {"bits": [27, 27], "name": "DST_VOLATILE"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.6 9627 {"bits": [29, 30], "name": "SRC_SELECT"} array in object:register_types.CP_DMA_ME_CONTROL.fields.7 9632 {"bits": [0, 15], "name": "DST_ADDR_HI"} array in object:register_types.CP_DMA_ME_DST_ADDR_HI.fields.0 9637 {"bits": [0, 15], "name": "SRC_ADDR_HI"} array in object:register_types.CP_DMA_ME_SRC_ADDR_HI.fields.0 9642 {"bits": [0, 25], "name": "DMA_READ_TAG"}, array in object:register_types.CP_DMA_READ_TAGS.fields.0 9643 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} array in object:register_types.CP_DMA_READ_TAGS.fields.1 9648 {"bits": [0, 15], "name": "COUNT"} array in object:register_types.CP_DRAW_OBJECT_COUNTER.fields.0 9653 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.0 9654 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.1 9655 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.2 9656 {"bits": [8, 8], "name": "MODE"} array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.3 9661 {"bits": [0, 15], "name": "MIN"}, array in object:register_types.CP_DRAW_WINDOW_LO.fields.0 9662 {"bits": [16, 31], "name": "MAX"} array in object:register_types.CP_DRAW_WINDOW_LO.fields.1 9667 {"bits": [0, 15], "name": "ADDR_HI"} array in object:register_types.CP_EOP_DONE_ADDR_HI.fields.0 9672 {"bits": [0, 1], "name": "ADDR_SWAP"}, array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.0 9673 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.1 9678 {"bits": [0, 15], "name": "CNTX_ID"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.0 9679 {"bits": [16, 17], "name": "DST_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.1 9680 {"bits": [24, 26], "name": "INT_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.2 9681 {"bits": [29, 31], "name": "DATA_SEL"} array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.3 9686 {"bits": [0, 6], "name": "WBINV_TC_OP"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.0 9687 {"bits": [12, 17], "name": "WBINV_ACTION_ENA"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.1 9688 {"bits": [25, 26], "name": "CACHE_CONTROL"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.2 9689 {"bits": [27, 27], "name": "EOP_VOLATILE"} array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.3 9694 {"bits": [0, 19], "name": "IB1_OFFSET"} array in object:register_types.CP_IB1_OFFSET.fields.0 9699 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} array in object:register_types.CP_IB1_PREAMBLE_BEGIN.fields.0 9704 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} array in object:register_types.CP_IB1_PREAMBLE_END.fields.0 9709 {"bits": [0, 19], "name": "IB2_OFFSET"} array in object:register_types.CP_IB2_OFFSET.fields.0 9714 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} array in object:register_types.CP_IB2_PREAMBLE_BEGIN.fields.0 9719 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} array in object:register_types.CP_IB2_PREAMBLE_END.fields.0 9724 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"} array in object:register_types.CP_ME_MC_RADDR_HI.fields.0 9729 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"}, array in object:register_types.CP_ME_MC_RADDR_LO.fields.0 9730 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} array in object:register_types.CP_ME_MC_RADDR_LO.fields.1 9735 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"} array in object:register_types.CP_ME_MC_WADDR_HI.fields.0 9740 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"}, array in object:register_types.CP_ME_MC_WADDR_LO.fields.0 9741 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} array in object:register_types.CP_ME_MC_WADDR_LO.fields.1 9746 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.0 9747 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.1 9748 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, array in object:register_types.CP_PERFMON_CNTL.fields.2 9749 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.CP_PERFMON_CNTL.fields.3 9754 {"bits": [31, 31], "name": "PERFMON_ENABLE"} array in object:register_types.CP_PERFMON_CNTX_CNTL.fields.0 9759 {"bits": [0, 7], "name": "IB_EN"} array in object:register_types.CP_PFP_IB_CONTROL.fields.0 9764 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.0 9765 {"bits": [1, 1], "name": "CNTX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.1 9766 {"bits": [15, 15], "name": "UCONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.2 9767 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.3 9768 {"bits": [24, 24], "name": "SH_CS_REG_EN"} array in object:register_types.CP_PFP_LOAD_CONTROL.fields.4 9773 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"} array in object:register_types.CP_PIPE_STATS_ADDR_HI.fields.0 9778 {"bits": [0, 1], "name": "PIPE_STATS_ADDR_SWAP"}, array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.0 9779 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.1 9784 {"bits": [0, 19], "name": "RB_OFFSET"} array in object:register_types.CP_RB_OFFSET.fields.0 9789 {"bits": [0, 1], "name": "RINGID"} array in object:register_types.CP_RINGID.fields.0 9794 {"bits": [0, 15], "name": "SEM_ADDR_HI"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.0 9795 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.1 9796 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.2 9797 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.3 9798 {"bits": [29, 31], "name": "SEM_SELECT"} array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.4 9803 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.0 9804 {"bits": [3, 31], "name": "SEM_ADDR_LO"} array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.1 9809 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"} array in object:register_types.CP_STREAM_OUT_ADDR_HI.fields.0 9814 {"bits": [0, 1], "name": "STREAM_OUT_ADDR_SWAP"}, array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.0 9815 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.1 9820 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} array in object:register_types.CP_STRMOUT_CNTL.fields.0 9825 {"bits": [0, 15], "name": "ST_BASE_HI"} array in object:register_types.CP_ST_BASE_HI.fields.0 9830 {"bits": [2, 31], "name": "ST_BASE_LO"} array in object:register_types.CP_ST_BASE_LO.fields.0 9835 {"bits": [0, 19], "name": "ST_BUFSZ"} array in object:register_types.CP_ST_BUFSZ.fields.0 9840 {"bits": [0, 3], "name": "VMID"} array in object:register_types.CP_VMID.fields.0 9845 {"bits": [0, 2], "name": "SRC_STATE_ID"} array in object:register_types.CS_COPY_STATE.fields.0 9850 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.0 9851 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.1 9852 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.2 9853 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.3 9854 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.4 9855 {"bits": [16, 16], "name": "OFFSET_ROUND"} array in object:register_types.DB_ALPHA_TO_MASK.fields.5 9860 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.0 9861 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.1 9862 {"bits": [4, 6], "name": "SAMPLE_RATE"}, array in object:register_types.DB_COUNT_CONTROL.fields.2 9863 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.3 9864 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.4 9865 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.5 9866 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.6 9867 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.7 9868 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} array in object:register_types.DB_COUNT_CONTROL.fields.8 9873 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.0 9874 {"bits": [1, 1], "name": "Z_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.1 9875 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.2 9876 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.3 9877 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.4 9878 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.5 9879 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.6 9880 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, array in object:register_types.DB_DEPTH_CONTROL.fields.7 9881 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, array in object:register_types.DB_DEPTH_CONTROL.fields.8 9882 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} array in object:register_types.DB_DEPTH_CONTROL.fields.9 9887 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"}, array in object:register_types.DB_DEPTH_INFO.fields.0 9888 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.DB_DEPTH_INFO.fields.1 9889 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.DB_DEPTH_INFO.fields.2 9890 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, array in object:register_types.DB_DEPTH_INFO.fields.3 9891 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, array in object:register_types.DB_DEPTH_INFO.fields.4 9892 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, array in object:register_types.DB_DEPTH_INFO.fields.5 9893 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} array in object:register_types.DB_DEPTH_INFO.fields.6 9898 {"bits": [0, 10], "name": "PITCH_TILE_MAX"}, array in object:register_types.DB_DEPTH_SIZE.fields.0 9899 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"} array in object:register_types.DB_DEPTH_SIZE.fields.1 9904 {"bits": [0, 21], "name": "SLICE_TILE_MAX"} array in object:register_types.DB_DEPTH_SLICE.fields.0 9909 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.DB_DEPTH_VIEW.fields.0 9910 {"bits": [13, 23], "name": "SLICE_MAX"}, array in object:register_types.DB_DEPTH_VIEW.fields.1 9911 {"bits": [24, 24], "name": "Z_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.2 9912 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"} array in object:register_types.DB_DEPTH_VIEW.fields.3 9917 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, array in object:register_types.DB_EQAA.fields.0 9918 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, array in object:register_types.DB_EQAA.fields.1 9919 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.2 9920 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.3 9921 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, array in object:register_types.DB_EQAA.fields.4 9922 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, array in object:register_types.DB_EQAA.fields.5 9923 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, array in object:register_types.DB_EQAA.fields.6 9924 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, array in object:register_types.DB_EQAA.fields.7 9925 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, array in object:register_types.DB_EQAA.fields.8 9926 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, array in object:register_types.DB_EQAA.fields.9 9927 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, array in object:register_types.DB_EQAA.fields.10 9928 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} array in object:register_types.DB_EQAA.fields.11 9933 {"bits": [0, 0], "name": "LINEAR"}, array in object:register_types.DB_HTILE_SURFACE.fields.0 9934 {"bits": [1, 1], "name": "FULL_CACHE"}, array in object:register_types.DB_HTILE_SURFACE.fields.1 9935 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, array in object:register_types.DB_HTILE_SURFACE.fields.2 9936 {"bits": [3, 3], "name": "PRELOAD"}, array in object:register_types.DB_HTILE_SURFACE.fields.3 9937 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, array in object:register_types.DB_HTILE_SURFACE.fields.4 9938 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, array in object:register_types.DB_HTILE_SURFACE.fields.5 9939 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"} array in object:register_types.DB_HTILE_SURFACE.fields.6 9944 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.0 9945 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.1 9946 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.2 9947 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.3 9948 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.4 9953 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.0 9954 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.1 9955 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.2 9956 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.3 9961 {"bits": [0, 7], "name": "START_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.0 9962 {"bits": [8, 15], "name": "START_Y"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.1 9963 {"bits": [16, 23], "name": "MAX_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.2 9964 {"bits": [24, 31], "name": "MAX_Y"} array in object:register_types.DB_PRELOAD_CONTROL.fields.3 9969 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.0 9970 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.1 9971 {"bits": [2, 2], "name": "DEPTH_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.2 9972 {"bits": [3, 3], "name": "STENCIL_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.3 9973 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.4 9974 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.5 9975 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.6 9976 {"bits": [7, 7], "name": "COPY_CENTROID"}, array in object:register_types.DB_RENDER_CONTROL.fields.7 9977 {"bits": [8, 11], "name": "COPY_SAMPLE"} array in object:register_types.DB_RENDER_CONTROL.fields.8 9982 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.0 9983 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.1 9984 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.2 9985 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.3 9986 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.4 9987 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.5 9988 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.6 9989 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.7 9990 {"bits": [11, 11], "name": "FORCE_Z_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.8 9991 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.9 9992 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.10 9993 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.11 9994 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.12 9995 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.13 9996 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.14 9997 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.15 9998 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.16 9999 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.17 10000 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.18 10001 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.19 10002 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.20 10003 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.21 10004 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} array in object:register_types.DB_RENDER_OVERRIDE.fields.22 10009 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.0 10010 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.1 10011 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.2 10012 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.3 10013 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.4 10014 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.5 10015 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.6 10016 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.7 10017 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.8 10018 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.9 10019 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.10 10020 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.11 10021 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.12 10022 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.13 10023 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"} array in object:register_types.DB_RENDER_OVERRIDE2.fields.14 10028 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.0 10029 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.1 10030 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.2 10031 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, array in object:register_types.DB_SHADER_CONTROL.fields.3 10032 {"bits": [6, 6], "name": "KILL_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.4 10033 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.5 10034 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.6 10035 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, array in object:register_types.DB_SHADER_CONTROL.fields.7 10036 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, array in object:register_types.DB_SHADER_CONTROL.fields.8 10037 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.9 10038 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.10 10039 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} array in object:register_types.DB_SHADER_CONTROL.fields.11 10044 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0 10045 {"bits": [4, 11], "name": "COMPAREVALUE0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.1 10046 {"bits": [12, 19], "name": "COMPAREMASK0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.2 10047 {"bits": [24, 24], "name": "ENABLE0"} array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.3 10052 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0 10053 {"bits": [4, 11], "name": "COMPAREVALUE1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.1 10054 {"bits": [12, 19], "name": "COMPAREMASK1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.2 10055 {"bits": [24, 24], "name": "ENABLE1"} array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.3 10060 {"bits": [0, 7], "name": "STENCILTESTVAL"}, array in object:register_types.DB_STENCILREFMASK.fields.0 10061 {"bits": [8, 15], "name": "STENCILMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.1 10062 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.2 10063 {"bits": [24, 31], "name": "STENCILOPVAL"} array in object:register_types.DB_STENCILREFMASK.fields.3 10068 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.0 10069 {"bits": [8, 15], "name": "STENCILMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.1 10070 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.2 10071 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} array in object:register_types.DB_STENCILREFMASK_BF.fields.3 10076 {"bits": [0, 7], "name": "CLEAR"} array in object:register_types.DB_STENCIL_CLEAR.fields.0 10081 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.0 10082 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, array in object:register_types.DB_STENCIL_CONTROL.fields.1 10083 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.2 10084 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.3 10085 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.4 10086 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} array in object:register_types.DB_STENCIL_CONTROL.fields.5 10091 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, array in object:register_types.DB_STENCIL_INFO.fields.0 10092 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.DB_STENCIL_INFO.fields.1 10093 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, array in object:register_types.DB_STENCIL_INFO.fields.2 10094 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_STENCIL_INFO.fields.3 10095 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} array in object:register_types.DB_STENCIL_INFO.fields.4 10100 {"bits": [0, 30], "name": "COUNT_HI"} array in object:register_types.DB_ZPASS_COUNT_HI.fields.0 10105 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, array in object:register_types.DB_Z_INFO.fields.0 10106 {"bits": [2, 3], "name": "NUM_SAMPLES"}, array in object:register_types.DB_Z_INFO.fields.1 10107 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.DB_Z_INFO.fields.2 10108 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, array in object:register_types.DB_Z_INFO.fields.3 10109 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_Z_INFO.fields.4 10110 {"bits": [28, 28], "name": "READ_SIZE"}, array in object:register_types.DB_Z_INFO.fields.5 10111 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, array in object:register_types.DB_Z_INFO.fields.6 10112 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} array in object:register_types.DB_Z_INFO.fields.7 10117 {"bits": [0, 2], "name": "NUM_PIPES"}, array in object:register_types.GB_ADDR_CONFIG.fields.0 10118 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.1 10119 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.2 10120 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"}, array in object:register_types.GB_ADDR_CONFIG.fields.3 10121 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.4 10122 {"bits": [20, 22], "name": "NUM_GPUS"}, array in object:register_types.GB_ADDR_CONFIG.fields.5 10123 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.6 10124 {"bits": [28, 29], "name": "ROW_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.7 10125 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"} array in object:register_types.GB_ADDR_CONFIG.fields.8 10130 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, array in object:register_types.GB_MACROTILE_MODE0.fields.0 10131 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.1 10132 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.2 10133 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} array in object:register_types.GB_MACROTILE_MODE0.fields.3 10138 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.GB_TILE_MODE0.fields.0 10139 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.GB_TILE_MODE0.fields.1 10140 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.GB_TILE_MODE0.fields.2 10141 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, array in object:register_types.GB_TILE_MODE0.fields.3 10142 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} array in object:register_types.GB_TILE_MODE0.fields.4 10147 {"bits": [0, 15], "name": "BASE"}, array in object:register_types.GDS_ATOM_BASE.fields.0 10148 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_BASE.fields.1 10153 {"bits": [0, 5], "name": "AINC"}, array in object:register_types.GDS_ATOM_CNTL.fields.0 10154 {"bits": [6, 7], "name": "UNUSED1"}, array in object:register_types.GDS_ATOM_CNTL.fields.1 10155 {"bits": [8, 8], "name": "DMODE"}, array in object:register_types.GDS_ATOM_CNTL.fields.2 10156 {"bits": [9, 31], "name": "UNUSED2"} array in object:register_types.GDS_ATOM_CNTL.fields.3 10161 {"bits": [0, 0], "name": "COMPLETE"}, array in object:register_types.GDS_ATOM_COMPLETE.fields.0 10162 {"bits": [1, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_COMPLETE.fields.1 10167 {"bits": [0, 7], "name": "OFFSET0"}, array in object:register_types.GDS_ATOM_OFFSET0.fields.0 10168 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET0.fields.1 10173 {"bits": [0, 7], "name": "OFFSET1"}, array in object:register_types.GDS_ATOM_OFFSET1.fields.0 10174 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET1.fields.1 10179 {"bits": [0, 7], "name": "OP"}, array in object:register_types.GDS_ATOM_OP.fields.0 10180 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OP.fields.1 10185 {"bits": [0, 15], "name": "SIZE"}, array in object:register_types.GDS_ATOM_SIZE.fields.0 10186 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_SIZE.fields.1 10191 {"bits": [0, 0], "name": "FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.0 10192 {"bits": [1, 12], "name": "COUNTER"}, array in object:register_types.GDS_GWS_RESOURCE.fields.1 10193 {"bits": [13, 13], "name": "TYPE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.2 10194 {"bits": [14, 14], "name": "DED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.3 10195 {"bits": [15, 15], "name": "RELEASE_ALL"}, array in object:register_types.GDS_GWS_RESOURCE.fields.4 10196 {"bits": [16, 26], "name": "HEAD_QUEUE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.5 10197 {"bits": [27, 27], "name": "HEAD_VALID"}, array in object:register_types.GDS_GWS_RESOURCE.fields.6 10198 {"bits": [28, 28], "name": "HEAD_FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.7 10199 {"bits": [29, 31], "name": "UNUSED1"} array in object:register_types.GDS_GWS_RESOURCE.fields.8 10204 {"bits": [0, 15], "name": "RESOURCE_CNT"}, array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.0 10205 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.1 10210 {"bits": [0, 5], "name": "INDEX"}, array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.0 10211 {"bits": [6, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.1 10216 {"bits": [0, 15], "name": "DS_ADDRESS"}, array in object:register_types.GDS_OA_ADDRESS.fields.0 10217 {"bits": [16, 19], "name": "CRAWLER_TYPE"}, array in object:register_types.GDS_OA_ADDRESS.fields.1 10218 {"bits": [20, 23], "name": "CRAWLER"}, array in object:register_types.GDS_OA_ADDRESS.fields.2 10219 {"bits": [24, 29], "name": "UNUSED"}, array in object:register_types.GDS_OA_ADDRESS.fields.3 10220 {"bits": [30, 30], "name": "NO_ALLOC"}, array in object:register_types.GDS_OA_ADDRESS.fields.4 10221 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.GDS_OA_ADDRESS.fields.5 10226 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.GDS_OA_CNTL.fields.0 10227 {"bits": [4, 31], "name": "UNUSED"} array in object:register_types.GDS_OA_CNTL.fields.1 10232 {"bits": [0, 30], "name": "VALUE"}, array in object:register_types.GDS_OA_INCDEC.fields.0 10233 {"bits": [31, 31], "name": "INCDEC"} array in object:register_types.GDS_OA_INCDEC.fields.1 10238 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.0 10239 {"bits": [8, 15], "name": "SH_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.1 10240 {"bits": [16, 23], "name": "SE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.2 10241 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.3 10242 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.4 10243 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} array in object:register_types.GRBM_GFX_INDEX.fields.5 10248 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.0 10249 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.1 10250 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.2 10251 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.3 10252 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.4 10253 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.5 10254 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.6 10255 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.7 10256 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.8 10257 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.9 10258 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.10 10259 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.11 10260 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.12 10261 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.13 10262 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.14 10263 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.15 10264 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.16 10265 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.17 10266 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.18 10271 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.0 10272 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.1 10273 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.2 10274 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.3 10275 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.4 10276 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.5 10277 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.6 10278 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.7 10279 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.8 10280 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.9 10281 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.10 10282 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.11 10287 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS.fields.0 10288 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.1 10289 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.2 10290 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.3 10291 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.4 10292 {"bits": [12, 12], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.5 10293 {"bits": [13, 13], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.6 10294 {"bits": [14, 14], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.7 10295 {"bits": [15, 15], "name": "GDS_BUSY"}, array in object:register_types.GRBM_STATUS.fields.8 10296 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.9 10297 {"bits": [17, 17], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS.fields.10 10298 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.11 10299 {"bits": [19, 19], "name": "IA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.12 10300 {"bits": [20, 20], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS.fields.13 10301 {"bits": [21, 21], "name": "WD_BUSY"}, array in object:register_types.GRBM_STATUS.fields.14 10302 {"bits": [22, 22], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.15 10303 {"bits": [23, 23], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.16 10304 {"bits": [24, 24], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS.fields.17 10305 {"bits": [25, 25], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.18 10306 {"bits": [26, 26], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.19 10307 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, array in object:register_types.GRBM_STATUS.fields.20 10308 {"bits": [29, 29], "name": "CP_BUSY"}, array in object:register_types.GRBM_STATUS.fields.21 10309 {"bits": [30, 30], "name": "CB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.22 10310 {"bits": [31, 31], "name": "GUI_ACTIVE"} array in object:register_types.GRBM_STATUS.fields.23 10315 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS2.fields.0 10316 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.1 10317 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.2 10318 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.3 10319 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.4 10320 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.5 10321 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.6 10322 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.7 10323 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.8 10324 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.9 10325 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.10 10326 {"bits": [14, 14], "name": "RLC_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.11 10327 {"bits": [24, 24], "name": "RLC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.12 10328 {"bits": [25, 25], "name": "TC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.13 10329 {"bits": [28, 28], "name": "CPF_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.14 10330 {"bits": [29, 29], "name": "CPC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.15 10331 {"bits": [30, 30], "name": "CPG_BUSY"} array in object:register_types.GRBM_STATUS2.fields.16 10336 {"bits": [1, 1], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.0 10337 {"bits": [2, 2], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.1 10338 {"bits": [22, 22], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.2 10339 {"bits": [23, 23], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.3 10340 {"bits": [24, 24], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.4 10341 {"bits": [25, 25], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.5 10342 {"bits": [26, 26], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.6 10343 {"bits": [27, 27], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.7 10344 {"bits": [29, 29], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.8 10345 {"bits": [30, 30], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.9 10346 {"bits": [31, 31], "name": "CB_BUSY"} array in object:register_types.GRBM_STATUS_SE0.fields.10 10351 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.0 10352 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.1 10353 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.2 10354 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.3 10355 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.4 10356 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} array in object:register_types.IA_MULTI_VGT_PARAM.fields.5 10361 {"bits": [0, 0], "name": "UCP_ENA_0"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.0 10362 {"bits": [1, 1], "name": "UCP_ENA_1"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.1 10363 {"bits": [2, 2], "name": "UCP_ENA_2"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.2 10364 {"bits": [3, 3], "name": "UCP_ENA_3"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.3 10365 {"bits": [4, 4], "name": "UCP_ENA_4"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.4 10366 {"bits": [5, 5], "name": "UCP_ENA_5"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.5 10367 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.6 10368 {"bits": [14, 15], "name": "PS_UCP_MODE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.7 10369 {"bits": [16, 16], "name": "CLIP_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.8 10370 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.9 10371 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.10 10372 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.11 10373 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.12 10374 {"bits": [21, 21], "name": "VTX_KILL_OR"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.13 10375 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.14 10376 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.15 10377 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.16 10378 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.17 10379 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"} array in object:register_types.PA_CL_CLIP_CNTL.fields.18 10384 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.0 10385 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.1 10386 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.2 10387 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.3 10388 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.4 10389 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.5 10390 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.6 10391 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.7 10392 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.8 10393 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.9 10394 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.10 10395 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.11 10396 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.12 10397 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.13 10398 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.14 10399 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} array in object:register_types.PA_CL_NANINF_CNTL.fields.15 10404 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.0 10405 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.1 10406 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.2 10407 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.3 10408 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.4 10409 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.5 10410 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.6 10411 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.7 10412 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.8 10413 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.9 10414 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.10 10415 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.11 10416 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.12 10417 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.13 10418 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.14 10419 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.15 10420 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.16 10421 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.17 10422 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.18 10423 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.19 10424 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.20 10425 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.21 10426 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.22 10427 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.23 10428 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.24 10429 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"} array in object:register_types.PA_CL_VS_OUT_CNTL.fields.25 10434 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.0 10435 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.1 10436 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.2 10437 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.3 10438 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.4 10439 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.5 10440 {"bits": [8, 8], "name": "VTX_XY_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.6 10441 {"bits": [9, 9], "name": "VTX_Z_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.7 10442 {"bits": [10, 10], "name": "VTX_W0_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.8 10443 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} array in object:register_types.PA_CL_VTE_CNTL.fields.9 10448 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.0 10449 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, array in object:register_types.PA_SC_AA_CONFIG.fields.1 10450 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, array in object:register_types.PA_SC_AA_CONFIG.fields.2 10451 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.3 10452 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"} array in object:register_types.PA_SC_AA_CONFIG.fields.4 10457 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.0 10458 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.1 10463 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.0 10464 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.1 10469 {"bits": [0, 3], "name": "S0_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.0 10470 {"bits": [4, 7], "name": "S0_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.1 10471 {"bits": [8, 11], "name": "S1_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.2 10472 {"bits": [12, 15], "name": "S1_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.3 10473 {"bits": [16, 19], "name": "S2_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.4 10474 {"bits": [20, 23], "name": "S2_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.5 10475 {"bits": [24, 27], "name": "S3_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.6 10476 {"bits": [28, 31], "name": "S3_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.7 10481 {"bits": [0, 3], "name": "S4_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.0 10482 {"bits": [4, 7], "name": "S4_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.1 10483 {"bits": [8, 11], "name": "S5_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.2 10484 {"bits": [12, 15], "name": "S5_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.3 10485 {"bits": [16, 19], "name": "S6_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.4 10486 {"bits": [20, 23], "name": "S6_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.5 10487 {"bits": [24, 27], "name": "S7_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.6 10488 {"bits": [28, 31], "name": "S7_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.7 10493 {"bits": [0, 3], "name": "S8_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.0 10494 {"bits": [4, 7], "name": "S8_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.1 10495 {"bits": [8, 11], "name": "S9_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.2 10496 {"bits": [12, 15], "name": "S9_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.3 10497 {"bits": [16, 19], "name": "S10_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.4 10498 {"bits": [20, 23], "name": "S10_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.5 10499 {"bits": [24, 27], "name": "S11_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.6 10500 {"bits": [28, 31], "name": "S11_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.7 10505 {"bits": [0, 3], "name": "S12_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.0 10506 {"bits": [4, 7], "name": "S12_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.1 10507 {"bits": [8, 11], "name": "S13_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.2 10508 {"bits": [12, 15], "name": "S13_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.3 10509 {"bits": [16, 19], "name": "S14_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.4 10510 {"bits": [20, 23], "name": "S14_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.5 10511 {"bits": [24, 27], "name": "S15_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.6 10512 {"bits": [28, 31], "name": "S15_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.7 10517 {"bits": [0, 3], "name": "DISTANCE_0"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.0 10518 {"bits": [4, 7], "name": "DISTANCE_1"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.1 10519 {"bits": [8, 11], "name": "DISTANCE_2"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.2 10520 {"bits": [12, 15], "name": "DISTANCE_3"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.3 10521 {"bits": [16, 19], "name": "DISTANCE_4"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.4 10522 {"bits": [20, 23], "name": "DISTANCE_5"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.5 10523 {"bits": [24, 27], "name": "DISTANCE_6"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.6 10524 {"bits": [28, 31], "name": "DISTANCE_7"} array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.7 10529 {"bits": [0, 3], "name": "DISTANCE_8"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.0 10530 {"bits": [4, 7], "name": "DISTANCE_9"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.1 10531 {"bits": [8, 11], "name": "DISTANCE_10"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.2 10532 {"bits": [12, 15], "name": "DISTANCE_11"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.3 10533 {"bits": [16, 19], "name": "DISTANCE_12"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.4 10534 {"bits": [20, 23], "name": "DISTANCE_13"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.5 10535 {"bits": [24, 27], "name": "DISTANCE_14"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.6 10536 {"bits": [28, 31], "name": "DISTANCE_15"} array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.7 10541 {"bits": [0, 14], "name": "BR_X"}, array in object:register_types.PA_SC_CLIPRECT_0_BR.fields.0 10542 {"bits": [16, 30], "name": "BR_Y"} array in object:register_types.PA_SC_CLIPRECT_0_BR.fields.1 10547 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.0 10548 {"bits": [16, 30], "name": "TL_Y"} array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.1 10553 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} array in object:register_types.PA_SC_CLIPRECT_RULE.fields.0 10558 {"bits": [0, 3], "name": "ER_TRI"}, array in object:register_types.PA_SC_EDGERULE.fields.0 10559 {"bits": [4, 7], "name": "ER_POINT"}, array in object:register_types.PA_SC_EDGERULE.fields.1 10560 {"bits": [8, 11], "name": "ER_RECT"}, array in object:register_types.PA_SC_EDGERULE.fields.2 10561 {"bits": [12, 17], "name": "ER_LINE_LR"}, array in object:register_types.PA_SC_EDGERULE.fields.3 10562 {"bits": [18, 23], "name": "ER_LINE_RL"}, array in object:register_types.PA_SC_EDGERULE.fields.4 10563 {"bits": [24, 27], "name": "ER_LINE_TB"}, array in object:register_types.PA_SC_EDGERULE.fields.5 10564 {"bits": [28, 31], "name": "ER_LINE_BT"} array in object:register_types.PA_SC_EDGERULE.fields.6 10569 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.0 10570 {"bits": [16, 30], "name": "TL_Y"}, array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.1 10571 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.2 10576 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, array in object:register_types.PA_SC_LINE_CNTL.fields.0 10577 {"bits": [10, 10], "name": "LAST_PIXEL"}, array in object:register_types.PA_SC_LINE_CNTL.fields.1 10578 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.2 10579 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"} array in object:register_types.PA_SC_LINE_CNTL.fields.3 10584 {"bits": [0, 15], "name": "LINE_PATTERN"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.0 10585 {"bits": [16, 23], "name": "REPEAT_COUNT"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.1 10586 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.2 10587 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} array in object:register_types.PA_SC_LINE_STIPPLE.fields.3 10592 {"bits": [0, 3], "name": "CURRENT_PTR"}, array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.0 10593 {"bits": [8, 15], "name": "CURRENT_COUNT"} array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.1 10598 {"bits": [0, 0], "name": "MSAA_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.0 10599 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.1 10600 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.2 10601 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"} array in object:register_types.PA_SC_MODE_CNTL_0.fields.3 10606 {"bits": [0, 0], "name": "WALK_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.0 10607 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.1 10608 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.2 10609 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.3 10610 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.4 10611 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.5 10612 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.6 10613 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.7 10614 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.8 10615 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.9 10616 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.10 10617 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.11 10618 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.12 10619 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.13 10620 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.14 10621 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.15 10622 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.16 10623 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.17 10624 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.18 10625 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.19 10626 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.20 10627 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.21 10628 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.22 10629 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} array in object:register_types.PA_SC_MODE_CNTL_1.fields.23 10634 {"bits": [0, 13], "name": "X_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_H.fields.0 10639 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"}, array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.0 10640 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.1 10645 {"bits": [0, 13], "name": "Y_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_V.fields.0 10650 {"bits": [0, 9], "name": "PERF_SEL"} array in object:register_types.PA_SC_PERFCOUNTER1_SELECT.fields.0 10655 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.0 10656 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.1 10657 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.2 10658 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.3 10659 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.4 10660 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.5 10661 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.6 10662 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.7 10663 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.8 10664 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.9 10665 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.10 10666 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.11 10667 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.12 10668 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.13 10669 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG.fields.14 10674 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0 10675 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1 10676 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2 10681 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.0 10682 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"} array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.1 10687 {"bits": [0, 15], "name": "X"}, array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.0 10688 {"bits": [16, 31], "name": "Y"} array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.1 10693 {"bits": [0, 15], "name": "BR_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.0 10694 {"bits": [16, 31], "name": "BR_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.1 10699 {"bits": [0, 15], "name": "TL_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.0 10700 {"bits": [16, 31], "name": "TL_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.1 10705 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, array in object:register_types.PA_SC_WINDOW_OFFSET.fields.0 10706 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} array in object:register_types.PA_SC_WINDOW_OFFSET.fields.1 10711 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.0 10712 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.1 10717 {"bits": [0, 15], "name": "WIDTH"} array in object:register_types.PA_SU_LINE_CNTL.fields.0 10722 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.0 10723 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.1 10724 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.2 10725 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.3 10730 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} array in object:register_types.PA_SU_LINE_STIPPLE_VALUE.fields.0 10735 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} array in object:register_types.PA_SU_PERFCOUNTER0_HI.fields.0 10740 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.0 10741 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.1 10742 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.2 10747 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.0 10748 {"bits": [10, 19], "name": "PERF_SEL3"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.1 10753 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.0 10754 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.1 10759 {"bits": [0, 15], "name": "MIN_SIZE"}, array in object:register_types.PA_SU_POINT_MINMAX.fields.0 10760 {"bits": [16, 31], "name": "MAX_SIZE"} array in object:register_types.PA_SU_POINT_MINMAX.fields.1 10765 {"bits": [0, 15], "name": "HEIGHT"}, array in object:register_types.PA_SU_POINT_SIZE.fields.0 10766 {"bits": [16, 31], "name": "WIDTH"} array in object:register_types.PA_SU_POINT_SIZE.fields.1 10771 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.0 10772 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.1 10777 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.0 10778 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.1 10779 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.2 10780 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.3 10781 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.4 10782 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.5 10783 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.6 10784 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.7 10785 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.8 10786 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.9 10787 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.10 10792 {"bits": [0, 0], "name": "CULL_FRONT"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.0 10793 {"bits": [1, 1], "name": "CULL_BACK"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.1 10794 {"bits": [2, 2], "name": "FACE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.2 10795 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.3 10796 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ array in object:register_types.PA_SU_SC_MODE_CNTL.fields.4 10797 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE array in object:register_types.PA_SU_SC_MODE_CNTL.fields.5 10798 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.6 10799 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.7 10800 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.8 10801 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.9 10802 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.10 10803 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.11 10804 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"} array in object:register_types.PA_SU_SC_MODE_CNTL.fields.12 10809 {"bits": [0, 0], "name": "PIX_CENTER"}, array in object:register_types.PA_SU_VTX_CNTL.fields.0 10810 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, array in object:register_types.PA_SU_VTX_CNTL.fields.1 10811 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} array in object:register_types.PA_SU_VTX_CNTL.fields.2 10816 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"} array in object:register_types.RLC_PERFCOUNTER0_SELECT.fields.0 10821 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.RLC_PERFMON_CNTL.fields.0 10822 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.RLC_PERFMON_CNTL.fields.1 10827 {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"}, array in object:register_types.RLC_SPM_CPG_PERFMON_SAMPLE_DELAY.fields.0 10828 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_CPG_PERFMON_SAMPLE_DELAY.fields.1 10833 {"bits": [0, 11], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.0 10834 {"bits": [12, 13], "name": "PERFMON_RING_MODE"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.1 10835 {"bits": [14, 15], "name": "RESERVED"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.2 10836 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"} array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.3 10841 {"bits": [0, 15], "name": "RING_BASE_HI"}, array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.0 10842 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.1 10847 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.0 10848 {"bits": [8, 10], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.1 10849 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.2 10850 {"bits": [16, 20], "name": "SE0_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.3 10851 {"bits": [21, 25], "name": "SE1_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.4 10852 {"bits": [26, 30], "name": "SE2_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.5 10853 {"bits": [31, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.6 10858 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, array in object:register_types.SCRATCH_UMSK.fields.0 10859 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} array in object:register_types.SCRATCH_UMSK.fields.1 10864 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.0 10865 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.1 10866 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.2 10867 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.3 10868 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, array in object:register_types.SPI_BARYC_CNTL.fields.4 10869 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, array in object:register_types.SPI_BARYC_CNTL.fields.5 10870 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} array in object:register_types.SPI_BARYC_CNTL.fields.6 10875 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, array in object:register_types.SPI_CONFIG_CNTL.fields.0 10876 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, array in object:register_types.SPI_CONFIG_CNTL.fields.1 10877 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.2 10878 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.3 10879 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, array in object:register_types.SPI_CONFIG_CNTL.fields.4 10880 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"} array in object:register_types.SPI_CONFIG_CNTL.fields.5 10885 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.0 10886 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.1 10887 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.2 10888 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.3 10889 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.4 10890 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.5 10891 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} array in object:register_types.SPI_INTERP_CONTROL_0.fields.6 10896 {"bits": [0, 7], "name": "PERF_SEL"} array in object:register_types.SPI_PERFCOUNTER4_SELECT.fields.0 10901 {"bits": [0, 3], "name": "BIN0_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.0 10902 {"bits": [4, 7], "name": "BIN0_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.1 10903 {"bits": [8, 11], "name": "BIN1_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.2 10904 {"bits": [12, 15], "name": "BIN1_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.3 10905 {"bits": [16, 19], "name": "BIN2_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.4 10906 {"bits": [20, 23], "name": "BIN2_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.5 10907 {"bits": [24, 27], "name": "BIN3_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.6 10908 {"bits": [28, 31], "name": "BIN3_MAX"} array in object:register_types.SPI_PERFCOUNTER_BINS.fields.7 10913 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.0 10914 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.1 10915 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.2 10916 {"bits": [13, 16], "name": "CYL_WRAP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.3 10917 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.4 10918 {"bits": [18, 18], "name": "DUP"} array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.5 10923 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.0 10924 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.1 10925 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.2 10926 {"bits": [18, 18], "name": "DUP"} array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.3 10931 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.0 10932 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.1 10933 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.2 10934 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.3 10935 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.4 10936 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.5 10937 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.6 10938 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.7 10939 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.8 10940 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.9 10941 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.10 10942 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.11 10943 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.12 10944 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.13 10945 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.14 10946 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} array in object:register_types.SPI_PS_INPUT_ENA.fields.15 10951 {"bits": [0, 5], "name": "NUM_INTERP"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.0 10952 {"bits": [6, 6], "name": "PARAM_GEN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.1 10953 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} array in object:register_types.SPI_PS_IN_CONTROL.fields.2 10958 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.0 10959 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.1 10960 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.2 10961 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.3 10962 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.4 10963 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.5 10964 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.6 10965 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_COL_FORMAT.fields.7 10970 {"bits": [0, 5], "name": "LIMIT"} array in object:register_types.SPI_SHADER_LATE_ALLOC_VS.fields.0 10975 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.0 10976 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.1 10977 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.2 10978 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3 10979 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.4 10980 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.5 10981 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.6 10982 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.7 10983 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.8 10984 {"bits": [25, 27], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.9 10985 {"bits": [28, 28], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.10 10990 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.0 10991 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.1 10992 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.2 10993 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3 10994 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.4 10995 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.5 10996 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.6 10997 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.7 10998 {"bits": [24, 26], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.8 10999 {"bits": [27, 27], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.9 11004 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.0 11005 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.1 11006 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.2 11007 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3 11008 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.4 11009 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.5 11010 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.6 11011 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.7 11012 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.8 11013 {"bits": [26, 28], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.9 11014 {"bits": [29, 29], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.10 11019 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.0 11020 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.1 11021 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.2 11022 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3 11023 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.4 11024 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.5 11025 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.6 11026 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.7 11027 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.8 11028 {"bits": [25, 27], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.9 11029 {"bits": [28, 28], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.10 11034 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.0 11035 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.1 11036 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.2 11037 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3 11038 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.4 11039 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.5 11040 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.6 11041 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.7 11042 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.8 11043 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.9 11044 {"bits": [27, 29], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.10 11045 {"bits": [30, 30], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.11 11050 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.0 11051 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.1 11052 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.2 11053 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.3 11054 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.4 11055 {"bits": [20, 28], "name": "LDS_SIZE"} array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.5 11060 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.0 11061 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.1 11062 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.2 11063 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3 11068 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.0 11069 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.1 11070 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.2 11071 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.3 11072 {"bits": [8, 8], "name": "TG_SIZE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.4 11073 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5 11078 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.0 11079 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.1 11080 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.2 11081 {"bits": [7, 15], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.3 11082 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.4 11087 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.0 11088 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.1 11089 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.2 11090 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.3 11091 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.4 11092 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5 11097 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.0 11098 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.1 11099 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.2 11100 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.3 11101 {"bits": [8, 8], "name": "SO_BASE0_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.4 11102 {"bits": [9, 9], "name": "SO_BASE1_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.5 11103 {"bits": [10, 10], "name": "SO_BASE2_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.6 11104 {"bits": [11, 11], "name": "SO_BASE3_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.7 11105 {"bits": [12, 12], "name": "SO_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.8 11106 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9 11111 {"bits": [0, 5], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.0 11112 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"} array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.1 11117 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.0 11118 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.1 11119 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"} array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.2 11124 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.0 11125 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.1 11126 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.2 11127 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_POS_FORMAT.fields.3 11132 {"bits": [0, 7], "name": "MEM_BASE"} array in object:register_types.SPI_SHADER_TBA_HI_PS.fields.0 11137 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_Z_FORMAT.fields.0 11142 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.0 11143 {"bits": [6, 6], "name": "VS_HALF_PACK"} array in object:register_types.SPI_VS_OUT_CONFIG.fields.1 11148 {"bits": [0, 0], "name": "INST_INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.0 11149 {"bits": [1, 1], "name": "DATA_INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.1 11150 {"bits": [2, 2], "name": "INVALIDATE_VOLATILE"} array in object:register_types.SQC_CACHES.fields.2 11155 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.0 11156 {"bits": [16, 29], "name": "STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.1 11157 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.2 11158 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} array in object:register_types.SQ_BUF_RSRC_WORD1.fields.3 11163 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.0 11164 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.1 11165 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.2 11166 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.3 11167 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.4 11168 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.5 11169 {"bits": [19, 20], "name": "ELEMENT_SIZE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.6 11170 {"bits": [21, 22], "name": "INDEX_STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.7 11171 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.8 11172 {"bits": [24, 24], "name": "ATC"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.9 11173 {"bits": [25, 25], "name": "HASH_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.10 11174 {"bits": [26, 26], "name": "HEAP"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.11 11175 {"bits": [27, 29], "name": "MTYPE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.12 11176 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} array in object:register_types.SQ_BUF_RSRC_WORD3.fields.13 11181 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.0 11182 {"bits": [8, 19], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.1 11183 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.2 11184 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.3 11185 {"bits": [30, 31], "name": "MTYPE"} array in object:register_types.SQ_IMG_RSRC_WORD1.fields.4 11190 {"bits": [0, 13], "name": "WIDTH"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.0 11191 {"bits": [14, 27], "name": "HEIGHT"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.1 11192 {"bits": [28, 30], "name": "PERF_MOD"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.2 11193 {"bits": [31, 31], "name": "INTERLACED"} array in object:register_types.SQ_IMG_RSRC_WORD2.fields.3 11198 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.0 11199 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.1 11200 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.2 11201 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.3 11202 {"bits": [12, 15], "name": "BASE_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.4 11203 {"bits": [16, 19], "name": "LAST_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.5 11204 {"bits": [20, 24], "name": "TILING_INDEX"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.6 11205 {"bits": [25, 25], "name": "POW2_PAD"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.7 11206 {"bits": [26, 26], "name": "MTYPE"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.8 11207 {"bits": [27, 27], "name": "ATC"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.9 11208 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} array in object:register_types.SQ_IMG_RSRC_WORD3.fields.10 11213 {"bits": [0, 12], "name": "DEPTH"}, array in object:register_types.SQ_IMG_RSRC_WORD4.fields.0 11214 {"bits": [13, 26], "name": "PITCH"} array in object:register_types.SQ_IMG_RSRC_WORD4.fields.1 11219 {"bits": [0, 12], "name": "BASE_ARRAY"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.0 11220 {"bits": [13, 25], "name": "LAST_ARRAY"} array in object:register_types.SQ_IMG_RSRC_WORD5.fields.1 11225 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.0 11226 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.1 11227 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.2 11228 {"bits": [21, 31], "name": "UNUNSED"} array in object:register_types.SQ_IMG_RSRC_WORD6.fields.3 11233 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.0 11234 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.1 11235 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.2 11236 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.3 11237 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.4 11238 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.5 11239 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.6 11240 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.7 11241 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.8 11242 {"bits": [21, 26], "name": "ANISO_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.9 11243 {"bits": [27, 27], "name": "TRUNC_COORD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.10 11244 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.11 11245 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"} array in object:register_types.SQ_IMG_SAMP_WORD0.fields.12 11250 {"bits": [0, 11], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.0 11251 {"bits": [12, 23], "name": "MAX_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.1 11252 {"bits": [24, 27], "name": "PERF_MIP"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.2 11253 {"bits": [28, 31], "name": "PERF_Z"} array in object:register_types.SQ_IMG_SAMP_WORD1.fields.3 11258 {"bits": [0, 13], "name": "LOD_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.0 11259 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.1 11260 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.2 11261 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.3 11262 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.4 11263 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.5 11264 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.6 11265 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.7 11266 {"bits": [30, 30], "name": "FILTER_PREC_FIX"} array in object:register_types.SQ_IMG_SAMP_WORD2.fields.8 11271 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.0 11272 {"bits": [29, 29], "name": "UPGRADED_DEPTH"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.1 11273 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} array in object:register_types.SQ_IMG_SAMP_WORD3.fields.2 11278 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.0 11279 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.1 11280 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.2 11281 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.3 11282 {"bits": [24, 27], "name": "SIMD_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.4 11283 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.5 11288 {"bits": [0, 0], "name": "PS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.0 11289 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1 11290 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2 11291 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3 11292 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4 11293 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5 11294 {"bits": [6, 6], "name": "CS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.6 11295 {"bits": [8, 12], "name": "CNTR_RATE"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.7 11296 {"bits": [13, 13], "name": "DISABLE_FLUSH"} array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.8 11301 {"bits": [0, 0], "name": "FORCE_EN"} array in object:register_types.SQ_PERFCOUNTER_CTRL2.fields.0 11306 {"bits": [0, 15], "name": "SH0_MASK"}, array in object:register_types.SQ_PERFCOUNTER_MASK.fields.0 11307 {"bits": [16, 31], "name": "SH1_MASK"} array in object:register_types.SQ_PERFCOUNTER_MASK.fields.1 11312 {"bits": [0, 3], "name": "ADDR_HI"}, array in object:register_types.SQ_THREAD_TRACE_BASE2.fields.0 11313 {"bits": [4, 4], "name": "ATC"} array in object:register_types.SQ_THREAD_TRACE_BASE2.fields.1 11318 {"bits": [31, 31], "name": "RESET_BUFFER"} array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.0 11323 {"bits": [0, 2], "name": "HIWATER"} array in object:register_types.SQ_THREAD_TRACE_HIWATER.fields.0 11328 {"bits": [0, 4], "name": "CU_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.0 11329 {"bits": [5, 5], "name": "SH_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.1 11330 {"bits": [7, 7], "name": "REG_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.2 11331 {"bits": [8, 11], "name": "SIMD_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.3 11332 {"bits": [12, 13], "name": "VM_ID_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.4 11333 {"bits": [14, 14], "name": "SPI_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.5 11334 {"bits": [15, 15], "name": "SQ_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.6 11335 {"bits": [16, 31], "name": "RANDOM_SEED"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.7 11336 {"bits": [16, 31], "name": "RANDOM_SEED"} array in object:register_types.SQ_THREAD_TRACE_MASK.fields.8 11341 {"bits": [0, 2], "name": "MASK_PS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.0 11342 {"bits": [3, 5], "name": "MASK_VS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.1 11343 {"bits": [6, 8], "name": "MASK_GS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.2 11344 {"bits": [9, 11], "name": "MASK_ES"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.3 11345 {"bits": [12, 14], "name": "MASK_HS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.4 11346 {"bits": [15, 17], "name": "MASK_LS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.5 11347 {"bits": [18, 20], "name": "MASK_CS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.6 11348 {"bits": [21, 22], "name": "MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.7 11349 {"bits": [23, 24], "name": "CAPTURE_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.8 11350 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.9 11351 {"bits": [26, 26], "name": "PRIV"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.10 11352 {"bits": [27, 28], "name": "ISSUE_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.11 11353 {"bits": [29, 29], "name": "TEST_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.12 11354 {"bits": [30, 30], "name": "INTERRUPT_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.13 11355 {"bits": [31, 31], "name": "WRAP"} array in object:register_types.SQ_THREAD_TRACE_MODE.fields.14 11360 {"bits": [0, 21], "name": "SIZE"} array in object:register_types.SQ_THREAD_TRACE_SIZE.fields.0 11365 {"bits": [0, 9], "name": "FINISH_PENDING"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.0 11366 {"bits": [16, 25], "name": "FINISH_DONE"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.1 11367 {"bits": [29, 29], "name": "NEW_BUF"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.2 11368 {"bits": [30, 30], "name": "BUSY"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.3 11369 {"bits": [31, 31], "name": "FULL"} array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.4 11374 {"bits": [0, 15], "name": "TOKEN_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0 11375 {"bits": [16, 23], "name": "REG_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.1 11376 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.2 11381 {"bits": [0, 15], "name": "INST_MASK"} array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK2.fields.0 11386 {"bits": [0, 29], "name": "WPTR"}, array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.0 11387 {"bits": [30, 31], "name": "READ_OFFSET"} array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.1 11392 {"bits": [0, 5], "name": "VGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.0 11393 {"bits": [8, 13], "name": "VGPR_SIZE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.1 11394 {"bits": [16, 21], "name": "SGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.2 11395 {"bits": [24, 27], "name": "SGPR_SIZE"} array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.3 11400 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.0 11401 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.1 11402 {"bits": [6, 7], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.2 11403 {"bits": [8, 11], "name": "CU_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.3 11404 {"bits": [12, 12], "name": "SH_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.4 11405 {"bits": [13, 14], "name": "SE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.5 11406 {"bits": [16, 19], "name": "TG_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.6 11407 {"bits": [20, 23], "name": "VM_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.7 11408 {"bits": [24, 26], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.8 11409 {"bits": [27, 29], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.9 11410 {"bits": [30, 31], "name": "ME_ID"} array in object:register_types.SQ_WAVE_HW_ID.fields.10 11415 {"bits": [0, 2], "name": "IBUF_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.0 11416 {"bits": [3, 3], "name": "PC_INVALID"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.1 11417 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.2 11418 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.3 11419 {"bits": [8, 9], "name": "IBUF_RPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.4 11420 {"bits": [10, 11], "name": "IBUF_WPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.5 11421 {"bits": [16, 18], "name": "INST_STR_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.6 11422 {"bits": [19, 21], "name": "MISC_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.7 11423 {"bits": [22, 23], "name": "ECC_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.8 11424 {"bits": [24, 24], "name": "IS_HYB"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.9 11425 {"bits": [25, 26], "name": "HYB_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.10 11426 {"bits": [27, 27], "name": "KILL"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.11 11427 {"bits": [28, 28], "name": "NEED_KILL_IFETCH"} array in object:register_types.SQ_WAVE_IB_DBG0.fields.12 11432 {"bits": [0, 3], "name": "VM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.0 11433 {"bits": [4, 6], "name": "EXP_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.1 11434 {"bits": [8, 11], "name": "LGKM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.2 11435 {"bits": [12, 14], "name": "VALU_CNT"} array in object:register_types.SQ_WAVE_IB_STS.fields.3 11440 {"bits": [0, 7], "name": "LDS_BASE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.0 11441 {"bits": [12, 20], "name": "LDS_SIZE"} array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.1 11446 {"bits": [0, 3], "name": "FP_ROUND"}, array in object:register_types.SQ_WAVE_MODE.fields.0 11447 {"bits": [4, 7], "name": "FP_DENORM"}, array in object:register_types.SQ_WAVE_MODE.fields.1 11448 {"bits": [8, 8], "name": "DX10_CLAMP"}, array in object:register_types.SQ_WAVE_MODE.fields.2 11449 {"bits": [9, 9], "name": "IEEE"}, array in object:register_types.SQ_WAVE_MODE.fields.3 11450 {"bits": [10, 10], "name": "LOD_CLAMPED"}, array in object:register_types.SQ_WAVE_MODE.fields.4 11451 {"bits": [11, 11], "name": "DEBUG_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.5 11452 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.6 11453 {"bits": [28, 28], "name": "VSKIP"}, array in object:register_types.SQ_WAVE_MODE.fields.7 11454 {"bits": [29, 31], "name": "CSP"} array in object:register_types.SQ_WAVE_MODE.fields.8 11459 {"bits": [0, 7], "name": "PC_HI"} array in object:register_types.SQ_WAVE_PC_HI.fields.0 11464 {"bits": [0, 0], "name": "SCC"}, array in object:register_types.SQ_WAVE_STATUS.fields.0 11465 {"bits": [1, 2], "name": "SPI_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.1 11466 {"bits": [3, 4], "name": "WAVE_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.2 11467 {"bits": [5, 5], "name": "PRIV"}, array in object:register_types.SQ_WAVE_STATUS.fields.3 11468 {"bits": [6, 6], "name": "TRAP_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.4 11469 {"bits": [7, 7], "name": "TTRACE_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.5 11470 {"bits": [8, 8], "name": "EXPORT_RDY"}, array in object:register_types.SQ_WAVE_STATUS.fields.6 11471 {"bits": [9, 9], "name": "EXECZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.7 11472 {"bits": [10, 10], "name": "VCCZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.8 11473 {"bits": [11, 11], "name": "IN_TG"}, array in object:register_types.SQ_WAVE_STATUS.fields.9 11474 {"bits": [12, 12], "name": "IN_BARRIER"}, array in object:register_types.SQ_WAVE_STATUS.fields.10 11475 {"bits": [13, 13], "name": "HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.11 11476 {"bits": [14, 14], "name": "TRAP"}, array in object:register_types.SQ_WAVE_STATUS.fields.12 11477 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.13 11478 {"bits": [16, 16], "name": "VALID"}, array in object:register_types.SQ_WAVE_STATUS.fields.14 11479 {"bits": [17, 17], "name": "ECC_ERR"}, array in object:register_types.SQ_WAVE_STATUS.fields.15 11480 {"bits": [18, 18], "name": "SKIP_EXPORT"}, array in object:register_types.SQ_WAVE_STATUS.fields.16 11481 {"bits": [19, 19], "name": "PERF_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.17 11482 {"bits": [20, 20], "name": "COND_DBG_USER"}, array in object:register_types.SQ_WAVE_STATUS.fields.18 11483 {"bits": [21, 21], "name": "COND_DBG_SYS"}, array in object:register_types.SQ_WAVE_STATUS.fields.19 11484 {"bits": [22, 22], "name": "DATA_ATC"}, array in object:register_types.SQ_WAVE_STATUS.fields.20 11485 {"bits": [23, 23], "name": "INST_ATC"}, array in object:register_types.SQ_WAVE_STATUS.fields.21 11486 {"bits": [24, 26], "name": "DISPATCH_CACHE_CTRL"}, array in object:register_types.SQ_WAVE_STATUS.fields.22 11487 {"bits": [27, 27], "name": "MUST_EXPORT"} array in object:register_types.SQ_WAVE_STATUS.fields.23 11492 {"bits": [0, 7], "name": "ADDR_HI"} array in object:register_types.SQ_WAVE_TBA_HI.fields.0 11497 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.0 11498 {"bits": [16, 21], "name": "EXCP_CYCLE"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.1 11499 {"bits": [29, 31], "name": "DP_RATE"} array in object:register_types.SQ_WAVE_TRAPSTS.fields.2 11504 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"}, array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.0 11505 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"}, array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.1 11506 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.2 11511 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"}, array in object:register_types.SX_PERFCOUNTER0_SELECT1.fields.0 11512 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"} array in object:register_types.SX_PERFCOUNTER0_SELECT1.fields.1 11517 {"bits": [0, 7], "name": "ADDRESS"} array in object:register_types.TA_BC_BASE_ADDR_HI.fields.0 11522 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.0 11523 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.1 11524 {"bits": [24, 27], "name": "PERF_MODE2"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.2 11525 {"bits": [28, 31], "name": "PERF_MODE3"} array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.3 11530 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.TCC_PERFCOUNTER2_SELECT.fields.0 11531 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TCC_PERFCOUNTER2_SELECT.fields.1 11532 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TCC_PERFCOUNTER2_SELECT.fields.2 11537 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.0 11538 {"bits": [10, 17], "name": "PERF_SEL1"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.1 11539 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.2 11540 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.3 11541 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.4 11546 {"bits": [0, 7], "name": "PERF_SEL2"}, array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.0 11547 {"bits": [10, 17], "name": "PERF_SEL3"}, array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.1 11548 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.2 11549 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.3 11554 {"bits": [0, 7], "name": "BASE_ADDR"} array in object:register_types.VGT_DMA_BASE_HI.fields.0 11559 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.0 11560 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.1 11561 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.2 11562 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.3 11563 {"bits": [8, 8], "name": "ATC"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.4 11564 {"bits": [9, 9], "name": "NOT_EOP"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.5 11565 {"bits": [10, 10], "name": "REQ_PATH"} array in object:register_types.VGT_DMA_INDEX_TYPE.fields.6 11570 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.0 11571 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.1 11572 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.2 11573 {"bits": [5, 5], "name": "NOT_EOP"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.3 11574 {"bits": [6, 6], "name": "USE_OPAQUE"} array in object:register_types.VGT_DRAW_INITIATOR.fields.4 11579 {"bits": [0, 14], "name": "ITEMSIZE"} array in object:register_types.VGT_ESGS_RING_ITEMSIZE.fields.0 11584 {"bits": [0, 10], "name": "ES_PER_GS"} array in object:register_types.VGT_ES_PER_GS.fields.0 11589 {"bits": [0, 27], "name": "ADDRESS_LOW"} array in object:register_types.VGT_EVENT_ADDRESS_REG.fields.0 11594 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.0 11595 {"bits": [18, 26], "name": "ADDRESS_HI"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.1 11596 {"bits": [27, 27], "name": "EXTENDED_EVENT"} array in object:register_types.VGT_EVENT_INITIATOR.fields.2 11601 {"bits": [0, 3], "name": "DECR"} array in object:register_types.VGT_GROUP_DECR.fields.0 11606 {"bits": [0, 3], "name": "FIRST_DECR"} array in object:register_types.VGT_GROUP_FIRST_DECR.fields.0 11611 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0 11612 {"bits": [14, 14], "name": "RETAIN_ORDER"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.1 11613 {"bits": [15, 15], "name": "RETAIN_QUADS"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.2 11614 {"bits": [16, 18], "name": "PRIM_ORDER"} array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.3 11619 {"bits": [0, 0], "name": "COMP_X_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.0 11620 {"bits": [1, 1], "name": "COMP_Y_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.1 11621 {"bits": [2, 2], "name": "COMP_Z_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.2 11622 {"bits": [3, 3], "name": "COMP_W_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.3 11623 {"bits": [8, 15], "name": "STRIDE"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.4 11624 {"bits": [16, 23], "name": "SHIFT"} array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.5 11629 {"bits": [0, 3], "name": "X_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.0 11630 {"bits": [4, 7], "name": "X_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.1 11631 {"bits": [8, 11], "name": "Y_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.2 11632 {"bits": [12, 15], "name": "Y_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.3 11633 {"bits": [16, 19], "name": "Z_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.4 11634 {"bits": [20, 23], "name": "Z_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.5 11635 {"bits": [24, 27], "name": "W_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.6 11636 {"bits": [28, 31], "name": "W_OFFSET"} array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.7 11641 {"bits": [0, 14], "name": "OFFSET"} array in object:register_types.VGT_GSVS_RING_OFFSET_1.fields.0 11646 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.0 11647 {"bits": [2, 8], "name": "CNT"} array in object:register_types.VGT_GS_INSTANCE_CNT.fields.1 11652 {"bits": [0, 10], "name": "MAX_VERT_OUT"} array in object:register_types.VGT_GS_MAX_VERT_OUT.fields.0 11657 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, array in object:register_types.VGT_GS_MODE.fields.0 11658 {"bits": [3, 3], "name": "RESERVED_0"}, array in object:register_types.VGT_GS_MODE.fields.1 11659 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, array in object:register_types.VGT_GS_MODE.fields.2 11660 {"bits": [6, 10], "name": "RESERVED_1"}, array in object:register_types.VGT_GS_MODE.fields.3 11661 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, array in object:register_types.VGT_GS_MODE.fields.4 11662 {"bits": [12, 12], "name": "RESERVED_2"}, array in object:register_types.VGT_GS_MODE.fields.5 11663 {"bits": [13, 13], "name": "ES_PASSTHRU"}, array in object:register_types.VGT_GS_MODE.fields.6 11664 {"bits": [14, 14], "name": "COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.7 11665 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, array in object:register_types.VGT_GS_MODE.fields.8 11666 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, array in object:register_types.VGT_GS_MODE.fields.9 11667 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, array in object:register_types.VGT_GS_MODE.fields.10 11668 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, array in object:register_types.VGT_GS_MODE.fields.11 11669 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.12 11670 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.13 11671 {"bits": [21, 22], "name": "ONCHIP"} array in object:register_types.VGT_GS_MODE.fields.14 11676 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.0 11677 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"} array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.1 11682 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0 11683 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1 11684 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2 11685 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3 11686 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.4 11691 {"bits": [0, 10], "name": "GS_PER_ES"} array in object:register_types.VGT_GS_PER_ES.fields.0 11696 {"bits": [0, 3], "name": "GS_PER_VS"} array in object:register_types.VGT_GS_PER_VS.fields.0 11701 {"bits": [0, 1], "name": "TESS_MODE"} array in object:register_types.VGT_HOS_CNTL.fields.0 11706 {"bits": [0, 7], "name": "REUSE_DEPTH"} array in object:register_types.VGT_HOS_REUSE_DEPTH.fields.0 11711 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"}, array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.0 11712 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1 11717 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} array in object:register_types.VGT_INDEX_TYPE.fields.0 11722 {"bits": [0, 7], "name": "NUM_PATCHES"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.0 11723 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.1 11724 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} array in object:register_types.VGT_LS_HS_CONFIG.fields.2 11729 {"bits": [0, 0], "name": "RESET_EN"} array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.0 11734 {"bits": [0, 2], "name": "PATH_SELECT"} array in object:register_types.VGT_OUTPUT_PATH_CNTL.fields.0 11739 {"bits": [0, 6], "name": "DEALLOC_DIST"} array in object:register_types.VGT_OUT_DEALLOC_CNTL.fields.0 11744 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.VGT_PERFCOUNTER2_SELECT.fields.0 11745 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.VGT_PERFCOUNTER2_SELECT.fields.1 11750 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} array in object:register_types.VGT_PERFCOUNTER_SEID_MASK.fields.0 11755 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.0 11756 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"} array in object:register_types.VGT_PRIMITIVEID_EN.fields.1 11761 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} array in object:register_types.VGT_PRIMITIVE_TYPE.fields.0 11766 {"bits": [0, 0], "name": "REUSE_OFF"} array in object:register_types.VGT_REUSE_OFF.fields.0 11771 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.0 11772 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.1 11773 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.2 11774 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.3 11775 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.4 11776 {"bits": [8, 8], "name": "DYNAMIC_HS"} array in object:register_types.VGT_SHADER_STAGES_EN.fields.5 11781 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.0 11782 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.1 11783 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.2 11784 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.3 11789 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.0 11790 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.1 11791 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.2 11792 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.3 11793 {"bits": [4, 6], "name": "RAST_STREAM"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.4 11794 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.5 11795 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} array in object:register_types.VGT_STRMOUT_CONFIG.fields.6 11800 {"bits": [0, 8], "name": "VERTEX_STRIDE"} array in object:register_types.VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE.fields.0 11805 {"bits": [0, 9], "name": "STRIDE"} array in object:register_types.VGT_STRMOUT_VTX_STRIDE_0.fields.0 11810 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, array in object:register_types.VGT_TF_PARAM.fields.0 11811 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, array in object:register_types.VGT_TF_PARAM.fields.1 11812 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, array in object:register_types.VGT_TF_PARAM.fields.2 11813 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, array in object:register_types.VGT_TF_PARAM.fields.3 11814 {"bits": [9, 9], "name": "DEPRECATED"}, array in object:register_types.VGT_TF_PARAM.fields.4 11815 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, array in object:register_types.VGT_TF_PARAM.fields.5 11816 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, array in object:register_types.VGT_TF_PARAM.fields.6 11817 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"} array in object:register_types.VGT_TF_PARAM.fields.7 11822 {"bits": [0, 15], "name": "SIZE"} array in object:register_types.VGT_TF_RING_SIZE.fields.0 11827 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} array in object:register_types.VGT_VERTEX_REUSE_BLOCK_CNTL.fields.0 11832 {"bits": [0, 0], "name": "VTX_CNT_EN"} array in object:register_types.VGT_VTX_CNT_EN.fields.0 [all...]
H A D	gfx9.json	10302 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.ATC_L2_PERFCOUNTER0_CFG.fields.0 10303 {"bits": [8, 15], "name": "PERF_SEL_END"}, array in object:register_types.ATC_L2_PERFCOUNTER0_CFG.fields.1 10304 {"bits": [24, 27], "name": "PERF_MODE"}, array in object:register_types.ATC_L2_PERFCOUNTER0_CFG.fields.2 10305 {"bits": [28, 28], "name": "ENABLE"}, array in object:register_types.ATC_L2_PERFCOUNTER0_CFG.fields.3 10306 {"bits": [29, 29], "name": "CLEAR"} array in object:register_types.ATC_L2_PERFCOUNTER0_CFG.fields.4 10311 {"bits": [0, 15], "name": "COUNTER_HI"}, array in object:register_types.ATC_L2_PERFCOUNTER_HI.fields.0 10312 {"bits": [16, 31], "name": "COMPARE_VALUE"} array in object:register_types.ATC_L2_PERFCOUNTER_HI.fields.1 10317 {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"}, array in object:register_types.ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.0 10318 {"bits": [8, 15], "name": "START_TRIGGER"}, array in object:register_types.ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.1 10319 {"bits" array in object:register_types.ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.2 10320 {"bits": [24, 24], "name": "ENABLE_ANY"}, array in object:register_types.ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.3 10321 {"bits": [25, 25], "name": "CLEAR_ALL"}, array in object:register_types.ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.4 10322 {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"} array in object:register_types.ATC_L2_PERFCOUNTER_RSLT_CNTL.fields.5 10327 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.0 10328 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.1 10329 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.2 10330 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.3 10331 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.4 10332 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.5 10333 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.6 10334 {"bits": [30, 30], "name": "ENABLE"}, array in object:register_types.CB_BLEND0_CONTROL.fields.7 10335 {"bits": [31, 31], "name": "DISABLE_ROP3"} array in object:register_types.CB_BLEND0_CONTROL.fields.8 10340 {"bits": [0, 10], "name": "MIP0_DEPTH"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.0 10341 {"bits": [11, 11], "name": "META_LINEAR"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.1 10342 {"bits": [12, 14], "name": "NUM_SAMPLES"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.2 10343 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.3 10344 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.4 10345 {"bits": [18, 22], "name": "COLOR_SW_MODE"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.5 10346 {"bits": [23, 27], "name": "FMASK_SW_MODE"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.6 10347 {"bits": [28, 29], "name": "RESOURCE_TYPE"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.7 10348 {"bits": [30, 30], "name": "RB_ALIGNED"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.8 10349 {"bits": [31, 31], "name": "PIPE_ALIGNED"} array in object:register_types.CB_COLOR0_ATTRIB.fields.9 10354 {"bits": [0, 13], "name": "MIP0_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB2.fields.0 10355 {"bits": [14, 27], "name": "MIP0_WIDTH"}, array in object:register_types.CB_COLOR0_ATTRIB2.fields.1 10356 {"bits": [28, 31], "name": "MAX_MIP"} array in object:register_types.CB_COLOR0_ATTRIB2.fields.2 10361 {"bits": [0, 7], "name": "BASE_256B"} array in object:register_types.CB_COLOR0_BASE_EXT.fields.0 10366 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.0 10367 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.1 10368 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": " array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2 10369 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MI array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3 10370 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.4 10371 {"bits": [7, 8], "name": "COLOR_TRANSFORM"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.5 10372 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.6 10373 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.7 10374 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.8 10375 {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.9 10376 {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"} array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.10 10381 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, array in object:register_types.CB_COLOR0_INFO.fields.0 10382 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, array in object:register_types.CB_COLOR0_INFO.fields.1 10383 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.2 10384 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, array in object:register_types.CB_COLOR0_INFO.fields.3 10385 {"bits": [13, 13], "name": "FAST_CLEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.4 10386 {"bits": [14, 14], "name": "COMPRESSION"}, array in object:register_types.CB_COLOR0_INFO.fields.5 10387 {"bits": [15, 15], "name": "BLEND_CLAMP"}, array in object:register_types.CB_COLOR0_INFO.fields.6 10388 {"bits": [16, 16], "name": "BLEND_BYPASS"}, array in object:register_types.CB_COLOR0_INFO.fields.7 10389 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, array in object:register_types.CB_COLOR0_INFO.fields.8 10390 {"bits": [18, 18], "name": "ROUND_MODE"}, array in object:register_types.CB_COLOR0_INFO.fields.9 10391 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, array in object:register_types.CB_COLOR0_INFO.fields.10 10392 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, array in object:register_types.CB_COLOR0_INFO.fields.11 10393 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.12 10394 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"}, array in object:register_types.CB_COLOR0_INFO.fields.13 10395 {"bits": [28, 28], "name": "DCC_ENABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.14 10396 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"} array in object:register_types.CB_COLOR0_INFO.fields.15 10401 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.CB_COLOR0_VIEW.fields.0 10402 {"bits": [13, 23], "name": "SLICE_MAX"}, array in object:register_types.CB_COLOR0_VIEW.fields.1 10403 {"bits": [24, 27], "name": "MIP_LEVEL"} array in object:register_types.CB_COLOR0_VIEW.fields.2 10408 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"}, array in object:register_types.CB_COLOR_CONTROL.fields.0 10409 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, array in object:register_types.CB_COLOR_CONTROL.fields.1 10410 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, array in object:register_types.CB_COLOR_CONTROL.fields.2 10411 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} array in object:register_types.CB_COLOR_CONTROL.fields.3 10416 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_DCC_CONTROL.fields.0 10417 {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"}, array in object:register_types.CB_DCC_CONTROL.fields.1 10418 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}, array in object:register_types.CB_DCC_CONTROL.fields.2 10419 {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"}, array in object:register_types.CB_DCC_CONTROL.fields.3 10420 {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"}, array in object:register_types.CB_DCC_CONTROL.fields.4 10421 {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"}, array in object:register_types.CB_DCC_CONTROL.fields.5 10422 {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"}, array in object:register_types.CB_DCC_CONTROL.fields.6 10423 {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"}, array in object:register_types.CB_DCC_CONTROL.fields.7 10424 {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"} array in object:register_types.CB_DCC_CONTROL.fields.8 10429 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.0 10430 {"bits": [10, 18], "name": "PERF_SEL1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.1 10431 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.2 10432 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.3 10433 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.4 10438 {"bits": [0, 8], "name": "PERF_SEL2"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.0 10439 {"bits": [10, 18], "name": "PERF_SEL3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.1 10440 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.2 10441 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.3 10446 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.0 10447 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.1 10452 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.0 10453 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.1 10454 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.2 10455 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.3 10456 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.4 10457 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.5 10458 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.6 10459 {"bits": [13, 15], "name": "MRT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.7 10460 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.8 10461 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.9 10462 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.10 10463 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"} array in object:register_types.CB_PERFCOUNTER_FILTER.fields.11 10468 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.0 10469 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.1 10470 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.2 10471 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.3 10472 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.4 10473 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.5 10474 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.6 10475 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} array in object:register_types.CB_SHADER_MASK.fields.7 10480 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.0 10481 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.1 10482 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.2 10483 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.3 10484 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.4 10485 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.5 10486 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.6 10487 {"bits": [28, 31], "name": "TARGET7_ENABLE"} array in object:register_types.CB_TARGET_MASK.fields.7 10492 {"bits": [0, 7], "name": "DEST_BASE_HI_256B"} array in object:register_types.COHER_DEST_BASE_HI_0.fields.0 10497 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.0 10498 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.1 10499 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.2 10500 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.3 10501 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.4 10502 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.5 10503 {"bits": [6, 6], "name": "ORDER_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.6 10504 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.7 10505 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.8 10506 {"bits": [12, 12], "name": "RESERVED"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.9 10507 {"bits": [14, 14], "name": "RESTORE"} array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.10 10512 {"bits": [0, 1], "name": "SEND_SEID"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.0 10513 {"bits": [2, 2], "name": "RESERVED2"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.1 10514 {"bits": [3, 3], "name": "RESERVED3"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.2 10515 {"bits": [4, 4], "name": "RESERVED4"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.3 10516 {"bits": [5, 16], "name": "WAVE_ID_BASE"} array in object:register_types.COMPUTE_MISC_RESERVED.fields.4 10521 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, array in object:register_types.COMPUTE_NUM_THREAD_X.fields.0 10522 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} array in object:register_types.COMPUTE_NUM_THREAD_X.fields.1 10527 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"} array in object:register_types.COMPUTE_PERFCOUNT_ENABLE.fields.0 10532 {"bits": [0, 7], "name": "DATA"} array in object:register_types.COMPUTE_PGM_HI.fields.0 10537 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.0 10538 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.1 10539 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.2 10540 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.3 10541 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.4 10542 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.5 10543 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.6 10544 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.7 10545 {"bits": [24, 24], "name": "BULKY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.8 10546 {"bits": [25, 25], "name": "CDBG_USER"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.9 10547 {"bits": [26, 26], "name": "FP16_OVFL"} array in object:register_types.COMPUTE_PGM_RSRC1.fields.10 10552 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.0 10553 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.1 10554 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.2 10555 {"bits": [7, 7], "name": "TGID_X_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.3 10556 {"bits": [8, 8], "name": "TGID_Y_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.4 10557 {"bits": [9, 9], "name": "TGID_Z_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.5 10558 {"bits": [10, 10], "name": "TG_SIZE_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.6 10559 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.7 10560 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.8 10561 {"bits": [15, 23], "name": "LDS_SIZE"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.9 10562 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.10 10563 {"bits": [31, 31], "name": "SKIP_USGPR0"} array in object:register_types.COMPUTE_PGM_RSRC2.fields.11 10568 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"} array in object:register_types.COMPUTE_PIPELINESTAT_ENABLE.fields.0 10573 {"bits": [0, 29], "name": "PAYLOAD"}, array in object:register_types.COMPUTE_RELAUNCH.fields.0 10574 {"bits": [30, 30], "name": "IS_EVENT"}, array in object:register_types.COMPUTE_RELAUNCH.fields.1 10575 {"bits": [31, 31], "name": "IS_STATE"} array in object:register_types.COMPUTE_RELAUNCH.fields.2 10580 {"bits": [0, 9], "name": "WAVES_PER_SH"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.0 10581 {"bits": [12, 15], "name": "TG_PER_CU"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.1 10582 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.2 10583 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.3 10584 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.4 10585 {"bits": [24, 26], "name": "CU_GROUP_COUNT"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.5 10586 {"bits": [27, 30], "name": "SIMD_DISABLE"} array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.6 10591 {"bits": [0, 15], "name": "SH0_CU_EN"}, array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.0 10592 {"bits": [16, 31], "name": "SH1_CU_EN"} array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.1 10597 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"} array in object:register_types.COMPUTE_THREAD_TRACE_ENABLE.fields.0 10602 {"bits": [0, 11], "name": "WAVES"}, array in object:register_types.COMPUTE_TMPRING_SIZE.fields.0 10603 {"bits": [12, 24], "name": "WAVESIZE"} array in object:register_types.COMPUTE_TMPRING_SIZE.fields.1 10608 {"bits": [0, 3], "name": "DATA"} array in object:register_types.COMPUTE_VMID.fields.0 10613 {"bits": [0, 15], "name": "ADDR"} array in object:register_types.COMPUTE_WAVE_RESTORE_ADDR_HI.fields.0 10618 {"bits": [0, 2], "name": "INDEX"}, array in object:register_types.CPC_LATENCY_STATS_SELECT.fields.0 10619 {"bits": [30, 30], "name": "CLEAR"}, array in object:register_types.CPC_LATENCY_STATS_SELECT.fields.1 10620 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPC_LATENCY_STATS_SELECT.fields.2 10625 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.0 10626 {"bits": [30, 30], "name": "CLEAR"}, array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.1 10627 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPF_LATENCY_STATS_SELECT.fields.2 10632 {"bits": [0, 2], "name": "INDEX"}, array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.0 10633 {"bits": [30, 30], "name": "ALWAYS"}, array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.1 10634 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPF_TC_PERF_COUNTER_WINDOW_SELECT.fields.2 10639 {"bits": [0, 4], "name": "INDEX"}, array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.0 10640 {"bits": [30, 30], "name": "CLEAR"}, array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.1 10641 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPG_LATENCY_STATS_SELECT.fields.2 10646 {"bits": [0, 9], "name": "CNTR_SEL2"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.0 10647 {"bits": [10, 19], "name": "CNTR_SEL3"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.1 10648 {"bits": [24, 27], "name": "CNTR_MODE3"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.2 10649 {"bits": [28, 31], "name": "CNTR_MODE2"} array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.3 10654 {"bits": [0, 9], "name": "CNTR_SEL0"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.0 10655 {"bits": [10, 19], "name": "CNTR_SEL1"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.1 10656 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.2 10657 {"bits": [24, 27], "name": "CNTR_MODE1"}, array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.3 10658 {"bits": [28, 31], "name": "CNTR_MODE0"} array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.4 10663 {"bits": [0, 4], "name": "INDEX"}, array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.0 10664 {"bits": [30, 30], "name": "ALWAYS"}, array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.1 10665 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.CPG_TC_PERF_COUNTER_WINDOW_SELECT.fields.2 10670 {"bits": [0, 15], "name": "MEM_ADDR_HI"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.0 10671 {"bits": [16, 16], "name": "CS_PS_SEL"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.1 10672 {"bits": [25, 25], "name": "CACHE_POLICY"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.2 10673 {"bits": [29, 31], "name": "COMMAND"} array in object:register_types.CP_APPEND_ADDR_HI.fields.3 10678 {"bits": [2, 31], "name": "MEM_ADDR_LO"} array in object:register_types.CP_APPEND_ADDR_LO.fields.0 10683 {"bits": [0, 15], "name": "IB1_BASE_HI"} array in object:register_types.CP_CE_IB1_BASE_HI.fields.0 10688 {"bits": [2, 31], "name": "IB1_BASE_LO"} array in object:register_types.CP_CE_IB1_BASE_LO.fields.0 10693 {"bits": [0, 19], "name": "IB1_BUFSZ"} array in object:register_types.CP_CE_IB1_BUFSZ.fields.0 10698 {"bits": [0, 19], "name": "IB1_CMD_REQSZ"} array in object:register_types.CP_CE_IB1_CMD_BUFSZ.fields.0 10703 {"bits": [0, 15], "name": "IB2_BASE_HI"} array in object:register_types.CP_CE_IB2_BASE_HI.fields.0 10708 {"bits": [2, 31], "name": "IB2_BASE_LO"} array in object:register_types.CP_CE_IB2_BASE_LO.fields.0 10713 {"bits": [0, 19], "name": "IB2_BUFSZ"} array in object:register_types.CP_CE_IB2_BUFSZ.fields.0 10718 {"bits": [0, 19], "name": "IB2_CMD_REQSZ"} array in object:register_types.CP_CE_IB2_CMD_BUFSZ.fields.0 10723 {"bits": [0, 15], "name": "INIT_BASE_HI"} array in object:register_types.CP_CE_INIT_BASE_HI.fields.0 10728 {"bits": [5, 31], "name": "INIT_BASE_LO"} array in object:register_types.CP_CE_INIT_BASE_LO.fields.0 10733 {"bits": [0, 11], "name": "INIT_BUFSZ"} array in object:register_types.CP_CE_INIT_BUFSZ.fields.0 10738 {"bits": [0, 11], "name": "INIT_CMD_REQSZ"} array in object:register_types.CP_CE_INIT_CMD_BUFSZ.fields.0 10743 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"} array in object:register_types.CP_COHER_BASE_HI.fields.0 10748 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.0 10749 {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.1 10750 {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.2 10751 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.3 10752 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.4 10753 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.5 10754 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.6 10755 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.7 10756 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.8 10757 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.9 10758 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.10 10759 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.11 10760 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"} array in object:register_types.CP_COHER_CNTL.fields.12 10765 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"} array in object:register_types.CP_COHER_SIZE_HI.fields.0 10770 {"bits": [0, 5], "name": "START_DELAY_COUNT"} array in object:register_types.CP_COHER_START_DELAY.fields.0 10775 {"bits": [24, 25], "name": "MEID"}, array in object:register_types.CP_COHER_STATUS.fields.0 10776 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_COHER_STATUS.fields.1 10781 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.0 10782 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.1 10783 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.2 10784 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.3 10785 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.4 10786 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.5 10787 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.6 10788 {"bits": [7, 7], "name": "MEC1_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.7 10789 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.8 10790 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.9 10791 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.10 10792 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.11 10793 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.12 10794 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.13 10795 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.14 10796 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.15 10797 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.16 10798 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.17 10799 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.18 10800 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.19 10801 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.20 10802 {"bits": [23, 23], "name": "MEC2_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.21 10803 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.22 10804 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.23 10805 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.24 10806 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.25 10807 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.26 10808 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"} array in object:register_types.CP_CPC_BUSY_STAT.fields.27 10813 {"bits": [0, 5], "name": "FREE_COUNT"} array in object:register_types.CP_CPC_GRBM_FREE_COUNT.fields.0 10818 {"bits": [0, 3], "name": "COUNT"} array in object:register_types.CP_CPC_HALT_HYST_COUNT.fields.0 10823 {"bits": [0, 8], "name": "SCRATCH_INDEX"} array in object:register_types.CP_CPC_SCRATCH_INDEX.fields.0 10828 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.0 10829 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.1 10830 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.2 10831 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.3 10832 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.4 10833 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.5 10834 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.6 10835 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.7 10836 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.8 10837 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.9 10838 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.10 10839 {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.11 10840 {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.12 10841 {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"} array in object:register_types.CP_CPC_STALLED_STAT1.fields.13 10846 {"bits": [0, 0], "name": "MEC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.0 10847 {"bits": [1, 1], "name": "MEC2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.1 10848 {"bits": [2, 2], "name": "DC0_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.2 10849 {"bits": [3, 3], "name": "DC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.3 10850 {"bits": [4, 4], "name": "RCIU1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.4 10851 {"bits": [5, 5], "name": "RCIU2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.5 10852 {"bits": [6, 6], "name": "ROQ1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.6 10853 {"bits": [7, 7], "name": "ROQ2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.7 10854 {"bits": [10, 10], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.8 10855 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.9 10856 {"bits": [12, 12], "name": "QU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.10 10857 {"bits": [13, 13], "name": "UTCL2IU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.11 10858 {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.12 10859 {"bits": [29, 29], "name": "CPG_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.13 10860 {"bits": [30, 30], "name": "CPF_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.14 10861 {"bits": [31, 31], "name": "CPC_BUSY"} array in object:register_types.CP_CPC_STATUS.fields.15 10866 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.0 10867 {"bits": [1, 1], "name": "CSF_RING_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.1 10868 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.2 10869 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.3 10870 {"bits": [4, 4], "name": "CSF_STATE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.4 10871 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.5 10872 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.6 10873 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.7 10874 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.8 10875 {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.9 10876 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.10 10877 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.11 10878 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.12 10879 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.13 10880 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.14 10881 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.15 10882 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.16 10883 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.17 10884 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.18 10885 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.19 10886 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.20 10887 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.21 10888 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.22 10889 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.23 10890 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.24 10891 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.25 10892 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.26 10893 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.27 10894 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.28 10895 {"bits": [30, 30], "name": "HQD_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.29 10896 {"bits": [31, 31], "name": "HQD_IB_BUSY"} array in object:register_types.CP_CPF_BUSY_STAT.fields.30 10901 {"bits": [0, 2], "name": "FREE_COUNT"} array in object:register_types.CP_CPF_GRBM_FREE_COUNT.fields.0 10906 {"bits": [0, 0], "name": "RING_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.0 10907 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.1 10908 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.2 10909 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.3 10910 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.4 10911 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.5 10912 {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.6 10913 {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.7 10914 {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.8 10915 {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.9 10916 {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"} array in object:register_types.CP_CPF_STALLED_STAT1.fields.10 10921 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.0 10922 {"bits": [1, 1], "name": "CSF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.1 10923 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.2 10924 {"bits": [5, 5], "name": "ROQ_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.3 10925 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.4 10926 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.5 10927 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.6 10928 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.7 10929 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.8 10930 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.9 10931 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.10 10932 {"bits": [13, 13], "name": "INTERRUPT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.11 10933 {"bits": [14, 14], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.12 10934 {"bits": [15, 15], "name": "HQD_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.13 10935 {"bits": [16, 16], "name": "PRT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.14 10936 {"bits": [17, 17], "name": "UTCL2IU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.15 10937 {"bits": [26, 26], "name": "CPF_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.16 10938 {"bits": [27, 27], "name": "CPF_CMP_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.17 10939 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.18 10940 {"bits": [30, 30], "name": "CPC_CPF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.19 10941 {"bits": [31, 31], "name": "CPF_BUSY"} array in object:register_types.CP_CPF_STATUS.fields.20 10946 {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"}, array in object:register_types.CP_DMA_CNTL.fields.0 10947 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, array in object:register_types.CP_DMA_CNTL.fields.1 10948 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, array in object:register_types.CP_DMA_CNTL.fields.2 10949 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, array in object:register_types.CP_DMA_CNTL.fields.3 10950 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, array in object:register_types.CP_DMA_CNTL.fields.4 10951 {"bits": [30, 31], "name": "PIO_COUNT"} array in object:register_types.CP_DMA_CNTL.fields.5 10956 {"bits": [0, 25], "name": "BYTE_COUNT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.0 10957 {"bits": [26, 26], "name": "SAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.1 10958 {"bits": [27, 27], "name": "DAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.2 10959 {"bits": [28, 28], "name": "SAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.3 10960 {"bits": [29, 29], "name": "DAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.4 10961 {"bits": [30, 30], "name": "RAW_WAIT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.5 10962 {"bits": [31, 31], "name": "DIS_WC"} array in object:register_types.CP_DMA_ME_COMMAND.fields.6 10967 {"bits": [0, 15], "name": "DST_ADDR_HI"} array in object:register_types.CP_DMA_ME_DST_ADDR_HI.fields.0 10972 {"bits": [0, 15], "name": "SRC_ADDR_HI"} array in object:register_types.CP_DMA_ME_SRC_ADDR_HI.fields.0 10977 {"bits": [10, 10], "name": "MEMLOG_CLEAR"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.0 10978 {"bits": [13, 13], "name": "SRC_CACHE_POLICY"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.1 10979 {"bits": [20, 21], "name": "DST_SELECT"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.2 10980 {"bits": [25, 25], "name": "DST_CACHE_POLICY"}, array in object:register_types.CP_DMA_PFP_CONTROL.fields.3 10981 {"bits": [29, 30], "name": "SRC_SELECT"} array in object:register_types.CP_DMA_PFP_CONTROL.fields.4 10986 {"bits": [0, 25], "name": "DMA_READ_TAG"}, array in object:register_types.CP_DMA_READ_TAGS.fields.0 10987 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} array in object:register_types.CP_DMA_READ_TAGS.fields.1 10992 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.0 10993 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.1 10994 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.2 10995 {"bits": [8, 8], "name": "MODE"} array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.3 11000 {"bits": [0, 15], "name": "MIN"}, array in object:register_types.CP_DRAW_WINDOW_LO.fields.0 11001 {"bits": [16, 31], "name": "MAX"} array in object:register_types.CP_DRAW_WINDOW_LO.fields.1 11006 {"bits": [0, 15], "name": "ADDR_HI"} array in object:register_types.CP_EOP_DONE_ADDR_HI.fields.0 11011 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.0 11016 {"bits": [16, 17], "name": "DST_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.0 11017 {"bits": [24, 26], "name": "INT_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.1 11018 {"bits": [29, 31], "name": "DATA_SEL"} array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.2 11023 {"bits": [0, 6], "name": "WBINV_TC_OP"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.0 11024 {"bits": [12, 17], "name": "WBINV_ACTION_ENA"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.1 11025 {"bits": [25, 25], "name": "CACHE_POLICY"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.2 11026 {"bits": [28, 28], "name": "EXECUTE"} array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.3 11031 {"bits": [0, 19], "name": "IB1_OFFSET"} array in object:register_types.CP_IB1_OFFSET.fields.0 11036 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} array in object:register_types.CP_IB1_PREAMBLE_BEGIN.fields.0 11041 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} array in object:register_types.CP_IB1_PREAMBLE_END.fields.0 11046 {"bits": [0, 19], "name": "IB2_OFFSET"} array in object:register_types.CP_IB2_OFFSET.fields.0 11051 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} array in object:register_types.CP_IB2_PREAMBLE_BEGIN.fields.0 11056 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} array in object:register_types.CP_IB2_PREAMBLE_END.fields.0 11061 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} array in object:register_types.CP_INDEX_TYPE.fields.0 11066 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.0 11067 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.1 11068 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.2 11069 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.3 11070 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.4 11071 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.5 11072 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.6 11073 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.7 11074 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.8 11075 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.9 11076 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.10 11077 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, array in object:register_types.CP_ME_COHER_CNTL.fields.11 11078 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"} array in object:register_types.CP_ME_COHER_CNTL.fields.12 11083 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, array in object:register_types.CP_ME_COHER_STATUS.fields.0 11084 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_ME_COHER_STATUS.fields.1 11089 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"}, array in object:register_types.CP_ME_MC_RADDR_HI.fields.0 11090 {"bits": [22, 22], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_RADDR_HI.fields.1 11095 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} array in object:register_types.CP_ME_MC_RADDR_LO.fields.0 11100 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"}, array in object:register_types.CP_ME_MC_WADDR_HI.fields.0 11101 {"bits": [22, 22], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_WADDR_HI.fields.1 11106 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} array in object:register_types.CP_ME_MC_WADDR_LO.fields.0 11111 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.0 11112 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.1 11113 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, array in object:register_types.CP_PERFMON_CNTL.fields.2 11114 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.CP_PERFMON_CNTL.fields.3 11119 {"bits": [31, 31], "name": "PERFMON_ENABLE"} array in object:register_types.CP_PERFMON_CNTX_CNTL.fields.0 11124 {"bits": [0, 1], "name": "STATUS"} array in object:register_types.CP_PFP_COMPLETION_STATUS.fields.0 11129 {"bits": [0, 7], "name": "IB_EN"} array in object:register_types.CP_PFP_IB_CONTROL.fields.0 11134 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.0 11135 {"bits": [1, 1], "name": "CNTX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.1 11136 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.2 11137 {"bits": [24, 24], "name": "SH_CS_REG_EN"} array in object:register_types.CP_PFP_LOAD_CONTROL.fields.3 11142 {"bits": [0, 1], "name": "PIPE_ID"} array in object:register_types.CP_PIPEID.fields.0 11147 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"} array in object:register_types.CP_PIPE_STATS_ADDR_HI.fields.0 11152 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.0 11157 {"bits": [25, 25], "name": "CACHE_POLICY"} array in object:register_types.CP_PIPE_STATS_CONTROL.fields.0 11162 {"bits": [0, 0], "name": "NOT_VISIBLE"} array in object:register_types.CP_PRED_NOT_VISIBLE.fields.0 11167 {"bits": [0, 19], "name": "RB_OFFSET"} array in object:register_types.CP_RB_OFFSET.fields.0 11172 {"bits": [0, 0], "name": "Z_PASS_ACITVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.0 11173 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.1 11174 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.2 11175 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.3 11176 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.4 11177 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.5 11178 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.6 11179 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"} array in object:register_types.CP_SAMPLE_STATUS.fields.7 11184 {"bits": [0, 7], "name": "SCRATCH_INDEX"} array in object:register_types.CP_SCRATCH_INDEX.fields.0 11189 {"bits": [0, 15], "name": "SEM_ADDR_HI"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.0 11190 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.1 11191 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.2 11192 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.3 11193 {"bits": [29, 31], "name": "SEM_SELECT"} array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.4 11198 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.0 11199 {"bits": [3, 31], "name": "SEM_ADDR_LO"} array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.1 11204 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"} array in object:register_types.CP_STREAM_OUT_ADDR_HI.fields.0 11209 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.0 11214 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} array in object:register_types.CP_STRMOUT_CNTL.fields.0 11219 {"bits": [0, 15], "name": "ST_BASE_HI"} array in object:register_types.CP_ST_BASE_HI.fields.0 11224 {"bits": [2, 31], "name": "ST_BASE_LO"} array in object:register_types.CP_ST_BASE_LO.fields.0 11229 {"bits": [0, 19], "name": "ST_BUFSZ"} array in object:register_types.CP_ST_BUFSZ.fields.0 11234 {"bits": [0, 19], "name": "ST_CMD_REQSZ"} array in object:register_types.CP_ST_CMD_BUFSZ.fields.0 11239 {"bits": [0, 3], "name": "VMID"} array in object:register_types.CP_VMID.fields.0 11244 {"bits": [0, 2], "name": "SRC_STATE_ID"} array in object:register_types.CS_COPY_STATE.fields.0 11249 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.0 11250 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.1 11251 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.2 11252 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.3 11253 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.4 11254 {"bits": [16, 16], "name": "OFFSET_ROUND"} array in object:register_types.DB_ALPHA_TO_MASK.fields.5 11259 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.0 11260 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.1 11261 {"bits": [4, 6], "name": "SAMPLE_RATE"}, array in object:register_types.DB_COUNT_CONTROL.fields.2 11262 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.3 11263 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.4 11264 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.5 11265 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.6 11266 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.7 11267 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} array in object:register_types.DB_COUNT_CONTROL.fields.8 11272 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.0 11273 {"bits": [1, 1], "name": "Z_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.1 11274 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.2 11275 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.3 11276 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.4 11277 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.5 11278 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.6 11279 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, array in object:register_types.DB_DEPTH_CONTROL.fields.7 11280 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, array in object:register_types.DB_DEPTH_CONTROL.fields.8 11281 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} array in object:register_types.DB_DEPTH_CONTROL.fields.9 11286 {"bits": [0, 13], "name": "X_MAX"}, array in object:register_types.DB_DEPTH_SIZE.fields.0 11287 {"bits": [16, 29], "name": "Y_MAX"} array in object:register_types.DB_DEPTH_SIZE.fields.1 11292 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.DB_DEPTH_VIEW.fields.0 11293 {"bits": [13, 23], "name": "SLICE_MAX"}, array in object:register_types.DB_DEPTH_VIEW.fields.1 11294 {"bits": [24, 24], "name": "Z_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.2 11295 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.3 11296 {"bits": [26, 29], "name": "MIPID"} array in object:register_types.DB_DEPTH_VIEW.fields.4 11301 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, array in object:register_types.DB_DFSM_CONTROL.fields.0 11302 {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"}, array in object:register_types.DB_DFSM_CONTROL.fields.1 11303 {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"} array in object:register_types.DB_DFSM_CONTROL.fields.2 11308 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, array in object:register_types.DB_EQAA.fields.0 11309 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, array in object:register_types.DB_EQAA.fields.1 11310 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.2 11311 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.3 11312 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, array in object:register_types.DB_EQAA.fields.4 11313 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, array in object:register_types.DB_EQAA.fields.5 11314 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, array in object:register_types.DB_EQAA.fields.6 11315 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, array in object:register_types.DB_EQAA.fields.7 11316 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, array in object:register_types.DB_EQAA.fields.8 11317 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, array in object:register_types.DB_EQAA.fields.9 11318 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, array in object:register_types.DB_EQAA.fields.10 11319 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} array in object:register_types.DB_EQAA.fields.11 11324 {"bits": [0, 7], "name": "BASE_HI"} array in object:register_types.DB_HTILE_DATA_BASE_HI.fields.0 11329 {"bits": [1, 1], "name": "FULL_CACHE"}, array in object:register_types.DB_HTILE_SURFACE.fields.0 11330 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, array in object:register_types.DB_HTILE_SURFACE.fields.1 11331 {"bits": [3, 3], "name": "PRELOAD"}, array in object:register_types.DB_HTILE_SURFACE.fields.2 11332 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, array in object:register_types.DB_HTILE_SURFACE.fields.3 11333 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, array in object:register_types.DB_HTILE_SURFACE.fields.4 11334 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}, array in object:register_types.DB_HTILE_SURFACE.fields.5 11335 {"bits": [18, 18], "name": "PIPE_ALIGNED"}, array in object:register_types.DB_HTILE_SURFACE.fields.6 11336 {"bits": [19, 19], "name": "RB_ALIGNED"} array in object:register_types.DB_HTILE_SURFACE.fields.7 11341 {"bits": [0, 30], "name": "COUNT_HI"} array in object:register_types.DB_OCCLUSION_COUNT0_HI.fields.0 11346 {"bits": [0, 7], "name": "START_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.0 11347 {"bits": [8, 15], "name": "START_Y"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.1 11348 {"bits": [16, 23], "name": "MAX_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.2 11349 {"bits": [24, 31], "name": "MAX_Y"} array in object:register_types.DB_PRELOAD_CONTROL.fields.3 11354 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.0 11355 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.1 11356 {"bits": [2, 2], "name": "DEPTH_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.2 11357 {"bits": [3, 3], "name": "STENCIL_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.3 11358 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.4 11359 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.5 11360 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.6 11361 {"bits": [7, 7], "name": "COPY_CENTROID"}, array in object:register_types.DB_RENDER_CONTROL.fields.7 11362 {"bits": [8, 11], "name": "COPY_SAMPLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.8 11363 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"} array in object:register_types.DB_RENDER_CONTROL.fields.9 11368 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.0 11369 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.1 11370 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.2 11371 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.3 11372 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.4 11373 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.5 11374 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.6 11375 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.7 11376 {"bits": [11, 11], "name": "FORCE_Z_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.8 11377 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.9 11378 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.10 11379 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.11 11380 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.12 11381 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.13 11382 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.14 11383 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.15 11384 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.16 11385 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.17 11386 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.18 11387 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.19 11388 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.20 11389 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.21 11390 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} array in object:register_types.DB_RENDER_OVERRIDE.fields.22 11395 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.0 11396 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.1 11397 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.2 11398 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.3 11399 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.4 11400 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.5 11401 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.6 11402 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.7 11403 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.8 11404 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.9 11405 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.10 11406 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.11 11407 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.12 11408 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.13 11409 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.14 11410 {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"} array in object:register_types.DB_RENDER_OVERRIDE2.fields.15 11415 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.0 11416 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.1 11417 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.2 11418 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, array in object:register_types.DB_SHADER_CONTROL.fields.3 11419 {"bits": [6, 6], "name": "KILL_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.4 11420 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.5 11421 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.6 11422 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, array in object:register_types.DB_SHADER_CONTROL.fields.7 11423 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, array in object:register_types.DB_SHADER_CONTROL.fields.8 11424 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.9 11425 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.10 11426 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, array in object:register_types.DB_SHADER_CONTROL.fields.11 11427 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.12 11428 {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.13 11429 {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"}, array in object:register_types.DB_SHADER_CONTROL.fields.14 11430 {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"} array in object:register_types.DB_SHADER_CONTROL.fields.15 11435 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0 11436 {"bits": [4, 11], "name": "COMPAREVALUE0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.1 11437 {"bits": [12, 19], "name": "COMPAREMASK0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.2 11438 {"bits": [24, 24], "name": "ENABLE0"} array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.3 11443 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0 11444 {"bits": [4, 11], "name": "COMPAREVALUE1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.1 11445 {"bits": [12, 19], "name": "COMPAREMASK1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.2 11446 {"bits": [24, 24], "name": "ENABLE1"} array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.3 11451 {"bits": [0, 7], "name": "STENCILTESTVAL"}, array in object:register_types.DB_STENCILREFMASK.fields.0 11452 {"bits": [8, 15], "name": "STENCILMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.1 11453 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.2 11454 {"bits": [24, 31], "name": "STENCILOPVAL"} array in object:register_types.DB_STENCILREFMASK.fields.3 11459 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.0 11460 {"bits": [8, 15], "name": "STENCILMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.1 11461 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.2 11462 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} array in object:register_types.DB_STENCILREFMASK_BF.fields.3 11467 {"bits": [0, 7], "name": "CLEAR"} array in object:register_types.DB_STENCIL_CLEAR.fields.0 11472 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.0 11473 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, array in object:register_types.DB_STENCIL_CONTROL.fields.1 11474 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.2 11475 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.3 11476 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.4 11477 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} array in object:register_types.DB_STENCIL_CONTROL.fields.5 11482 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, array in object:register_types.DB_STENCIL_INFO.fields.0 11483 {"bits": [4, 8], "name": "SW_MODE"}, array in object:register_types.DB_STENCIL_INFO.fields.1 11484 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, array in object:register_types.DB_STENCIL_INFO.fields.2 11485 {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, array in object:register_types.DB_STENCIL_INFO.fields.3 11486 {"bits": [15, 15], "name": "ITERATE_FLUSH"}, array in object:register_types.DB_STENCIL_INFO.fields.4 11487 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_STENCIL_INFO.fields.5 11488 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}, array in object:register_types.DB_STENCIL_INFO.fields.6 11489 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"} array in object:register_types.DB_STENCIL_INFO.fields.7 11494 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, array in object:register_types.DB_Z_INFO.fields.0 11495 {"bits": [2, 3], "name": "NUM_SAMPLES"}, array in object:register_types.DB_Z_INFO.fields.1 11496 {"bits": [4, 8], "name": "SW_MODE"}, array in object:register_types.DB_Z_INFO.fields.2 11497 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, array in object:register_types.DB_Z_INFO.fields.3 11498 {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, array in object:register_types.DB_Z_INFO.fields.4 11499 {"bits": [15, 15], "name": "ITERATE_FLUSH"}, array in object:register_types.DB_Z_INFO.fields.5 11500 {"bits": [16, 19], "name": "MAXMIP"}, array in object:register_types.DB_Z_INFO.fields.6 11501 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"}, array in object:register_types.DB_Z_INFO.fields.7 11502 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_Z_INFO.fields.8 11503 {"bits": [28, 28], "name": "READ_SIZE"}, array in object:register_types.DB_Z_INFO.fields.9 11504 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, array in object:register_types.DB_Z_INFO.fields.10 11505 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}, array in object:register_types.DB_Z_INFO.fields.11 11506 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} array in object:register_types.DB_Z_INFO.fields.12 11511 {"bits": [0, 15], "name": "EPITCH"} array in object:register_types.DB_Z_INFO2.fields.0 11516 {"bits": [0, 2], "name": "NUM_PIPES"}, array in object:register_types.GB_ADDR_CONFIG.fields.0 11517 {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.1 11518 {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"}, array in object:register_types.GB_ADDR_CONFIG.fields.2 11519 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.3 11520 {"bits": [12, 14], "enum_ref": "NumBanks", "name": "NUM_BANKS"}, array in object:register_types.GB_ADDR_CONFIG.fields.4 11521 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.5 11522 {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"}, array in object:register_types.GB_ADDR_CONFIG.fields.6 11523 {"bits": [21, 23], "name": "NUM_GPUS"}, array in object:register_types.GB_ADDR_CONFIG.fields.7 11524 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.8 11525 {"bits": [26, 27], "name": "NUM_RB_PER_SE"}, array in object:register_types.GB_ADDR_CONFIG.fields.9 11526 {"bits": [28, 29], "name": "ROW_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.10 11527 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}, array in object:register_types.GB_ADDR_CONFIG.fields.11 11528 {"bits": [31, 31], "name": "SE_ENABLE"} array in object:register_types.GB_ADDR_CONFIG.fields.12 11533 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, array in object:register_types.GB_MACROTILE_MODE0.fields.0 11534 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.1 11535 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.2 11536 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} array in object:register_types.GB_MACROTILE_MODE0.fields.3 11541 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.GB_TILE_MODE0.fields.0 11542 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.GB_TILE_MODE0.fields.1 11543 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.GB_TILE_MODE0.fields.2 11544 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, array in object:register_types.GB_TILE_MODE0.fields.3 11545 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} array in object:register_types.GB_TILE_MODE0.fields.4 11550 {"bits": [0, 15], "name": "BASE"}, array in object:register_types.GDS_ATOM_BASE.fields.0 11551 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_BASE.fields.1 11556 {"bits": [0, 5], "name": "AINC"}, array in object:register_types.GDS_ATOM_CNTL.fields.0 11557 {"bits": [6, 7], "name": "UNUSED1"}, array in object:register_types.GDS_ATOM_CNTL.fields.1 11558 {"bits": [8, 9], "name": "DMODE"}, array in object:register_types.GDS_ATOM_CNTL.fields.2 11559 {"bits": [10, 31], "name": "UNUSED2"} array in object:register_types.GDS_ATOM_CNTL.fields.3 11564 {"bits": [0, 0], "name": "COMPLETE"}, array in object:register_types.GDS_ATOM_COMPLETE.fields.0 11565 {"bits": [1, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_COMPLETE.fields.1 11570 {"bits": [0, 7], "name": "OFFSET0"}, array in object:register_types.GDS_ATOM_OFFSET0.fields.0 11571 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET0.fields.1 11576 {"bits": [0, 7], "name": "OFFSET1"}, array in object:register_types.GDS_ATOM_OFFSET1.fields.0 11577 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET1.fields.1 11582 {"bits": [0, 7], "name": "OP"}, array in object:register_types.GDS_ATOM_OP.fields.0 11583 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OP.fields.1 11588 {"bits": [0, 15], "name": "SIZE"}, array in object:register_types.GDS_ATOM_SIZE.fields.0 11589 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_SIZE.fields.1 11594 {"bits": [0, 0], "name": "FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.0 11595 {"bits": [1, 12], "name": "COUNTER"}, array in object:register_types.GDS_GWS_RESOURCE.fields.1 11596 {"bits": [13, 13], "name": "TYPE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.2 11597 {"bits": [14, 14], "name": "DED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.3 11598 {"bits": [15, 15], "name": "RELEASE_ALL"}, array in object:register_types.GDS_GWS_RESOURCE.fields.4 11599 {"bits": [16, 27], "name": "HEAD_QUEUE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.5 11600 {"bits": [28, 28], "name": "HEAD_VALID"}, array in object:register_types.GDS_GWS_RESOURCE.fields.6 11601 {"bits": [29, 29], "name": "HEAD_FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.7 11602 {"bits": [30, 30], "name": "HALTED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.8 11603 {"bits": [31, 31], "name": "UNUSED1"} array in object:register_types.GDS_GWS_RESOURCE.fields.9 11608 {"bits": [0, 15], "name": "RESOURCE_CNT"}, array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.0 11609 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.1 11614 {"bits": [0, 5], "name": "INDEX"}, array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.0 11615 {"bits": [6, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.1 11620 {"bits": [0, 15], "name": "DS_ADDRESS"}, array in object:register_types.GDS_OA_ADDRESS.fields.0 11621 {"bits": [16, 19], "name": "CRAWLER"}, array in object:register_types.GDS_OA_ADDRESS.fields.1 11622 {"bits": [20, 21], "name": "CRAWLER_TYPE"}, array in object:register_types.GDS_OA_ADDRESS.fields.2 11623 {"bits": [22, 29], "name": "UNUSED"}, array in object:register_types.GDS_OA_ADDRESS.fields.3 11624 {"bits": [30, 30], "name": "NO_ALLOC"}, array in object:register_types.GDS_OA_ADDRESS.fields.4 11625 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.GDS_OA_ADDRESS.fields.5 11630 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.GDS_OA_CNTL.fields.0 11631 {"bits": [4, 31], "name": "UNUSED"} array in object:register_types.GDS_OA_CNTL.fields.1 11636 {"bits": [0, 30], "name": "VALUE"}, array in object:register_types.GDS_OA_INCDEC.fields.0 11637 {"bits": [31, 31], "name": "INCDEC"} array in object:register_types.GDS_OA_INCDEC.fields.1 11642 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.0 11643 {"bits": [8, 15], "name": "SH_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.1 11644 {"bits": [16, 23], "name": "SE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.2 11645 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.3 11646 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.4 11647 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} array in object:register_types.GRBM_GFX_INDEX.fields.5 11652 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.0 11653 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.1 11654 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.2 11655 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.3 11656 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.4 11657 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.5 11658 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.6 11659 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.7 11660 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.8 11661 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.9 11662 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.10 11663 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.11 11664 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.12 11665 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.13 11666 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.14 11667 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.15 11668 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.16 11669 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.17 11670 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.18 11671 {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.19 11672 {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.20 11673 {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.21 11678 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.0 11679 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.1 11680 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.2 11681 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.3 11682 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.4 11683 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.5 11684 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.6 11685 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.7 11686 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.8 11687 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.9 11688 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.10 11689 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.11 11690 {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.12 11695 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS.fields.0 11696 {"bits": [5, 5], "name": "RSMU_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.1 11697 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.2 11698 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.3 11699 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.4 11700 {"bits": [12, 12], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.5 11701 {"bits": [13, 13], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.6 11702 {"bits": [14, 14], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.7 11703 {"bits": [15, 15], "name": "GDS_BUSY"}, array in object:register_types.GRBM_STATUS.fields.8 11704 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.9 11705 {"bits": [17, 17], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS.fields.10 11706 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.11 11707 {"bits": [19, 19], "name": "IA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.12 11708 {"bits": [20, 20], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS.fields.13 11709 {"bits": [21, 21], "name": "WD_BUSY"}, array in object:register_types.GRBM_STATUS.fields.14 11710 {"bits": [22, 22], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.15 11711 {"bits": [23, 23], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.16 11712 {"bits": [24, 24], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS.fields.17 11713 {"bits": [25, 25], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.18 11714 {"bits": [26, 26], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.19 11715 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, array in object:register_types.GRBM_STATUS.fields.20 11716 {"bits": [29, 29], "name": "CP_BUSY"}, array in object:register_types.GRBM_STATUS.fields.21 11717 {"bits": [30, 30], "name": "CB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.22 11718 {"bits": [31, 31], "name": "GUI_ACTIVE"} array in object:register_types.GRBM_STATUS.fields.23 11723 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS2.fields.0 11724 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.1 11725 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.2 11726 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.3 11727 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.4 11728 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.5 11729 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.6 11730 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.7 11731 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.8 11732 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.9 11733 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.10 11734 {"bits": [14, 14], "name": "RLC_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.11 11735 {"bits": [15, 15], "name": "UTCL2_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.12 11736 {"bits": [16, 16], "name": "EA_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.13 11737 {"bits": [17, 17], "name": "RMI_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.14 11738 {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.15 11739 {"bits": [19, 19], "name": "CPF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.16 11740 {"bits": [20, 20], "name": "EA_LINK_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.17 11741 {"bits": [24, 24], "name": "RLC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.18 11742 {"bits": [25, 25], "name": "TC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.19 11743 {"bits": [26, 26], "name": "TCC_CC_RESIDENT"}, array in object:register_types.GRBM_STATUS2.fields.20 11744 {"bits": [28, 28], "name": "CPF_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.21 11745 {"bits": [29, 29], "name": "CPC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.22 11746 {"bits": [30, 30], "name": "CPG_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.23 11747 {"bits": [31, 31], "name": "CPAXI_BUSY"} array in object:register_types.GRBM_STATUS2.fields.24 11752 {"bits": [1, 1], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.0 11753 {"bits": [2, 2], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.1 11754 {"bits": [21, 21], "name": "RMI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.2 11755 {"bits": [22, 22], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.3 11756 {"bits": [23, 23], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.4 11757 {"bits": [24, 24], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.5 11758 {"bits": [25, 25], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.6 11759 {"bits": [26, 26], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.7 11760 {"bits": [27, 27], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.8 11761 {"bits": [29, 29], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.9 11762 {"bits": [30, 30], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.10 11763 {"bits": [31, 31], "name": "CB_BUSY"} array in object:register_types.GRBM_STATUS_SE0.fields.11 11768 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.0 11769 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.1 11770 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.2 11771 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.3 11772 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.4 11773 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.5 11774 {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.6 11775 {"bits": [22, 22], "name": "EN_INST_OPT_ADV"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.7 11776 {"bits": [23, 23], "name": "HW_USE_ONLY"} array in object:register_types.IA_MULTI_VGT_PARAM.fields.8 11781 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.0 11782 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.1 11783 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.2 11784 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.3 11785 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.IA_PERFCOUNTER0_SELECT.fields.4 11790 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.IA_PERFCOUNTER0_SELECT1.fields.0 11791 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.IA_PERFCOUNTER0_SELECT1.fields.1 11792 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.IA_PERFCOUNTER0_SELECT1.fields.2 11793 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.IA_PERFCOUNTER0_SELECT1.fields.3 11798 {"bits": [0, 0], "name": "UCP_ENA_0"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.0 11799 {"bits": [1, 1], "name": "UCP_ENA_1"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.1 11800 {"bits": [2, 2], "name": "UCP_ENA_2"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.2 11801 {"bits": [3, 3], "name": "UCP_ENA_3"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.3 11802 {"bits": [4, 4], "name": "UCP_ENA_4"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.4 11803 {"bits": [5, 5], "name": "UCP_ENA_5"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.5 11804 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.6 11805 {"bits": [14, 15], "name": "PS_UCP_MODE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.7 11806 {"bits": [16, 16], "name": "CLIP_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.8 11807 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.9 11808 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.10 11809 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.11 11810 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.12 11811 {"bits": [21, 21], "name": "VTX_KILL_OR"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.13 11812 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.14 11813 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.15 11814 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.16 11815 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.17 11816 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.18 11817 {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"} array in object:register_types.PA_CL_CLIP_CNTL.fields.19 11822 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.0 11823 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.1 11824 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.2 11825 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.3 11826 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.4 11827 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.5 11828 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.6 11829 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.7 11830 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.8 11831 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.9 11832 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.10 11833 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.11 11834 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.12 11835 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.13 11836 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.14 11837 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} array in object:register_types.PA_CL_NANINF_CNTL.fields.15 11842 {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"}, array in object:register_types.PA_CL_NGG_CNTL.fields.0 11843 {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"} array in object:register_types.PA_CL_NGG_CNTL.fields.1 11848 {"bits": [0, 0], "name": "OBJ_ID_SEL"}, array in object:register_types.PA_CL_OBJPRIM_ID_CNTL.fields.0 11849 {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"}, array in object:register_types.PA_CL_OBJPRIM_ID_CNTL.fields.1 11850 {"bits": [2, 2], "name": "EN_32BIT_OBJPRIMID"} array in object:register_types.PA_CL_OBJPRIM_ID_CNTL.fields.2 11855 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.0 11856 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.1 11857 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.2 11858 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.3 11859 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.4 11860 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.5 11861 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.6 11862 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.7 11863 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.8 11864 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.9 11865 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.10 11866 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.11 11867 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.12 11868 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.13 11869 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.14 11870 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.15 11871 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.16 11872 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.17 11873 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.18 11874 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.19 11875 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.20 11876 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.21 11877 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.22 11878 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.23 11879 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.24 11880 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.25 11881 {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.26 11882 {"bits": [27, 27], "name": "USE_VTX_SHD_OBJPRIM_ID"} array in object:register_types.PA_CL_VS_OUT_CNTL.fields.27 11887 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.0 11888 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.1 11889 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.2 11890 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.3 11891 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.4 11892 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.5 11893 {"bits": [8, 8], "name": "VTX_XY_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.6 11894 {"bits": [9, 9], "name": "VTX_Z_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.7 11895 {"bits": [10, 10], "name": "VTX_W0_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.8 11896 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} array in object:register_types.PA_CL_VTE_CNTL.fields.9 11901 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.0 11902 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, array in object:register_types.PA_SC_AA_CONFIG.fields.1 11903 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, array in object:register_types.PA_SC_AA_CONFIG.fields.2 11904 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.3 11905 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}, array in object:register_types.PA_SC_AA_CONFIG.fields.4 11906 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"} array in object:register_types.PA_SC_AA_CONFIG.fields.5 11911 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.0 11912 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.1 11917 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.0 11918 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.1 11923 {"bits": [0, 3], "name": "S0_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.0 11924 {"bits": [4, 7], "name": "S0_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.1 11925 {"bits": [8, 11], "name": "S1_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.2 11926 {"bits": [12, 15], "name": "S1_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.3 11927 {"bits": [16, 19], "name": "S2_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.4 11928 {"bits": [20, 23], "name": "S2_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.5 11929 {"bits": [24, 27], "name": "S3_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.6 11930 {"bits": [28, 31], "name": "S3_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.7 11935 {"bits": [0, 3], "name": "S4_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.0 11936 {"bits": [4, 7], "name": "S4_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.1 11937 {"bits": [8, 11], "name": "S5_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.2 11938 {"bits": [12, 15], "name": "S5_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.3 11939 {"bits": [16, 19], "name": "S6_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.4 11940 {"bits": [20, 23], "name": "S6_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.5 11941 {"bits": [24, 27], "name": "S7_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.6 11942 {"bits": [28, 31], "name": "S7_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.7 11947 {"bits": [0, 3], "name": "S8_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.0 11948 {"bits": [4, 7], "name": "S8_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.1 11949 {"bits": [8, 11], "name": "S9_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.2 11950 {"bits": [12, 15], "name": "S9_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.3 11951 {"bits": [16, 19], "name": "S10_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.4 11952 {"bits": [20, 23], "name": "S10_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.5 11953 {"bits": [24, 27], "name": "S11_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.6 11954 {"bits": [28, 31], "name": "S11_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.7 11959 {"bits": [0, 3], "name": "S12_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.0 11960 {"bits": [4, 7], "name": "S12_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.1 11961 {"bits": [8, 11], "name": "S13_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.2 11962 {"bits": [12, 15], "name": "S13_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.3 11963 {"bits": [16, 19], "name": "S14_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.4 11964 {"bits": [20, 23], "name": "S14_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.5 11965 {"bits": [24, 27], "name": "S15_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.6 11966 {"bits": [28, 31], "name": "S15_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.7 11971 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.0 11972 {"bits": [2, 2], "name": "BIN_SIZE_X"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.1 11973 {"bits": [3, 3], "name": "BIN_SIZE_Y"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.2 11974 {"bits": [4, 6], "name": "BIN_SIZE_X_EXTEND"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.3 11975 {"bits": [7, 9], "name": "BIN_SIZE_Y_EXTEND"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.4 11976 {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.5 11977 {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.6 11978 {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.7 11979 {"bits": [19, 26], "name": "FPOVS_PER_BATCH"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.8 11980 {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"}, array in object:register_types.PA_SC_BINNER_CNTL_0.fields.9 11981 {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"} array in object:register_types.PA_SC_BINNER_CNTL_0.fields.10 11986 {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"}, array in object:register_types.PA_SC_BINNER_CNTL_1.fields.0 11987 {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"} array in object:register_types.PA_SC_BINNER_CNTL_1.fields.1 11992 {"bits": [0, 3], "name": "DISTANCE_0"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.0 11993 {"bits": [4, 7], "name": "DISTANCE_1"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.1 11994 {"bits": [8, 11], "name": "DISTANCE_2"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.2 11995 {"bits": [12, 15], "name": "DISTANCE_3"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.3 11996 {"bits": [16, 19], "name": "DISTANCE_4"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.4 11997 {"bits": [20, 23], "name": "DISTANCE_5"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.5 11998 {"bits": [24, 27], "name": "DISTANCE_6"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.6 11999 {"bits": [28, 31], "name": "DISTANCE_7"} array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.7 12004 {"bits": [0, 3], "name": "DISTANCE_8"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.0 12005 {"bits": [4, 7], "name": "DISTANCE_9"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.1 12006 {"bits": [8, 11], "name": "DISTANCE_10"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.2 12007 {"bits": [12, 15], "name": "DISTANCE_11"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.3 12008 {"bits": [16, 19], "name": "DISTANCE_12"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.4 12009 {"bits": [20, 23], "name": "DISTANCE_13"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.5 12010 {"bits": [24, 27], "name": "DISTANCE_14"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.6 12011 {"bits": [28, 31], "name": "DISTANCE_15"} array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.7 12016 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.0 12017 {"bits": [16, 30], "name": "TL_Y"} array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.1 12022 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} array in object:register_types.PA_SC_CLIPRECT_RULE.fields.0 12027 {"bits": [0, 0], "name": "OVER_RAST_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.0 12028 {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.1 12029 {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.2 12030 {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.3 12031 {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.4 12032 {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.5 12033 {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.6 12034 {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.7 12035 {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.8 12036 {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.9 12037 {"bits": [16, 17], "name": "UNCERTAINTY_REGION_MODE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.10 12038 {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.11 12039 {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.12 12040 {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.13 12041 {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.14 12042 {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.15 12043 {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"}, array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.16 12044 {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"} array in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.17 12049 {"bits": [0, 3], "name": "ER_TRI"}, array in object:register_types.PA_SC_EDGERULE.fields.0 12050 {"bits": [4, 7], "name": "ER_POINT"}, array in object:register_types.PA_SC_EDGERULE.fields.1 12051 {"bits": [8, 11], "name": "ER_RECT"}, array in object:register_types.PA_SC_EDGERULE.fields.2 12052 {"bits": [12, 17], "name": "ER_LINE_LR"}, array in object:register_types.PA_SC_EDGERULE.fields.3 12053 {"bits": [18, 23], "name": "ER_LINE_RL"}, array in object:register_types.PA_SC_EDGERULE.fields.4 12054 {"bits": [24, 27], "name": "ER_LINE_TB"}, array in object:register_types.PA_SC_EDGERULE.fields.5 12055 {"bits": [28, 31], "name": "ER_LINE_BT"} array in object:register_types.PA_SC_EDGERULE.fields.6 12060 {"bits": [0, 7], "name": "TOP_QTR"}, array in object:register_types.PA_SC_HORIZ_GRID.fields.0 12061 {"bits": [8, 15], "name": "TOP_HALF"}, array in object:register_types.PA_SC_HORIZ_GRID.fields.1 12062 {"bits": [16, 23], "name": "BOT_HALF"}, array in object:register_types.PA_SC_HORIZ_GRID.fields.2 12063 {"bits": [24, 31], "name": "BOT_QTR"} array in object:register_types.PA_SC_HORIZ_GRID.fields.3 12068 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, array in object:register_types.PA_SC_LINE_CNTL.fields.0 12069 {"bits": [10, 10], "name": "LAST_PIXEL"}, array in object:register_types.PA_SC_LINE_CNTL.fields.1 12070 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.2 12071 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.3 12072 {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"} array in object:register_types.PA_SC_LINE_CNTL.fields.4 12077 {"bits": [0, 15], "name": "LINE_PATTERN"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.0 12078 {"bits": [16, 23], "name": "REPEAT_COUNT"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.1 12079 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.2 12080 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} array in object:register_types.PA_SC_LINE_STIPPLE.fields.3 12085 {"bits": [0, 3], "name": "CURRENT_PTR"}, array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.0 12086 {"bits": [8, 15], "name": "CURRENT_COUNT"} array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.1 12091 {"bits": [0, 0], "name": "MSAA_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.0 12092 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.1 12093 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.2 12094 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.3 12095 {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.4 12096 {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.5 12097 {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"} array in object:register_types.PA_SC_MODE_CNTL_0.fields.6 12102 {"bits": [0, 0], "name": "WALK_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.0 12103 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.1 12104 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.2 12105 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.3 12106 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.4 12107 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.5 12108 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.6 12109 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.7 12110 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.8 12111 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.9 12112 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.10 12113 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.11 12114 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.12 12115 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.13 12116 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.14 12117 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.15 12118 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.16 12119 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.17 12120 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.18 12121 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.19 12122 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.20 12123 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.21 12124 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.22 12125 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} array in object:register_types.PA_SC_MODE_CNTL_1.fields.23 12130 {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"} array in object:register_types.PA_SC_NGG_MODE_CNTL.fields.0 12135 {"bits": [0, 13], "name": "X_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_H.fields.0 12140 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"}, array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.0 12141 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.1 12146 {"bits": [0, 15], "name": "COUNT"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_OCCURRENCE.fields.0 12151 {"bits": [0, 13], "name": "Y_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_V.fields.0 12156 {"bits": [0, 9], "name": "PERF_SEL"} array in object:register_types.PA_SC_PERFCOUNTER1_SELECT.fields.0 12161 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.0 12162 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.1 12163 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.2 12164 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.3 12165 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.4 12166 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.5 12167 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.6 12168 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.7 12169 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.8 12170 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.9 12171 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.10 12172 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.11 12173 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.12 12174 {"bits": [26, 28], "enum_ref": "SeXsel", "name": "SE_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.13 12175 {"bits": [29, 31], "enum_ref": "SeYsel", "name": "SE_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG.fields.14 12180 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0 12181 {"bits": [2, 4], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1 12182 {"bits": [5, 7], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2 12187 {"bits": [0, 7], "name": "LEFT_QTR"}, array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.0 12188 {"bits": [8, 15], "name": "LEFT_HALF"}, array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.1 12189 {"bits": [16, 23], "name": "RIGHT_HALF"}, array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.2 12190 {"bits": [24, 31], "name": "RIGHT_QTR"} array in object:register_types.PA_SC_RIGHT_VERT_GRID.fields.3 12195 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.0 12196 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"} array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.1 12201 {"bits": [0, 15], "name": "X"}, array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.0 12202 {"bits": [16, 31], "name": "Y"} array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.1 12207 {"bits": [0, 15], "name": "BR_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.0 12208 {"bits": [16, 31], "name": "BR_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.1 12213 {"bits": [0, 15], "name": "TL_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.0 12214 {"bits": [16, 31], "name": "TL_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.1 12219 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.0 12220 {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"}, array in object:register_types.PA_SC_SHADER_CONTROL.fields.1 12221 {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"} array in object:register_types.PA_SC_SHADER_CONTROL.fields.2 12226 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.0 12227 {"bits": [1, 2], "name": "NUM_SE"}, array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.1 12228 {"bits": [5, 6], "name": "NUM_RB_PER_SE"} array in object:register_types.PA_SC_TILE_STEERING_OVERRIDE.fields.2 12233 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, array in object:register_types.PA_SC_WINDOW_OFFSET.fields.0 12234 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} array in object:register_types.PA_SC_WINDOW_OFFSET.fields.1 12239 {"bits": [0, 14], "name": "BR_X"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_BR.fields.0 12240 {"bits": [16, 30], "name": "BR_Y"} array in object:register_types.PA_SC_WINDOW_SCISSOR_BR.fields.1 12245 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.0 12246 {"bits": [16, 30], "name": "TL_Y"}, array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.1 12247 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} array in object:register_types.PA_SC_WINDOW_SCISSOR_TL.fields.2 12252 {"bits": [0, 0], "name": "EN_STEREO"}, array in object:register_types.PA_STEREO_CNTL.fields.0 12253 {"bits": [1, 4], "name": "STEREO_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.1 12254 {"bits": [5, 7], "name": "RT_SLICE_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.2 12255 {"bits": [8, 9], "name": "RT_SLICE_OFFSET"}, array in object:register_types.PA_STEREO_CNTL.fields.3 12256 {"bits": [10, 12], "name": "VP_ID_MODE"}, array in object:register_types.PA_STEREO_CNTL.fields.4 12257 {"bits": [13, 16], "name": "VP_ID_OFFSET"} array in object:register_types.PA_STEREO_CNTL.fields.5 12262 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.0 12263 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.1 12268 {"bits": [0, 15], "name": "WIDTH"} array in object:register_types.PA_SU_LINE_CNTL.fields.0 12273 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.0 12274 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.1 12275 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.2 12276 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.3 12281 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} array in object:register_types.PA_SU_LINE_STIPPLE_VALUE.fields.0 12286 {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.0 12287 {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.1 12288 {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.2 12289 {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"}, array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.3 12290 {"bits": [4, 4], "name": "USE_PROVOKING_ZW"} array in object:register_types.PA_SU_OVER_RASTERIZATION_CNTL.fields.4 12295 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} array in object:register_types.PA_SU_PERFCOUNTER0_HI.fields.0 12300 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.0 12301 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.1 12302 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.2 12307 {"bits": [0, 15], "name": "MIN_SIZE"}, array in object:register_types.PA_SU_POINT_MINMAX.fields.0 12308 {"bits": [16, 31], "name": "MAX_SIZE"} array in object:register_types.PA_SU_POINT_MINMAX.fields.1 12313 {"bits": [0, 15], "name": "HEIGHT"}, array in object:register_types.PA_SU_POINT_SIZE.fields.0 12314 {"bits": [16, 31], "name": "WIDTH"} array in object:register_types.PA_SU_POINT_SIZE.fields.1 12319 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.0 12320 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.1 12325 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.0 12326 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.1 12327 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.2 12328 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.3 12329 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.4 12330 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.5 12331 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.6 12332 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.7 12333 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.8 12334 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.9 12335 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.10 12340 {"bits": [0, 0], "name": "CULL_FRONT"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.0 12341 {"bits": [1, 1], "name": "CULL_BACK"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.1 12342 {"bits": [2, 2], "name": "FACE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.2 12343 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.3 12344 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ array in object:register_types.PA_SU_SC_MODE_CNTL.fields.4 12345 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE array in object:register_types.PA_SU_SC_MODE_CNTL.fields.5 12346 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.6 12347 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.7 12348 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.8 12349 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.9 12350 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.10 12351 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.11 12352 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.12 12353 {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.13 12354 {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"} array in object:register_types.PA_SU_SC_MODE_CNTL.fields.14 12359 {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.0 12360 {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.1 12361 {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.2 12362 {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.3 12363 {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.4 12364 {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"} array in object:register_types.PA_SU_SMALL_PRIM_FILTER_CNTL.fields.5 12369 {"bits": [0, 0], "name": "PIX_CENTER"}, array in object:register_types.PA_SU_VTX_CNTL.fields.0 12370 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, array in object:register_types.PA_SU_VTX_CNTL.fields.1 12371 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} array in object:register_types.PA_SU_VTX_CNTL.fields.2 12376 {"bits": [0, 3], "name": "FEATURE_SEL"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.0 12377 {"bits": [4, 7], "name": "SE_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.1 12378 {"bits": [8, 11], "name": "SH_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.2 12379 {"bits": [12, 15], "name": "CU_INDEX"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.3 12380 {"bits": [16, 17], "name": "EVENT_SEL"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.4 12381 {"bits": [18, 19], "name": "UNUSED"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.5 12382 {"bits": [20, 20], "name": "ENABLE"}, array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.6 12383 {"bits": [21, 31], "name": "RESERVED"} array in object:register_types.RLC_GPM_PERF_COUNT_0.fields.7 12388 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.0 12389 {"bits": [1, 1], "name": "MODE_SELECT"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.1 12390 {"bits": [2, 2], "name": "RESET"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.2 12391 {"bits": [3, 31], "name": "RESERVED"} array in object:register_types.RLC_GPU_IOV_PERF_CNT_CNTL.fields.3 12396 {"bits": [0, 3], "name": "VFID"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.0 12397 {"bits": [4, 5], "name": "CNT_ID"}, array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.1 12398 {"bits": [6, 31], "name": "RESERVED"} array in object:register_types.RLC_GPU_IOV_PERF_CNT_WR_ADDR.fields.2 12403 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"} array in object:register_types.RLC_PERFCOUNTER0_SELECT.fields.0 12408 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"} array in object:register_types.RLC_PERFMON_CLK_CNTL_UCODE.fields.0 12413 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.RLC_PERFMON_CNTL.fields.0 12414 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.RLC_PERFMON_CNTL.fields.1 12419 {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"}, array in object:register_types.RLC_SPM_CPG_PERFMON_SAMPLE_DELAY.fields.0 12420 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_CPG_PERFMON_SAMPLE_DELAY.fields.1 12425 {"bits": [0, 11], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.0 12426 {"bits": [12, 13], "name": "PERFMON_RING_MODE"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.1 12427 {"bits": [14, 15], "name": "RESERVED"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.2 12428 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"} array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.3 12433 {"bits": [0, 15], "name": "RING_BASE_HI"}, array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.0 12434 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.1 12439 {"bits": [0, 7], "name": "PERFMON_MAX_SAMPLE_DELAY"}, array in object:register_types.RLC_SPM_PERFMON_SAMPLE_DELAY_MAX.fields.0 12440 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_SAMPLE_DELAY_MAX.fields.1 12445 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.0 12446 {"bits": [8, 10], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.1 12447 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.2 12448 {"bits": [16, 20], "name": "SE0_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.3 12449 {"bits": [21, 25], "name": "SE1_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.4 12450 {"bits": [26, 30], "name": "SE2_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.5 12451 {"bits": [31, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.6 12456 {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.0 12457 {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.1 12458 {"bits": [4, 5], "name": "TC_PERF_EN_SEL"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.2 12459 {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.3 12460 {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.4 12461 {"bits": [10, 13], "name": "PERF_COUNTER_CID"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.5 12462 {"bits": [14, 18], "name": "PERF_COUNTER_VMID"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.6 12463 {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.7 12464 {"bits": [25, 25], "name": "PERF_SOFT_RESET"}, array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.8 12465 {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"} array in object:register_types.RMI_PERF_COUNTER_CNTL.fields.9 12470 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, array in object:register_types.SCRATCH_UMSK.fields.0 12471 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} array in object:register_types.SCRATCH_UMSK.fields.1 12476 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.0 12477 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.1 12478 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.2 12479 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.3 12480 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, array in object:register_types.SPI_BARYC_CNTL.fields.4 12481 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, array in object:register_types.SPI_BARYC_CNTL.fields.5 12482 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} array in object:register_types.SPI_BARYC_CNTL.fields.6 12487 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, array in object:register_types.SPI_CONFIG_CNTL.fields.0 12488 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, array in object:register_types.SPI_CONFIG_CNTL.fields.1 12489 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.2 12490 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.3 12491 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, array in object:register_types.SPI_CONFIG_CNTL.fields.4 12492 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}, array in object:register_types.SPI_CONFIG_CNTL.fields.5 12493 {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"}, array in object:register_types.SPI_CONFIG_CNTL.fields.6 12494 {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"}, array in object:register_types.SPI_CONFIG_CNTL.fields.7 12495 {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"} array in object:register_types.SPI_CONFIG_CNTL.fields.8 12500 {"bits": [0, 3], "name": "VTX_DONE_DELAY"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.0 12501 {"bits": [4, 4], "name": "INTERP_ONE_PRIM_PER_ROW"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.1 12502 {"bits": [5, 5], "name": "BATON_RESET_DISABLE"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.2 12503 {"bits": [6, 6], "name": "PC_LIMIT_ENABLE"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.3 12504 {"bits": [7, 7], "name": "PC_LIMIT_STRICT"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.4 12505 {"bits": [8, 8], "name": "CRC_SIMD_ID_WADDR_DISABLE"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.5 12506 {"bits": [9, 9], "name": "LBPW_CU_CHK_MODE"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.6 12507 {"bits": [10, 13], "name": "LBPW_CU_CHK_CNT"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.7 12508 {"bits": [14, 14], "name": "CSC_PWR_SAVE_DISABLE"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.8 12509 {"bits": [15, 15], "name": "CSG_PWR_SAVE_DISABLE"}, array in object:register_types.SPI_CONFIG_CNTL_1.fields.9 12510 {"bits": [16, 31], "name": "PC_LIMIT_SIZE"} array in object:register_types.SPI_CONFIG_CNTL_1.fields.10 12515 {"bits": [0, 3], "name": "CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD"}, array in object:register_types.SPI_CONFIG_CNTL_2.fields.0 12516 {"bits": [4, 7], "name": "CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD"} array in object:register_types.SPI_CONFIG_CNTL_2.fields.1 12521 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.0 12522 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.1 12523 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.2 12524 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.3 12525 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.4 12526 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.5 12527 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} array in object:register_types.SPI_INTERP_CONTROL_0.fields.6 12532 {"bits": [0, 7], "name": "PERF_SEL"} array in object:register_types.SPI_PERFCOUNTER4_SELECT.fields.0 12537 {"bits": [0, 3], "name": "BIN0_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.0 12538 {"bits": [4, 7], "name": "BIN0_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.1 12539 {"bits": [8, 11], "name": "BIN1_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.2 12540 {"bits": [12, 15], "name": "BIN1_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.3 12541 {"bits": [16, 19], "name": "BIN2_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.4 12542 {"bits": [20, 23], "name": "BIN2_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.5 12543 {"bits": [24, 27], "name": "BIN3_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.6 12544 {"bits": [28, 31], "name": "BIN3_MAX"} array in object:register_types.SPI_PERFCOUNTER_BINS.fields.7 12549 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.0 12550 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.1 12551 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.2 12552 {"bits": [13, 16], "name": "CYL_WRAP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.3 12553 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.4 12554 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.5 12555 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.6 12556 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.7 12557 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.8 12558 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.9 12559 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.10 12560 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.11 12565 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.0 12566 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.1 12567 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.2 12568 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.3 12569 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.4 12570 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.5 12571 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.6 12572 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.7 12573 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.8 12578 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.0 12579 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.1 12580 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.2 12581 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.3 12582 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.4 12583 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.5 12584 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.6 12585 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.7 12586 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.8 12587 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.9 12588 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.10 12589 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.11 12590 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.12 12591 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.13 12592 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.14 12593 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} array in object:register_types.SPI_PS_INPUT_ENA.fields.15 12598 {"bits": [0, 5], "name": "NUM_INTERP"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.0 12599 {"bits": [6, 6], "name": "PARAM_GEN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.1 12600 {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.2 12601 {"bits": [8, 8], "name": "LATE_PC_DEALLOC"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.3 12602 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} array in object:register_types.SPI_PS_IN_CONTROL.fields.4 12607 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.0 12608 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.1 12609 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.2 12610 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.3 12611 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.4 12612 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.5 12613 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.6 12614 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_COL_FORMAT.fields.7 12619 {"bits": [0, 5], "name": "LIMIT"} array in object:register_types.SPI_SHADER_LATE_ALLOC_VS.fields.0 12624 {"bits": [0, 7], "name": "MEM_BASE"} array in object:register_types.SPI_SHADER_PGM_HI_PS.fields.0 12629 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.0 12630 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.1 12631 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.2 12632 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3 12633 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.4 12634 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.5 12635 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.6 12636 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.7 12637 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.8 12638 {"bits": [28, 28], "name": "CDBG_USER"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.9 12639 {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.10 12640 {"bits": [31, 31], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.11 12645 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.0 12646 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.1 12647 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.2 12648 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3 12649 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.4 12650 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.5 12651 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.6 12652 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.7 12653 {"bits": [27, 27], "name": "CDBG_USER"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.8 12654 {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.9 12655 {"bits": [30, 30], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.10 12660 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.0 12661 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.1 12662 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.2 12663 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3 12664 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.4 12665 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.5 12666 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.6 12667 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.7 12668 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.8 12669 {"bits": [28, 28], "name": "CDBG_USER"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.9 12670 {"bits": [29, 29], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.10 12675 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.0 12676 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.1 12677 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.2 12678 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3 12679 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.4 12680 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.5 12681 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.6 12682 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.7 12683 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.8 12684 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.9 12685 {"bits": [30, 30], "name": "CDBG_USER"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.10 12686 {"bits": [31, 31], "name": "FP16_OVFL"} array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.11 12691 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.0 12692 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.1 12693 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.2 12694 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3 12695 {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.4 12696 {"bits": [18, 18], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.5 12697 {"bits": [19, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.6 12698 {"bits": [27, 27], "name": "SKIP_USGPR0"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.7 12699 {"bits": [28, 28], "name": "USER_SGPR_MSB"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.8 12704 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.0 12705 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.1 12706 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.2 12707 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.3 12708 {"bits": [16, 17], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.4 12709 {"bits": [18, 18], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.5 12710 {"bits": [19, 26], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.6 12711 {"bits": [27, 27], "name": "SKIP_USGPR0"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.7 12712 {"bits": [28, 28], "name": "USER_SGPR_MSB"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.8 12717 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.0 12718 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.1 12719 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.2 12720 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.3 12721 {"bits": [16, 24], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.4 12722 {"bits": [27, 27], "name": "SKIP_USGPR0"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5 12723 {"bits": [28, 28], "name": "USER_SGPR_MSB"} array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.6 12728 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.0 12729 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.1 12730 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.2 12731 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.3 12732 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.4 12733 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5 12734 {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.6 12735 {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.7 12736 {"bits": [27, 27], "name": "SKIP_USGPR0"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.8 12737 {"bits": [28, 28], "name": "USER_SGPR_MSB"} array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.9 12742 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.0 12743 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.1 12744 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.2 12745 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.3 12746 {"bits": [8, 8], "name": "SO_BASE0_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.4 12747 {"bits": [9, 9], "name": "SO_BASE1_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.5 12748 {"bits": [10, 10], "name": "SO_BASE2_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.6 12749 {"bits": [11, 11], "name": "SO_BASE3_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.7 12750 {"bits": [12, 12], "name": "SO_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.8 12751 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9 12752 {"bits": [22, 22], "name": "PC_BASE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.10 12753 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.11 12754 {"bits": [27, 27], "name": "SKIP_USGPR0"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.12 12755 {"bits": [28, 28], "name": "USER_SGPR_MSB"} array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.13 12760 {"bits": [0, 5], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.0 12761 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.1 12762 {"bits": [10, 13], "name": "SIMD_DISABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.2 12763 {"bits": [16, 31], "name": "CU_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.3 12768 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.0 12769 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.1 12770 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.2 12771 {"bits": [26, 29], "name": "SIMD_DISABLE"} array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.3 12776 {"bits": [0, 6], "name": "GROUP_FIFO_DEPTH"}, array in object:register_types.SPI_SHADER_PGM_RSRC4_GS.fields.0 12777 {"bits": [7, 13], "name": "SPI_SHADER_LATE_ALLOC_GS"} array in object:register_types.SPI_SHADER_PGM_RSRC4_GS.fields.1 12782 {"bits": [0, 6], "name": "GROUP_FIFO_DEPTH"} array in object:register_types.SPI_SHADER_PGM_RSRC4_HS.fields.0 12787 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.0 12788 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.1 12789 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.2 12790 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_POS_FORMAT.fields.3 12795 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_Z_FORMAT.fields.0 12800 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.0 12801 {"bits": [6, 6], "name": "VS_HALF_PACK"} array in object:register_types.SPI_VS_OUT_CONFIG.fields.1 12806 {"bits": [0, 1], "name": "PS_WAVE_GRAN"}, array in object:register_types.SPI_WAVE_LIMIT_CNTL.fields.0 12807 {"bits": [2, 3], "name": "VS_WAVE_GRAN"}, array in object:register_types.SPI_WAVE_LIMIT_CNTL.fields.1 12808 {"bits": [4, 5], "name": "GS_WAVE_GRAN"}, array in object:register_types.SPI_WAVE_LIMIT_CNTL.fields.2 12809 {"bits": [6, 7], "name": "HS_WAVE_GRAN"} array in object:register_types.SPI_WAVE_LIMIT_CNTL.fields.3 12814 {"bits": [0, 0], "name": "TARGET_INST"}, array in object:register_types.SQC_CACHES.fields.0 12815 {"bits": [1, 1], "name": "TARGET_DATA"}, array in object:register_types.SQC_CACHES.fields.1 12816 {"bits": [2, 2], "name": "INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.2 12817 {"bits": [3, 3], "name": "WRITEBACK"}, array in object:register_types.SQC_CACHES.fields.3 12818 {"bits": [4, 4], "name": "VOL"}, array in object:register_types.SQC_CACHES.fields.4 12819 {"bits": [16, 16], "name": "COMPLETE"} array in object:register_types.SQC_CACHES.fields.5 12824 {"bits": [0, 0], "name": "DWB"}, array in object:register_types.SQC_WRITEBACK.fields.0 12825 {"bits": [1, 1], "name": "DIRTY"} array in object:register_types.SQC_WRITEBACK.fields.1 12830 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.0 12831 {"bits": [16, 29], "name": "STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.1 12832 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.2 12833 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} array in object:register_types.SQ_BUF_RSRC_WORD1.fields.3 12838 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.0 12839 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.1 12840 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.2 12841 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.3 12842 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.4 12843 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.5 12844 {"bits": [19, 19], "name": "USER_VM_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.6 12845 {"bits": [20, 20], "name": "USER_VM_MODE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.7 12846 {"bits": [21, 22], "name": "INDEX_STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.8 12847 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.9 12848 {"bits": [27, 27], "name": "NV"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.10 12849 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} array in object:register_types.SQ_BUF_RSRC_WORD3.fields.11 12854 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.0 12855 {"bits": [8, 19], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.1 12856 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.2 12857 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT_STENCIL", "name": "DATA_FORMAT_STENCIL"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.3 12858 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.4 12859 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT_FMASK", "name": "NUM_FORMAT_FMASK"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.5 12860 {"bits": [30, 30], "name": "NV"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.6 12861 {"bits": [31, 31], "name": "META_DIRECT"} array in object:register_types.SQ_IMG_RSRC_WORD1.fields.7 12866 {"bits": [0, 13], "name": "WIDTH"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.0 12867 {"bits": [14, 27], "name": "HEIGHT"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.1 12868 {"bits": [28, 30], "name": "PERF_MOD"} array in object:register_types.SQ_IMG_RSRC_WORD2.fields.2 12873 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.0 12874 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.1 12875 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.2 12876 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.3 12877 {"bits": [12, 15], "name": "BASE_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.4 12878 {"bits": [16, 19], "name": "LAST_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.5 12879 {"bits": [20, 24], "name": "SW_MODE"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.6 12880 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} array in object:register_types.SQ_IMG_RSRC_WORD3.fields.7 12885 {"bits": [0, 12], "name": "DEPTH"}, array in object:register_types.SQ_IMG_RSRC_WORD4.fields.0 12886 {"bits": [13, 28], "name": "PITCH"}, array in object:register_types.SQ_IMG_RSRC_WORD4.fields.1 12887 {"bits": [29, 31], "enum_ref": "SQ_IMG_RSRC_WORD4__BC_SWIZZLE", "name": "BC_SWIZZLE"} array in object:register_types.SQ_IMG_RSRC_WORD4.fields.2 12892 {"bits": [0, 12], "name": "BASE_ARRAY"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.0 12893 {"bits": [13, 16], "name": "ARRAY_PITCH"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.1 12894 {"bits": [17, 24], "name": "META_DATA_ADDRESS"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.2 12895 {"bits": [25, 25], "name": "META_LINEAR"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.3 12896 {"bits": [26, 26], "name": "META_PIPE_ALIGNED"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.4 12897 {"bits": [27, 27], "name": "META_RB_ALIGNED"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.5 12898 {"bits": [28, 31], "name": "MAX_MIP"} array in object:register_types.SQ_IMG_RSRC_WORD5.fields.6 12903 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.0 12904 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.1 12905 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.2 12906 {"bits": [21, 21], "name": "COMPRESSION_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.3 12907 {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.4 12908 {"bits": [23, 23], "name": "COLOR_TRANSFORM"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.5 12909 {"bits": [24, 27], "name": "LOST_ALPHA_BITS"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.6 12910 {"bits": [28, 31], "name": "LOST_COLOR_BITS"} array in object:register_types.SQ_IMG_RSRC_WORD6.fields.7 12915 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.0 12916 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.1 12917 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.2 12918 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.3 12919 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.4 12920 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.5 12921 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.6 12922 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.7 12923 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.8 12924 {"bits": [21, 26], "name": "ANISO_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.9 12925 {"bits": [27, 27], "name": "TRUNC_COORD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.10 12926 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.11 12927 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.12 12928 {"bits": [31, 31], "name": "COMPAT_MODE"} array in object:register_types.SQ_IMG_SAMP_WORD0.fields.13 12933 {"bits": [0, 11], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.0 12934 {"bits": [12, 23], "name": "MAX_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.1 12935 {"bits": [24, 27], "name": "PERF_MIP"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.2 12936 {"bits": [28, 31], "name": "PERF_Z"} array in object:register_types.SQ_IMG_SAMP_WORD1.fields.3 12941 {"bits": [0, 13], "name": "LOD_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.0 12942 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.1 12943 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.2 12944 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.3 12945 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.4 12946 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.5 12947 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.6 12948 {"bits": [29, 29], "name": "BLEND_ZERO_PRT"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.7 12949 {"bits": [30, 30], "name": "FILTER_PREC_FIX"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.8 12950 {"bits": [31, 31], "name": "ANISO_OVERRIDE"} array in object:register_types.SQ_IMG_SAMP_WORD2.fields.9 12955 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.0 12956 {"bits": [12, 12], "name": "SKIP_DEGAMMA"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.1 12957 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} array in object:register_types.SQ_IMG_SAMP_WORD3.fields.2 12962 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.0 12963 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.1 12964 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.2 12965 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.3 12966 {"bits": [24, 27], "name": "SIMD_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.4 12967 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.5 12972 {"bits": [0, 0], "name": "PS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.0 12973 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1 12974 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2 12975 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3 12976 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4 12977 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5 12978 {"bits": [6, 6], "name": "CS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.6 12979 {"bits": [8, 12], "name": "CNTR_RATE"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.7 12980 {"bits": [13, 13], "name": "DISABLE_FLUSH"} array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.8 12985 {"bits": [0, 0], "name": "FORCE_EN"} array in object:register_types.SQ_PERFCOUNTER_CTRL2.fields.0 12990 {"bits": [0, 3], "name": "ADDR_HI"} array in object:register_types.SQ_THREAD_TRACE_BASE2.fields.0 12995 {"bits": [31, 31], "name": "RESET_BUFFER"} array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.0 13000 {"bits": [0, 2], "name": "HIWATER"} array in object:register_types.SQ_THREAD_TRACE_HIWATER.fields.0 13005 {"bits": [0, 4], "name": "CU_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.0 13006 {"bits": [5, 5], "name": "SH_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.1 13007 {"bits": [7, 7], "name": "REG_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.2 13008 {"bits": [8, 11], "name": "SIMD_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.3 13009 {"bits": [12, 13], "name": "VM_ID_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.4 13010 {"bits": [14, 14], "name": "SPI_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.5 13011 {"bits": [15, 15], "name": "SQ_STALL_EN"} array in object:register_types.SQ_THREAD_TRACE_MASK.fields.6 13016 {"bits": [0, 2], "name": "MASK_PS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.0 13017 {"bits": [3, 5], "name": "MASK_VS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.1 13018 {"bits": [6, 8], "name": "MASK_GS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.2 13019 {"bits": [9, 11], "name": "MASK_ES"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.3 13020 {"bits": [12, 14], "name": "MASK_HS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.4 13021 {"bits": [15, 17], "name": "MASK_LS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.5 13022 {"bits": [18, 20], "name": "MASK_CS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.6 13023 {"bits": [21, 22], "name": "MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.7 13024 {"bits": [23, 24], "name": "CAPTURE_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.8 13025 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.9 13026 {"bits": [26, 26], "name": "TC_PERF_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.10 13027 {"bits": [27, 28], "name": "ISSUE_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.11 13028 {"bits": [29, 29], "name": "TEST_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.12 13029 {"bits": [30, 30], "name": "INTERRUPT_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.13 13030 {"bits": [31, 31], "name": "WRAP"} array in object:register_types.SQ_THREAD_TRACE_MODE.fields.14 13035 {"bits": [0, 15], "name": "SH0_MASK"}, array in object:register_types.SQ_THREAD_TRACE_PERF_MASK.fields.0 13036 {"bits": [16, 31], "name": "SH1_MASK"} array in object:register_types.SQ_THREAD_TRACE_PERF_MASK.fields.1 13041 {"bits": [0, 21], "name": "SIZE"} array in object:register_types.SQ_THREAD_TRACE_SIZE.fields.0 13046 {"bits": [0, 9], "name": "FINISH_PENDING"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.0 13047 {"bits": [16, 25], "name": "FINISH_DONE"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.1 13048 {"bits": [28, 28], "name": "UTC_ERROR"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.2 13049 {"bits": [29, 29], "name": "NEW_BUF"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.3 13050 {"bits": [30, 30], "name": "BUSY"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.4 13051 {"bits": [31, 31], "name": "FULL"} array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.5 13056 {"bits": [0, 15], "name": "TOKEN_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0 13057 {"bits": [16, 23], "name": "REG_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.1 13058 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.2 13063 {"bits": [0, 29], "name": "WPTR"}, array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.0 13064 {"bits": [30, 31], "name": "READ_OFFSET"} array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.1 13069 {"bits": [0, 5], "name": "VGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.0 13070 {"bits": [8, 13], "name": "VGPR_SIZE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.1 13071 {"bits": [16, 21], "name": "SGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.2 13072 {"bits": [24, 27], "name": "SGPR_SIZE"} array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.3 13077 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.0 13078 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.1 13079 {"bits": [6, 7], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.2 13080 {"bits": [8, 11], "name": "CU_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.3 13081 {"bits": [12, 12], "name": "SH_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.4 13082 {"bits": [13, 14], "name": "SE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.5 13083 {"bits": [16, 19], "name": "TG_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.6 13084 {"bits": [20, 23], "name": "VM_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.7 13085 {"bits": [24, 26], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.8 13086 {"bits": [27, 29], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.9 13087 {"bits": [30, 31], "name": "ME_ID"} array in object:register_types.SQ_WAVE_HW_ID.fields.10 13092 {"bits": [0, 2], "name": "IBUF_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.0 13093 {"bits": [3, 3], "name": "PC_INVALID"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.1 13094 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.2 13095 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.3 13096 {"bits": [8, 9], "name": "IBUF_RPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.4 13097 {"bits": [10, 11], "name": "IBUF_WPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.5 13098 {"bits": [16, 19], "name": "INST_STR_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.6 13099 {"bits": [24, 25], "name": "ECC_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.7 13100 {"bits": [26, 26], "name": "IS_HYB"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.8 13101 {"bits": [27, 28], "name": "HYB_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.9 13102 {"bits": [29, 29], "name": "KILL"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.10 13103 {"bits": [30, 30], "name": "NEED_KILL_IFETCH"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.11 13104 {"bits": [31, 31], "name": "NO_PREFETCH_CNT_HI"} array in object:register_types.SQ_WAVE_IB_DBG0.fields.12 13109 {"bits": [0, 0], "name": "IXNACK"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.0 13110 {"bits": [1, 1], "name": "XNACK"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.1 13111 {"bits": [2, 2], "name": "TA_NEED_RESET"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.2 13112 {"bits": [4, 8], "name": "XCNT"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.3 13113 {"bits": [11, 15], "name": "QCNT"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.4 13114 {"bits": [18, 22], "name": "RCNT"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.5 13115 {"bits": [25, 31], "name": "MISC_CNT"} array in object:register_types.SQ_WAVE_IB_DBG1.fields.6 13120 {"bits": [0, 3], "name": "VM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.0 13121 {"bits": [4, 6], "name": "EXP_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.1 13122 {"bits": [8, 11], "name": "LGKM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.2 13123 {"bits": [12, 14], "name": "VALU_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.3 13124 {"bits": [15, 15], "name": "FIRST_REPLAY"}, array in object:register_types.SQ_WAVE_IB_STS.fields.4 13125 {"bits": [16, 20], "name": "RCNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.5 13126 {"bits": [22, 23], "name": "VM_CNT_HI"} array in object:register_types.SQ_WAVE_IB_STS.fields.6 13131 {"bits": [0, 7], "name": "LDS_BASE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.0 13132 {"bits": [12, 20], "name": "LDS_SIZE"} array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.1 13137 {"bits": [0, 3], "name": "FP_ROUND"}, array in object:register_types.SQ_WAVE_MODE.fields.0 13138 {"bits": [4, 7], "name": "FP_DENORM"}, array in object:register_types.SQ_WAVE_MODE.fields.1 13139 {"bits": [8, 8], "name": "DX10_CLAMP"}, array in object:register_types.SQ_WAVE_MODE.fields.2 13140 {"bits": [9, 9], "name": "IEEE"}, array in object:register_types.SQ_WAVE_MODE.fields.3 13141 {"bits": [10, 10], "name": "LOD_CLAMPED"}, array in object:register_types.SQ_WAVE_MODE.fields.4 13142 {"bits": [11, 11], "name": "DEBUG_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.5 13143 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.6 13144 {"bits": [23, 23], "name": "FP16_OVFL"}, array in object:register_types.SQ_WAVE_MODE.fields.7 13145 {"bits": [24, 24], "name": "POPS_PACKER0"}, array in object:register_types.SQ_WAVE_MODE.fields.8 13146 {"bits": [25, 25], "name": "POPS_PACKER1"}, array in object:register_types.SQ_WAVE_MODE.fields.9 13147 {"bits": [26, 26], "name": "DISABLE_PERF"}, array in object:register_types.SQ_WAVE_MODE.fields.10 13148 {"bits": [27, 27], "name": "GPR_IDX_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.11 13149 {"bits": [28, 28], "name": "VSKIP"}, array in object:register_types.SQ_WAVE_MODE.fields.12 13150 {"bits": [29, 31], "name": "CSP"} array in object:register_types.SQ_WAVE_MODE.fields.13 13155 {"bits": [0, 15], "name": "PC_HI"} array in object:register_types.SQ_WAVE_PC_HI.fields.0 13160 {"bits": [0, 0], "name": "SCC"}, array in object:register_types.SQ_WAVE_STATUS.fields.0 13161 {"bits": [1, 2], "name": "SPI_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.1 13162 {"bits": [3, 4], "name": "USER_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.2 13163 {"bits": [5, 5], "name": "PRIV"}, array in object:register_types.SQ_WAVE_STATUS.fields.3 13164 {"bits": [6, 6], "name": "TRAP_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.4 13165 {"bits": [7, 7], "name": "TTRACE_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.5 13166 {"bits": [8, 8], "name": "EXPORT_RDY"}, array in object:register_types.SQ_WAVE_STATUS.fields.6 13167 {"bits": [9, 9], "name": "EXECZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.7 13168 {"bits": [10, 10], "name": "VCCZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.8 13169 {"bits": [11, 11], "name": "IN_TG"}, array in object:register_types.SQ_WAVE_STATUS.fields.9 13170 {"bits": [12, 12], "name": "IN_BARRIER"}, array in object:register_types.SQ_WAVE_STATUS.fields.10 13171 {"bits": [13, 13], "name": "HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.11 13172 {"bits": [14, 14], "name": "TRAP"}, array in object:register_types.SQ_WAVE_STATUS.fields.12 13173 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.13 13174 {"bits": [16, 16], "name": "VALID"}, array in object:register_types.SQ_WAVE_STATUS.fields.14 13175 {"bits": [17, 17], "name": "ECC_ERR"}, array in object:register_types.SQ_WAVE_STATUS.fields.15 13176 {"bits": [18, 18], "name": "SKIP_EXPORT"}, array in object:register_types.SQ_WAVE_STATUS.fields.16 13177 {"bits": [19, 19], "name": "PERF_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.17 13178 {"bits": [20, 20], "name": "COND_DBG_USER"}, array in object:register_types.SQ_WAVE_STATUS.fields.18 13179 {"bits": [21, 21], "name": "COND_DBG_SYS"}, array in object:register_types.SQ_WAVE_STATUS.fields.19 13180 {"bits": [22, 22], "name": "ALLOW_REPLAY"}, array in object:register_types.SQ_WAVE_STATUS.fields.20 13181 {"bits": [23, 23], "name": "FATAL_HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.21 13182 {"bits": [27, 27], "name": "MUST_EXPORT"} array in object:register_types.SQ_WAVE_STATUS.fields.22 13187 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.0 13188 {"bits": [10, 10], "name": "SAVECTX"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.1 13189 {"bits": [11, 11], "name": "ILLEGAL_INST"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.2 13190 {"bits": [12, 14], "name": "EXCP_HI"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.3 13191 {"bits": [16, 21], "name": "EXCP_CYCLE"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.4 13192 {"bits": [28, 28], "name": "XNACK_ERROR"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.5 13193 {"bits": [29, 31], "name": "DP_RATE"} array in object:register_types.SQ_WAVE_TRAPSTS.fields.6 13198 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.0 13199 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.1 13200 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.2 13201 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.3 13202 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.4 13203 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.5 13204 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.6 13205 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.7 13206 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.8 13207 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.9 13208 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.10 13209 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.11 13210 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.12 13211 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.13 13212 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.14 13213 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.15 13214 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"} array in object:register_types.SX_BLEND_OPT_CONTROL.fields.16 13219 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.0 13220 {"bits": [4, 7], "name": "MRT1_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.1 13221 {"bits": [8, 11], "name": "MRT2_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.2 13222 {"bits": [12, 15], "name": "MRT3_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.3 13223 {"bits": [16, 19], "name": "MRT4_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.4 13224 {"bits": [20, 23], "name": "MRT5_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.5 13225 {"bits": [24, 27], "name": "MRT6_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.6 13226 {"bits": [28, 31], "name": "MRT7_EPSILON"} array in object:register_types.SX_BLEND_OPT_EPSILON.fields.7 13231 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.0 13232 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.1 13233 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.2 13234 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.3 13235 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.4 13236 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} array in object:register_types.SX_MRT0_BLEND_OPT.fields.5 13241 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.0 13242 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.1 13243 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.2 13244 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.3 13245 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.4 13246 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.5 13247 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.6 13248 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} array in object:register_types.SX_PS_DOWNCONVERT.fields.7 13253 {"bits": [0, 7], "name": "ADDRESS"} array in object:register_types.TA_BC_BASE_ADDR_HI.fields.0 13258 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.0 13259 {"bits": [10, 17], "name": "PERF_SEL1"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.1 13260 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.2 13261 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.3 13262 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TA_PERFCOUNTER0_SELECT.fields.4 13267 {"bits": [0, 7], "name": "PERF_SEL2"}, array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.0 13268 {"bits": [10, 17], "name": "PERF_SEL3"}, array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.1 13269 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.2 13270 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.TA_PERFCOUNTER0_SELECT1.fields.3 13275 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.TA_PERFCOUNTER1_SELECT.fields.0 13276 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TA_PERFCOUNTER1_SELECT.fields.1 13277 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TA_PERFCOUNTER1_SELECT.fields.2 13282 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.0 13283 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.1 13284 {"bits": [24, 27], "name": "PERF_MODE2"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.2 13285 {"bits": [28, 31], "name": "PERF_MODE3"} array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.3 13290 {"bits": [0, 15], "name": "BASE_ADDR"} array in object:register_types.VGT_DMA_BASE_HI.fields.0 13295 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.0 13296 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.1 13297 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.2 13298 {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.3 13299 {"bits": [8, 8], "name": "PRIMGEN_EN"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.4 13300 {"bits": [9, 9], "name": "NOT_EOP"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.5 13301 {"bits": [10, 10], "name": "REQ_PATH"} array in object:register_types.VGT_DMA_INDEX_TYPE.fields.6 13306 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.0 13307 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.1 13308 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.2 13309 {"bits": [5, 5], "name": "NOT_EOP"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.3 13310 {"bits": [6, 6], "name": "USE_OPAQUE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.4 13311 {"bits": [7, 7], "name": "UNROLLED_INST"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.5 13312 {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.6 13313 {"bits": [29, 31], "name": "REG_RT_INDEX"} array in object:register_types.VGT_DRAW_INITIATOR.fields.7 13318 {"bits": [0, 0], "name": "OBJPRIM_ID_EN"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.0 13319 {"bits": [1, 1], "name": "EN_REG_RT_INDEX"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.1 13320 {"bits": [2, 2], "name": "EN_PIPELINE_PRIMID"}, array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.2 13321 {"bits": [3, 3], "name": "OBJECT_ID_INST_EN"} array in object:register_types.VGT_DRAW_PAYLOAD_CNTL.fields.3 13326 {"bits": [0, 14], "name": "ITEMSIZE"} array in object:register_types.VGT_ESGS_RING_ITEMSIZE.fields.0 13331 {"bits": [0, 10], "name": "ES_PER_GS"} array in object:register_types.VGT_ES_PER_GS.fields.0 13336 {"bits": [0, 27], "name": "ADDRESS_LOW"} array in object:register_types.VGT_EVENT_ADDRESS_REG.fields.0 13341 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.0 13342 {"bits": [10, 26], "name": "ADDRESS_HI"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.1 13343 {"bits": [27, 27], "name": "EXTENDED_EVENT"} array in object:register_types.VGT_EVENT_INITIATOR.fields.2 13348 {"bits": [0, 3], "name": "DECR"} array in object:register_types.VGT_GROUP_DECR.fields.0 13353 {"bits": [0, 3], "name": "FIRST_DECR"} array in object:register_types.VGT_GROUP_FIRST_DECR.fields.0 13358 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0 13359 {"bits": [14, 14], "name": "RETAIN_ORDER"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.1 13360 {"bits": [15, 15], "name": "RETAIN_QUADS"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.2 13361 {"bits": [16, 18], "name": "PRIM_ORDER"} array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.3 13366 {"bits": [0, 0], "name": "COMP_X_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.0 13367 {"bits": [1, 1], "name": "COMP_Y_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.1 13368 {"bits": [2, 2], "name": "COMP_Z_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.2 13369 {"bits": [3, 3], "name": "COMP_W_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.3 13370 {"bits": [8, 15], "name": "STRIDE"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.4 13371 {"bits": [16, 23], "name": "SHIFT"} array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.5 13376 {"bits": [0, 3], "name": "X_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.0 13377 {"bits": [4, 7], "name": "X_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.1 13378 {"bits": [8, 11], "name": "Y_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.2 13379 {"bits": [12, 15], "name": "Y_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.3 13380 {"bits": [16, 19], "name": "Z_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.4 13381 {"bits": [20, 23], "name": "Z_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.5 13382 {"bits": [24, 27], "name": "W_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.6 13383 {"bits": [28, 31], "name": "W_OFFSET"} array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.7 13388 {"bits": [0, 14], "name": "OFFSET"} array in object:register_types.VGT_GSVS_RING_OFFSET_1.fields.0 13393 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.0 13394 {"bits": [2, 8], "name": "CNT"} array in object:register_types.VGT_GS_INSTANCE_CNT.fields.1 13399 {"bits": [0, 15], "name": "MAX_PRIMS_PER_SUBGROUP"} array in object:register_types.VGT_GS_MAX_PRIMS_PER_SUBGROUP.fields.0 13404 {"bits": [0, 10], "name": "MAX_VERT_OUT"} array in object:register_types.VGT_GS_MAX_VERT_OUT.fields.0 13409 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, array in object:register_types.VGT_GS_MODE.fields.0 13410 {"bits": [3, 3], "name": "RESERVED_0"}, array in object:register_types.VGT_GS_MODE.fields.1 13411 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, array in object:register_types.VGT_GS_MODE.fields.2 13412 {"bits": [6, 10], "name": "RESERVED_1"}, array in object:register_types.VGT_GS_MODE.fields.3 13413 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, array in object:register_types.VGT_GS_MODE.fields.4 13414 {"bits": [12, 12], "name": "RESERVED_2"}, array in object:register_types.VGT_GS_MODE.fields.5 13415 {"bits": [13, 13], "name": "ES_PASSTHRU"}, array in object:register_types.VGT_GS_MODE.fields.6 13416 {"bits": [14, 14], "name": "RESERVED_3"}, array in object:register_types.VGT_GS_MODE.fields.7 13417 {"bits": [15, 15], "name": "RESERVED_4"}, array in object:register_types.VGT_GS_MODE.fields.8 13418 {"bits": [16, 16], "name": "RESERVED_5"}, array in object:register_types.VGT_GS_MODE.fields.9 13419 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, array in object:register_types.VGT_GS_MODE.fields.10 13420 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, array in object:register_types.VGT_GS_MODE.fields.11 13421 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.12 13422 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.13 13423 {"bits": [21, 22], "name": "ONCHIP"} array in object:register_types.VGT_GS_MODE.fields.14 13428 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.0 13429 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.1 13430 {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"} array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.2 13435 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0 13436 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1 13437 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2 13438 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3 13439 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.4 13444 {"bits": [0, 10], "name": "GS_PER_ES"} array in object:register_types.VGT_GS_PER_ES.fields.0 13449 {"bits": [0, 3], "name": "GS_PER_VS"} array in object:register_types.VGT_GS_PER_VS.fields.0 13454 {"bits": [0, 1], "name": "TESS_MODE"} array in object:register_types.VGT_HOS_CNTL.fields.0 13459 {"bits": [0, 7], "name": "REUSE_DEPTH"} array in object:register_types.VGT_HOS_REUSE_DEPTH.fields.0 13464 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"}, array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.0 13465 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1 13470 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_INDEX_TYPE.fields.0 13471 {"bits": [8, 8], "name": "PRIMGEN_EN"} array in object:register_types.VGT_INDEX_TYPE.fields.1 13476 {"bits": [0, 7], "name": "NUM_PATCHES"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.0 13477 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.1 13478 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} array in object:register_types.VGT_LS_HS_CONFIG.fields.2 13483 {"bits": [0, 0], "name": "RESET_EN"}, array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.0 13484 {"bits": [1, 1], "name": "MATCH_ALL_BITS"} array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.1 13489 {"bits": [0, 2], "name": "PATH_SELECT"} array in object:register_types.VGT_OUTPUT_PATH_CNTL.fields.0 13494 {"bits": [0, 6], "name": "DEALLOC_DIST"} array in object:register_types.VGT_OUT_DEALLOC_CNTL.fields.0 13499 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} array in object:register_types.VGT_PERFCOUNTER_SEID_MASK.fields.0 13504 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.0 13505 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.1 13506 {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"} array in object:register_types.VGT_PRIMITIVEID_EN.fields.2 13511 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} array in object:register_types.VGT_PRIMITIVE_TYPE.fields.0 13516 {"bits": [0, 0], "name": "REUSE_OFF"} array in object:register_types.VGT_REUSE_OFF.fields.0 13521 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.0 13522 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.1 13523 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.2 13524 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.3 13525 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.4 13526 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.5 13527 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.6 13528 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.7 13529 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.8 13530 {"bits": [13, 13], "name": "PRIMGEN_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.9 13531 {"bits": [14, 14], "name": "ORDERED_ID_MODE"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.10 13532 {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.11 13533 {"bits": [19, 20], "name": "GS_FAST_LAUNCH"} array in object:register_types.VGT_SHADER_STAGES_EN.fields.12 13538 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.0 13539 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.1 13540 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.2 13541 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.3 13546 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.0 13547 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.1 13548 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.2 13549 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.3 13550 {"bits": [4, 6], "name": "RAST_STREAM"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.4 13551 {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.5 13552 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.6 13553 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} array in object:register_types.VGT_STRMOUT_CONFIG.fields.7 13558 {"bits": [0, 8], "name": "VERTEX_STRIDE"} array in object:register_types.VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE.fields.0 13563 {"bits": [0, 9], "name": "STRIDE"} array in object:register_types.VGT_STRMOUT_VTX_STRIDE_0.fields.0 13568 {"bits": [0, 7], "name": "ACCUM_ISOLINE"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.0 13569 {"bits": [8, 15], "name": "ACCUM_TRI"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.1 13570 {"bits": [16, 23], "name": "ACCUM_QUAD"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.2 13571 {"bits": [24, 28], "name": "DONUT_SPLIT"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.3 13572 {"bits": [29, 31], "name": "TRAP_SPLIT"} array in object:register_types.VGT_TESS_DISTRIBUTION.fields.4 13577 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, array in object:register_types.VGT_TF_PARAM.fields.0 13578 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, array in object:register_types.VGT_TF_PARAM.fields.1 13579 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, array in object:register_types.VGT_TF_PARAM.fields.2 13580 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, array in object:register_types.VGT_TF_PARAM.fields.3 13581 {"bits": [9, 9], "name": "DEPRECATED"}, array in object:register_types.VGT_TF_PARAM.fields.4 13582 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, array in object:register_types.VGT_TF_PARAM.fields.5 13583 {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_TF_PARAM.fields.6 13584 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"} array in object:register_types.VGT_TF_PARAM.fields.7 13589 {"bits": [0, 15], "name": "SIZE"} array in object:register_types.VGT_TF_RING_SIZE.fields.0 13594 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} array in object:register_types.VGT_VERTEX_REUSE_BLOCK_CNTL.fields.0 13599 {"bits": [0, 0], "name": "VTX_CNT_EN"} array in object:register_types.VGT_VTX_CNT_EN.fields.0 13604 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.WD_PERFCOUNTER0_SELECT.fields.0 13605 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.WD_PERFCOUNTER0_SELECT.fields.1 [all...]
H A D	gfx81.json	9394 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.0 9395 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.1 9396 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.2 9397 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.3 9398 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, array in object:register_types.CB_BLEND0_CONTROL.fields.4 9399 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.5 9400 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, array in object:register_types.CB_BLEND0_CONTROL.fields.6 9401 {"bits": [30, 30], "name": "ENABLE"}, array in object:register_types.CB_BLEND0_CONTROL.fields.7 9402 {"bits": [31, 31], "name": "DISABLE_ROP3"} array in object:register_types.CB_BLEND0_CONTROL.fields.8 9407 {"bits" array in object:register_types.CB_COLOR0_ATTRIB.fields.0 9408 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.1 9409 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.2 9410 {"bits": [12, 14], "name": "NUM_SAMPLES"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.3 9411 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, array in object:register_types.CB_COLOR0_ATTRIB.fields.4 9412 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"} array in object:register_types.CB_COLOR0_ATTRIB.fields.5 9417 {"bits": [0, 13], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_CMASK_SLICE.fields.0 9422 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.0 9423 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.1 9424 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": " array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2 9425 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MI array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3 9426 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.4 9427 {"bits": [7, 8], "name": "COLOR_TRANSFORM"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.5 9428 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.6 9429 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"}, array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.7 9430 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"} array in object:register_types.CB_COLOR0_DCC_CONTROL.fields.8 9435 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, array in object:register_types.CB_COLOR0_INFO.fields.0 9436 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, array in object:register_types.CB_COLOR0_INFO.fields.1 9437 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, array in object:register_types.CB_COLOR0_INFO.fields.2 9438 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, array in object:register_types.CB_COLOR0_INFO.fields.3 9439 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, array in object:register_types.CB_COLOR0_INFO.fields.4 9440 {"bits": [13, 13], "name": "FAST_CLEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.5 9441 {"bits": [14, 14], "name": "COMPRESSION"}, array in object:register_types.CB_COLOR0_INFO.fields.6 9442 {"bits": [15, 15], "name": "BLEND_CLAMP"}, array in object:register_types.CB_COLOR0_INFO.fields.7 9443 {"bits": [16, 16], "name": "BLEND_BYPASS"}, array in object:register_types.CB_COLOR0_INFO.fields.8 9444 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, array in object:register_types.CB_COLOR0_INFO.fields.9 9445 {"bits": [18, 18], "name": "ROUND_MODE"}, array in object:register_types.CB_COLOR0_INFO.fields.10 9446 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, array in object:register_types.CB_COLOR0_INFO.fields.11 9447 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, array in object:register_types.CB_COLOR0_INFO.fields.12 9448 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, array in object:register_types.CB_COLOR0_INFO.fields.13 9449 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.14 9450 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"}, array in object:register_types.CB_COLOR0_INFO.fields.15 9451 {"bits": [28, 28], "name": "DCC_ENABLE"}, array in object:register_types.CB_COLOR0_INFO.fields.16 9452 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"} array in object:register_types.CB_COLOR0_INFO.fields.17 9457 {"bits": [0, 10], "name": "TILE_MAX"}, array in object:register_types.CB_COLOR0_PITCH.fields.0 9458 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} array in object:register_types.CB_COLOR0_PITCH.fields.1 9463 {"bits": [0, 21], "name": "TILE_MAX"} array in object:register_types.CB_COLOR0_SLICE.fields.0 9468 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.CB_COLOR0_VIEW.fields.0 9469 {"bits": [13, 23], "name": "SLICE_MAX"} array in object:register_types.CB_COLOR0_VIEW.fields.1 9474 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"}, array in object:register_types.CB_COLOR_CONTROL.fields.0 9475 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, array in object:register_types.CB_COLOR_CONTROL.fields.1 9476 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, array in object:register_types.CB_COLOR_CONTROL.fields.2 9477 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} array in object:register_types.CB_COLOR_CONTROL.fields.3 9482 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, array in object:register_types.CB_DCC_CONTROL.fields.0 9483 {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"}, array in object:register_types.CB_DCC_CONTROL.fields.1 9484 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"} array in object:register_types.CB_DCC_CONTROL.fields.2 9489 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.0 9490 {"bits": [10, 18], "name": "PERF_SEL1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.1 9491 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.2 9492 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.3 9493 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER0_SELECT.fields.4 9498 {"bits": [0, 8], "name": "PERF_SEL2"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.0 9499 {"bits": [10, 18], "name": "PERF_SEL3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.1 9500 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.2 9501 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.CB_PERFCOUNTER0_SELECT1.fields.3 9506 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.0 9507 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.CB_PERFCOUNTER1_SELECT.fields.1 9512 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.0 9513 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.1 9514 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.2 9515 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.3 9516 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.4 9517 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.5 9518 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.6 9519 {"bits": [13, 15], "name": "MRT_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.7 9520 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.8 9521 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.9 9522 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"}, array in object:register_types.CB_PERFCOUNTER_FILTER.fields.10 9523 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"} array in object:register_types.CB_PERFCOUNTER_FILTER.fields.11 9528 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.0 9529 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.1 9530 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.2 9531 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.3 9532 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.4 9533 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.5 9534 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, array in object:register_types.CB_SHADER_MASK.fields.6 9535 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} array in object:register_types.CB_SHADER_MASK.fields.7 9540 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.0 9541 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.1 9542 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.2 9543 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.3 9544 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.4 9545 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.5 9546 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, array in object:register_types.CB_TARGET_MASK.fields.6 9547 {"bits": [28, 31], "name": "TARGET7_ENABLE"} array in object:register_types.CB_TARGET_MASK.fields.7 9552 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.0 9553 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.1 9554 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.2 9555 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.3 9556 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.4 9557 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.5 9558 {"bits": [6, 6], "name": "ORDER_MODE"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.6 9559 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.7 9560 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.8 9561 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.9 9562 {"bits": [12, 12], "name": "DATA_ATC"}, array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.10 9563 {"bits": [14, 14], "name": "RESTORE"} array in object:register_types.COMPUTE_DISPATCH_INITIATOR.fields.11 9568 {"bits": [0, 1], "name": "SEND_SEID"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.0 9569 {"bits": [2, 2], "name": "RESERVED2"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.1 9570 {"bits": [3, 3], "name": "RESERVED3"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.2 9571 {"bits": [4, 4], "name": "RESERVED4"}, array in object:register_types.COMPUTE_MISC_RESERVED.fields.3 9572 {"bits": [5, 16], "name": "WAVE_ID_BASE"} array in object:register_types.COMPUTE_MISC_RESERVED.fields.4 9577 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, array in object:register_types.COMPUTE_NUM_THREAD_X.fields.0 9578 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} array in object:register_types.COMPUTE_NUM_THREAD_X.fields.1 9583 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"} array in object:register_types.COMPUTE_PERFCOUNT_ENABLE.fields.0 9588 {"bits": [0, 7], "name": "DATA"}, array in object:register_types.COMPUTE_PGM_HI.fields.0 9589 {"bits": [8, 8], "name": "INST_ATC"} array in object:register_types.COMPUTE_PGM_HI.fields.1 9594 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.0 9595 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.1 9596 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.2 9597 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.3 9598 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.4 9599 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.5 9600 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.6 9601 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.7 9602 {"bits": [24, 24], "name": "BULKY"}, array in object:register_types.COMPUTE_PGM_RSRC1.fields.8 9603 {"bits": [25, 25], "name": "CDBG_USER"} array in object:register_types.COMPUTE_PGM_RSRC1.fields.9 9608 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.0 9609 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.1 9610 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.2 9611 {"bits": [7, 7], "name": "TGID_X_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.3 9612 {"bits": [8, 8], "name": "TGID_Y_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.4 9613 {"bits": [9, 9], "name": "TGID_Z_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.5 9614 {"bits": [10, 10], "name": "TG_SIZE_EN"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.6 9615 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.7 9616 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.8 9617 {"bits": [15, 23], "name": "LDS_SIZE"}, array in object:register_types.COMPUTE_PGM_RSRC2.fields.9 9618 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.COMPUTE_PGM_RSRC2.fields.10 9623 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"} array in object:register_types.COMPUTE_PIPELINESTAT_ENABLE.fields.0 9628 {"bits": [0, 29], "name": "PAYLOAD"}, array in object:register_types.COMPUTE_RELAUNCH.fields.0 9629 {"bits": [30, 30], "name": "IS_EVENT"}, array in object:register_types.COMPUTE_RELAUNCH.fields.1 9630 {"bits": [31, 31], "name": "IS_STATE"} array in object:register_types.COMPUTE_RELAUNCH.fields.2 9635 {"bits": [0, 9], "name": "WAVES_PER_SH"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.0 9636 {"bits": [12, 15], "name": "TG_PER_CU"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.1 9637 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.2 9638 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.3 9639 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.4 9640 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} array in object:register_types.COMPUTE_RESOURCE_LIMITS.fields.5 9645 {"bits": [0, 15], "name": "SH0_CU_EN"}, array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.0 9646 {"bits": [16, 31], "name": "SH1_CU_EN"} array in object:register_types.COMPUTE_STATIC_THREAD_MGMT_SE0.fields.1 9651 {"bits": [0, 7], "name": "DATA"} array in object:register_types.COMPUTE_TBA_HI.fields.0 9656 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"} array in object:register_types.COMPUTE_THREAD_TRACE_ENABLE.fields.0 9661 {"bits": [0, 11], "name": "WAVES"}, array in object:register_types.COMPUTE_TMPRING_SIZE.fields.0 9662 {"bits": [12, 24], "name": "WAVESIZE"} array in object:register_types.COMPUTE_TMPRING_SIZE.fields.1 9667 {"bits": [0, 3], "name": "DATA"} array in object:register_types.COMPUTE_VMID.fields.0 9672 {"bits": [0, 15], "name": "ADDR"} array in object:register_types.COMPUTE_WAVE_RESTORE_ADDR_HI.fields.0 9677 {"bits": [0, 0], "name": "ATC"}, array in object:register_types.COMPUTE_WAVE_RESTORE_CONTROL.fields.0 9678 {"bits": [1, 2], "name": "MTYPE"} array in object:register_types.COMPUTE_WAVE_RESTORE_CONTROL.fields.1 9683 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT.fields.0 9684 {"bits": [10, 15], "name": "PERF_SEL1"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT.fields.1 9685 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.CPG_PERFCOUNTER0_SELECT.fields.2 9690 {"bits": [0, 5], "name": "PERF_SEL2"}, array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.0 9691 {"bits": [10, 15], "name": "PERF_SEL3"} array in object:register_types.CPG_PERFCOUNTER0_SELECT1.fields.1 9696 {"bits": [0, 5], "name": "PERF_SEL"} array in object:register_types.CPG_PERFCOUNTER1_SELECT.fields.0 9701 {"bits": [0, 15], "name": "MEM_ADDR_HI"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.0 9702 {"bits": [16, 16], "name": "CS_PS_SEL"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.1 9703 {"bits": [25, 25], "name": "CACHE_POLICY"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.2 9704 {"bits": [27, 28], "name": "MTYPE"}, array in object:register_types.CP_APPEND_ADDR_HI.fields.3 9705 {"bits": [29, 31], "name": "COMMAND"} array in object:register_types.CP_APPEND_ADDR_HI.fields.4 9710 {"bits": [2, 31], "name": "MEM_ADDR_LO"} array in object:register_types.CP_APPEND_ADDR_LO.fields.0 9715 {"bits": [0, 15], "name": "IB1_BASE_HI"} array in object:register_types.CP_CE_IB1_BASE_HI.fields.0 9720 {"bits": [2, 31], "name": "IB1_BASE_LO"} array in object:register_types.CP_CE_IB1_BASE_LO.fields.0 9725 {"bits": [0, 19], "name": "IB1_BUFSZ"} array in object:register_types.CP_CE_IB1_BUFSZ.fields.0 9730 {"bits": [0, 15], "name": "IB2_BASE_HI"} array in object:register_types.CP_CE_IB2_BASE_HI.fields.0 9735 {"bits": [2, 31], "name": "IB2_BASE_LO"} array in object:register_types.CP_CE_IB2_BASE_LO.fields.0 9740 {"bits": [0, 19], "name": "IB2_BUFSZ"} array in object:register_types.CP_CE_IB2_BUFSZ.fields.0 9745 {"bits": [0, 15], "name": "INIT_BASE_HI"} array in object:register_types.CP_CE_INIT_BASE_HI.fields.0 9750 {"bits": [5, 31], "name": "INIT_BASE_LO"} array in object:register_types.CP_CE_INIT_BASE_LO.fields.0 9755 {"bits": [0, 11], "name": "INIT_BUFSZ"} array in object:register_types.CP_CE_INIT_BUFSZ.fields.0 9760 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"} array in object:register_types.CP_COHER_BASE_HI.fields.0 9765 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.0 9766 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.1 9767 {"bits": [2, 2], "name": "TC_SD_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.2 9768 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.3 9769 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.4 9770 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.5 9771 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.6 9772 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.7 9773 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.8 9774 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.9 9775 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.10 9776 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.11 9777 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.12 9778 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.13 9779 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.14 9780 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.15 9781 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.16 9782 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.17 9783 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.18 9784 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.19 9785 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.20 9786 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.21 9787 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.22 9788 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.23 9789 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}, array in object:register_types.CP_COHER_CNTL.fields.24 9790 {"bits": [31, 31], "name": "SH_SD_ACTION_ENA"} array in object:register_types.CP_COHER_CNTL.fields.25 9795 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"} array in object:register_types.CP_COHER_SIZE_HI.fields.0 9800 {"bits": [0, 5], "name": "START_DELAY_COUNT"} array in object:register_types.CP_COHER_START_DELAY.fields.0 9805 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, array in object:register_types.CP_COHER_STATUS.fields.0 9806 {"bits": [24, 25], "name": "MEID"}, array in object:register_types.CP_COHER_STATUS.fields.1 9807 {"bits": [30, 30], "name": "PHASE1_STATUS"}, array in object:register_types.CP_COHER_STATUS.fields.2 9808 {"bits": [31, 31], "name": "STATUS"} array in object:register_types.CP_COHER_STATUS.fields.3 9813 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.0 9814 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.1 9815 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.2 9816 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.3 9817 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.4 9818 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.5 9819 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.6 9820 {"bits": [7, 7], "name": "MEC1_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.7 9821 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.8 9822 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.9 9823 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.10 9824 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.11 9825 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.12 9826 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.13 9827 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.14 9828 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.15 9829 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.16 9830 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.17 9831 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.18 9832 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.19 9833 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.20 9834 {"bits": [23, 23], "name": "MEC2_TC_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.21 9835 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.22 9836 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.23 9837 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.24 9838 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.25 9839 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"}, array in object:register_types.CP_CPC_BUSY_STAT.fields.26 9840 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"} array in object:register_types.CP_CPC_BUSY_STAT.fields.27 9845 {"bits": [0, 5], "name": "FREE_COUNT"} array in object:register_types.CP_CPC_GRBM_FREE_COUNT.fields.0 9850 {"bits": [0, 3], "name": "COUNT"} array in object:register_types.CP_CPC_HALT_HYST_COUNT.fields.0 9855 {"bits": [0, 8], "name": "SCRATCH_INDEX"} array in object:register_types.CP_CPC_SCRATCH_INDEX.fields.0 9860 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.0 9861 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.1 9862 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.2 9863 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.3 9864 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.4 9865 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.5 9866 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.6 9867 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.7 9868 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.8 9869 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.9 9870 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.10 9871 {"bits": [22, 22], "name": "ATCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.11 9872 {"bits": [23, 23], "name": "ATCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPC_STALLED_STAT1.fields.12 9873 {"bits": [24, 24], "name": "ATCL1_WAITING_ON_TRANS"} array in object:register_types.CP_CPC_STALLED_STAT1.fields.13 9878 {"bits": [0, 0], "name": "MEC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.0 9879 {"bits": [1, 1], "name": "MEC2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.1 9880 {"bits": [2, 2], "name": "DC0_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.2 9881 {"bits": [3, 3], "name": "DC1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.3 9882 {"bits": [4, 4], "name": "RCIU1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.4 9883 {"bits": [5, 5], "name": "RCIU2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.5 9884 {"bits": [6, 6], "name": "ROQ1_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.6 9885 {"bits": [7, 7], "name": "ROQ2_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.7 9886 {"bits": [10, 10], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.8 9887 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.9 9888 {"bits": [12, 12], "name": "QU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.10 9889 {"bits": [13, 13], "name": "ATCL2IU_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.11 9890 {"bits": [29, 29], "name": "CPG_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.12 9891 {"bits": [30, 30], "name": "CPF_CPC_BUSY"}, array in object:register_types.CP_CPC_STATUS.fields.13 9892 {"bits": [31, 31], "name": "CPC_BUSY"} array in object:register_types.CP_CPC_STATUS.fields.14 9897 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.0 9898 {"bits": [1, 1], "name": "CSF_RING_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.1 9899 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.2 9900 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.3 9901 {"bits": [4, 4], "name": "CSF_STATE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.4 9902 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.5 9903 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.6 9904 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.7 9905 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.8 9906 {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.9 9907 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.10 9908 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.11 9909 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.12 9910 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.13 9911 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.14 9912 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.15 9913 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.16 9914 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.17 9915 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.18 9916 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.19 9917 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.20 9918 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.21 9919 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.22 9920 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.23 9921 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.24 9922 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.25 9923 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.26 9924 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.27 9925 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.28 9926 {"bits": [30, 30], "name": "HQD_PQ_BUSY"}, array in object:register_types.CP_CPF_BUSY_STAT.fields.29 9927 {"bits": [31, 31], "name": "HQD_IB_BUSY"} array in object:register_types.CP_CPF_BUSY_STAT.fields.30 9932 {"bits": [0, 0], "name": "RING_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.0 9933 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.1 9934 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.2 9935 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.3 9936 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.4 9937 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.5 9938 {"bits": [7, 7], "name": "ATCL2IU_WAITING_ON_FREE"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.6 9939 {"bits": [8, 8], "name": "ATCL2IU_WAITING_ON_TAGS"}, array in object:register_types.CP_CPF_STALLED_STAT1.fields.7 9940 {"bits": [9, 9], "name": "ATCL1_WAITING_ON_TRANS"} array in object:register_types.CP_CPF_STALLED_STAT1.fields.8 9945 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.0 9946 {"bits": [1, 1], "name": "CSF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.1 9947 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.2 9948 {"bits": [5, 5], "name": "ROQ_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.3 9949 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.4 9950 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.5 9951 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.6 9952 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.7 9953 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.8 9954 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.9 9955 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.10 9956 {"bits": [13, 13], "name": "INTERRUPT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.11 9957 {"bits": [14, 14], "name": "TCIU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.12 9958 {"bits": [15, 15], "name": "HQD_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.13 9959 {"bits": [16, 16], "name": "PRT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.14 9960 {"bits": [17, 17], "name": "ATCL2IU_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.15 9961 {"bits": [26, 26], "name": "CPF_GFX_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.16 9962 {"bits": [27, 27], "name": "CPF_CMP_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.17 9963 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.18 9964 {"bits": [30, 30], "name": "CPC_CPF_BUSY"}, array in object:register_types.CP_CPF_STATUS.fields.19 9965 {"bits": [31, 31], "name": "CPF_BUSY"} array in object:register_types.CP_CPF_STATUS.fields.20 9970 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, array in object:register_types.CP_DMA_CNTL.fields.0 9971 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, array in object:register_types.CP_DMA_CNTL.fields.1 9972 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, array in object:register_types.CP_DMA_CNTL.fields.2 9973 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, array in object:register_types.CP_DMA_CNTL.fields.3 9974 {"bits": [30, 31], "name": "PIO_COUNT"} array in object:register_types.CP_DMA_CNTL.fields.4 9979 {"bits": [0, 20], "name": "BYTE_COUNT"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.0 9980 {"bits": [21, 21], "name": "DIS_WC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.1 9981 {"bits": [22, 23], "name": "SRC_SWAP"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.2 9982 {"bits": [24, 25], "name": "DST_SWAP"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.3 9983 {"bits": [26, 26], "name": "SAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.4 9984 {"bits": [27, 27], "name": "DAS"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.5 9985 {"bits": [28, 28], "name": "SAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.6 9986 {"bits": [29, 29], "name": "DAIC"}, array in object:register_types.CP_DMA_ME_COMMAND.fields.7 9987 {"bits": [30, 30], "name": "RAW_WAIT"} array in object:register_types.CP_DMA_ME_COMMAND.fields.8 9992 {"bits": [10, 11], "name": "SRC_MTYPE"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.0 9993 {"bits": [12, 12], "name": "SRC_ATC"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.1 9994 {"bits": [13, 13], "name": "SRC_CACHE_POLICY"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.2 9995 {"bits": [20, 21], "name": "DST_SELECT"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.3 9996 {"bits": [22, 23], "name": "DST_MTYPE"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.4 9997 {"bits": [24, 24], "name": "DST_ATC"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.5 9998 {"bits": [25, 25], "name": "DST_CACHE_POLICY"}, array in object:register_types.CP_DMA_ME_CONTROL.fields.6 9999 {"bits": [29, 30], "name": "SRC_SELECT"} array in object:register_types.CP_DMA_ME_CONTROL.fields.7 10004 {"bits": [0, 15], "name": "DST_ADDR_HI"} array in object:register_types.CP_DMA_ME_DST_ADDR_HI.fields.0 10009 {"bits": [0, 15], "name": "SRC_ADDR_HI"} array in object:register_types.CP_DMA_ME_SRC_ADDR_HI.fields.0 10014 {"bits": [0, 25], "name": "DMA_READ_TAG"}, array in object:register_types.CP_DMA_READ_TAGS.fields.0 10015 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} array in object:register_types.CP_DMA_READ_TAGS.fields.1 10020 {"bits": [0, 15], "name": "COUNT"} array in object:register_types.CP_DRAW_OBJECT_COUNTER.fields.0 10025 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.0 10026 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.1 10027 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"}, array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.2 10028 {"bits": [8, 8], "name": "MODE"} array in object:register_types.CP_DRAW_WINDOW_CNTL.fields.3 10033 {"bits": [0, 15], "name": "MIN"}, array in object:register_types.CP_DRAW_WINDOW_LO.fields.0 10034 {"bits": [16, 31], "name": "MAX"} array in object:register_types.CP_DRAW_WINDOW_LO.fields.1 10039 {"bits": [0, 15], "name": "ADDR_HI"} array in object:register_types.CP_EOP_DONE_ADDR_HI.fields.0 10044 {"bits": [2, 31], "name": "ADDR_LO"} array in object:register_types.CP_EOP_DONE_ADDR_LO.fields.0 10049 {"bits": [0, 27], "name": "CNTX_ID"} array in object:register_types.CP_EOP_DONE_CNTX_ID.fields.0 10054 {"bits": [0, 15], "name": "CNTX_ID"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.0 10055 {"bits": [16, 17], "name": "DST_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.1 10056 {"bits": [24, 26], "name": "INT_SEL"}, array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.2 10057 {"bits": [29, 31], "name": "DATA_SEL"} array in object:register_types.CP_EOP_DONE_DATA_CNTL.fields.3 10062 {"bits": [0, 6], "name": "WBINV_TC_OP"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.0 10063 {"bits": [12, 17], "name": "WBINV_ACTION_ENA"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.1 10064 {"bits": [25, 25], "name": "CACHE_CONTROL"}, array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.2 10065 {"bits": [27, 28], "name": "MTYPE"} array in object:register_types.CP_EOP_DONE_EVENT_CNTL.fields.3 10070 {"bits": [0, 19], "name": "IB1_OFFSET"} array in object:register_types.CP_IB1_OFFSET.fields.0 10075 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} array in object:register_types.CP_IB1_PREAMBLE_BEGIN.fields.0 10080 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} array in object:register_types.CP_IB1_PREAMBLE_END.fields.0 10085 {"bits": [0, 19], "name": "IB2_OFFSET"} array in object:register_types.CP_IB2_OFFSET.fields.0 10090 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} array in object:register_types.CP_IB2_PREAMBLE_BEGIN.fields.0 10095 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} array in object:register_types.CP_IB2_PREAMBLE_END.fields.0 10100 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} array in object:register_types.CP_INDEX_TYPE.fields.0 10105 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"}, array in object:register_types.CP_ME_MC_RADDR_HI.fields.0 10106 {"bits": [20, 21], "name": "MTYPE"}, array in object:register_types.CP_ME_MC_RADDR_HI.fields.1 10107 {"bits": [22, 22], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_RADDR_HI.fields.2 10112 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"}, array in object:register_types.CP_ME_MC_RADDR_LO.fields.0 10113 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} array in object:register_types.CP_ME_MC_RADDR_LO.fields.1 10118 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"}, array in object:register_types.CP_ME_MC_WADDR_HI.fields.0 10119 {"bits": [20, 21], "name": "MTYPE"}, array in object:register_types.CP_ME_MC_WADDR_HI.fields.1 10120 {"bits": [22, 22], "name": "CACHE_POLICY"} array in object:register_types.CP_ME_MC_WADDR_HI.fields.2 10125 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"}, array in object:register_types.CP_ME_MC_WADDR_LO.fields.0 10126 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} array in object:register_types.CP_ME_MC_WADDR_LO.fields.1 10131 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.0 10132 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, array in object:register_types.CP_PERFMON_CNTL.fields.1 10133 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, array in object:register_types.CP_PERFMON_CNTL.fields.2 10134 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.CP_PERFMON_CNTL.fields.3 10139 {"bits": [31, 31], "name": "PERFMON_ENABLE"} array in object:register_types.CP_PERFMON_CNTX_CNTL.fields.0 10144 {"bits": [0, 1], "name": "STATUS"} array in object:register_types.CP_PFP_COMPLETION_STATUS.fields.0 10149 {"bits": [0, 7], "name": "IB_EN"} array in object:register_types.CP_PFP_IB_CONTROL.fields.0 10154 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.0 10155 {"bits": [1, 1], "name": "CNTX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.1 10156 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, array in object:register_types.CP_PFP_LOAD_CONTROL.fields.2 10157 {"bits": [24, 24], "name": "SH_CS_REG_EN"} array in object:register_types.CP_PFP_LOAD_CONTROL.fields.3 10162 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"} array in object:register_types.CP_PIPE_STATS_ADDR_HI.fields.0 10167 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} array in object:register_types.CP_PIPE_STATS_ADDR_LO.fields.0 10172 {"bits": [25, 25], "name": "CACHE_CONTROL"}, array in object:register_types.CP_PIPE_STATS_CONTROL.fields.0 10173 {"bits": [27, 28], "name": "MTYPE"} array in object:register_types.CP_PIPE_STATS_CONTROL.fields.1 10178 {"bits": [0, 0], "name": "NOT_VISIBLE"} array in object:register_types.CP_PRED_NOT_VISIBLE.fields.0 10183 {"bits": [0, 19], "name": "RB_OFFSET"} array in object:register_types.CP_RB_OFFSET.fields.0 10188 {"bits": [0, 1], "name": "RINGID"} array in object:register_types.CP_RINGID.fields.0 10193 {"bits": [0, 0], "name": "Z_PASS_ACITVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.0 10194 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.1 10195 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.2 10196 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.3 10197 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.4 10198 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.5 10199 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"}, array in object:register_types.CP_SAMPLE_STATUS.fields.6 10200 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"} array in object:register_types.CP_SAMPLE_STATUS.fields.7 10205 {"bits": [0, 7], "name": "SCRATCH_INDEX"} array in object:register_types.CP_SCRATCH_INDEX.fields.0 10210 {"bits": [0, 15], "name": "SEM_ADDR_HI"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.0 10211 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.1 10212 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.2 10213 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.3 10214 {"bits": [29, 31], "name": "SEM_SELECT"} array in object:register_types.CP_SIG_SEM_ADDR_HI.fields.4 10219 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.0 10220 {"bits": [3, 31], "name": "SEM_ADDR_LO"} array in object:register_types.CP_SIG_SEM_ADDR_LO.fields.1 10225 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"} array in object:register_types.CP_STREAM_OUT_ADDR_HI.fields.0 10230 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} array in object:register_types.CP_STREAM_OUT_ADDR_LO.fields.0 10235 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} array in object:register_types.CP_STRMOUT_CNTL.fields.0 10240 {"bits": [0, 15], "name": "ST_BASE_HI"} array in object:register_types.CP_ST_BASE_HI.fields.0 10245 {"bits": [2, 31], "name": "ST_BASE_LO"} array in object:register_types.CP_ST_BASE_LO.fields.0 10250 {"bits": [0, 19], "name": "ST_BUFSZ"} array in object:register_types.CP_ST_BUFSZ.fields.0 10255 {"bits": [0, 3], "name": "VMID"} array in object:register_types.CP_VMID.fields.0 10260 {"bits": [0, 2], "name": "SRC_STATE_ID"} array in object:register_types.CS_COPY_STATE.fields.0 10265 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.0 10266 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.1 10267 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.2 10268 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.3 10269 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, array in object:register_types.DB_ALPHA_TO_MASK.fields.4 10270 {"bits": [16, 16], "name": "OFFSET_ROUND"} array in object:register_types.DB_ALPHA_TO_MASK.fields.5 10275 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.0 10276 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, array in object:register_types.DB_COUNT_CONTROL.fields.1 10277 {"bits": [4, 6], "name": "SAMPLE_RATE"}, array in object:register_types.DB_COUNT_CONTROL.fields.2 10278 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.3 10279 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.4 10280 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.5 10281 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.6 10282 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.DB_COUNT_CONTROL.fields.7 10283 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} array in object:register_types.DB_COUNT_CONTROL.fields.8 10288 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.0 10289 {"bits": [1, 1], "name": "Z_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.1 10290 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.2 10291 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.3 10292 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.4 10293 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, array in object:register_types.DB_DEPTH_CONTROL.fields.5 10294 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, array in object:register_types.DB_DEPTH_CONTROL.fields.6 10295 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, array in object:register_types.DB_DEPTH_CONTROL.fields.7 10296 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, array in object:register_types.DB_DEPTH_CONTROL.fields.8 10297 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} array in object:register_types.DB_DEPTH_CONTROL.fields.9 10302 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"}, array in object:register_types.DB_DEPTH_INFO.fields.0 10303 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.DB_DEPTH_INFO.fields.1 10304 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.DB_DEPTH_INFO.fields.2 10305 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, array in object:register_types.DB_DEPTH_INFO.fields.3 10306 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, array in object:register_types.DB_DEPTH_INFO.fields.4 10307 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, array in object:register_types.DB_DEPTH_INFO.fields.5 10308 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} array in object:register_types.DB_DEPTH_INFO.fields.6 10313 {"bits": [0, 10], "name": "PITCH_TILE_MAX"}, array in object:register_types.DB_DEPTH_SIZE.fields.0 10314 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"} array in object:register_types.DB_DEPTH_SIZE.fields.1 10319 {"bits": [0, 21], "name": "SLICE_TILE_MAX"} array in object:register_types.DB_DEPTH_SLICE.fields.0 10324 {"bits": [0, 10], "name": "SLICE_START"}, array in object:register_types.DB_DEPTH_VIEW.fields.0 10325 {"bits": [13, 23], "name": "SLICE_MAX"}, array in object:register_types.DB_DEPTH_VIEW.fields.1 10326 {"bits": [24, 24], "name": "Z_READ_ONLY"}, array in object:register_types.DB_DEPTH_VIEW.fields.2 10327 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"} array in object:register_types.DB_DEPTH_VIEW.fields.3 10332 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, array in object:register_types.DB_EQAA.fields.0 10333 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, array in object:register_types.DB_EQAA.fields.1 10334 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.2 10335 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, array in object:register_types.DB_EQAA.fields.3 10336 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, array in object:register_types.DB_EQAA.fields.4 10337 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, array in object:register_types.DB_EQAA.fields.5 10338 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, array in object:register_types.DB_EQAA.fields.6 10339 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, array in object:register_types.DB_EQAA.fields.7 10340 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, array in object:register_types.DB_EQAA.fields.8 10341 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, array in object:register_types.DB_EQAA.fields.9 10342 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, array in object:register_types.DB_EQAA.fields.10 10343 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} array in object:register_types.DB_EQAA.fields.11 10348 {"bits": [0, 0], "name": "LINEAR"}, array in object:register_types.DB_HTILE_SURFACE.fields.0 10349 {"bits": [1, 1], "name": "FULL_CACHE"}, array in object:register_types.DB_HTILE_SURFACE.fields.1 10350 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, array in object:register_types.DB_HTILE_SURFACE.fields.2 10351 {"bits": [3, 3], "name": "PRELOAD"}, array in object:register_types.DB_HTILE_SURFACE.fields.3 10352 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, array in object:register_types.DB_HTILE_SURFACE.fields.4 10353 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, array in object:register_types.DB_HTILE_SURFACE.fields.5 10354 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}, array in object:register_types.DB_HTILE_SURFACE.fields.6 10355 {"bits": [17, 17], "name": "TC_COMPATIBLE"} array in object:register_types.DB_HTILE_SURFACE.fields.7 10360 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.0 10361 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.1 10362 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.2 10363 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.3 10364 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.DB_PERFCOUNTER0_SELECT.fields.4 10369 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.0 10370 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.1 10371 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.2 10372 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.DB_PERFCOUNTER0_SELECT1.fields.3 10377 {"bits": [0, 7], "name": "START_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.0 10378 {"bits": [8, 15], "name": "START_Y"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.1 10379 {"bits": [16, 23], "name": "MAX_X"}, array in object:register_types.DB_PRELOAD_CONTROL.fields.2 10380 {"bits": [24, 31], "name": "MAX_Y"} array in object:register_types.DB_PRELOAD_CONTROL.fields.3 10385 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.0 10386 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.1 10387 {"bits": [2, 2], "name": "DEPTH_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.2 10388 {"bits": [3, 3], "name": "STENCIL_COPY"}, array in object:register_types.DB_RENDER_CONTROL.fields.3 10389 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.4 10390 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.5 10391 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.6 10392 {"bits": [7, 7], "name": "COPY_CENTROID"}, array in object:register_types.DB_RENDER_CONTROL.fields.7 10393 {"bits": [8, 11], "name": "COPY_SAMPLE"}, array in object:register_types.DB_RENDER_CONTROL.fields.8 10394 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"} array in object:register_types.DB_RENDER_CONTROL.fields.9 10399 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.0 10400 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.1 10401 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.2 10402 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.3 10403 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.4 10404 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.5 10405 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.6 10406 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.7 10407 {"bits": [11, 11], "name": "FORCE_Z_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.8 10408 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.9 10409 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.10 10410 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.11 10411 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.12 10412 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.13 10413 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.14 10414 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.15 10415 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.16 10416 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.17 10417 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.18 10418 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.19 10419 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.20 10420 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, array in object:register_types.DB_RENDER_OVERRIDE.fields.21 10421 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} array in object:register_types.DB_RENDER_OVERRIDE.fields.22 10426 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.0 10427 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.1 10428 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.2 10429 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.3 10430 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.4 10431 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.5 10432 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.6 10433 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.7 10434 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.8 10435 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.9 10436 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.10 10437 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.11 10438 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.12 10439 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, array in object:register_types.DB_RENDER_OVERRIDE2.fields.13 10440 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"} array in object:register_types.DB_RENDER_OVERRIDE2.fields.14 10445 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.0 10446 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.1 10447 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.2 10448 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, array in object:register_types.DB_SHADER_CONTROL.fields.3 10449 {"bits": [6, 6], "name": "KILL_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.4 10450 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.5 10451 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.6 10452 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, array in object:register_types.DB_SHADER_CONTROL.fields.7 10453 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, array in object:register_types.DB_SHADER_CONTROL.fields.8 10454 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, array in object:register_types.DB_SHADER_CONTROL.fields.9 10455 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, array in object:register_types.DB_SHADER_CONTROL.fields.10 10456 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, array in object:register_types.DB_SHADER_CONTROL.fields.11 10457 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"} array in object:register_types.DB_SHADER_CONTROL.fields.12 10462 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0 10463 {"bits": [4, 11], "name": "COMPAREVALUE0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.1 10464 {"bits": [12, 19], "name": "COMPAREMASK0"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.2 10465 {"bits": [24, 24], "name": "ENABLE0"} array in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.3 10470 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0 10471 {"bits": [4, 11], "name": "COMPAREVALUE1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.1 10472 {"bits": [12, 19], "name": "COMPAREMASK1"}, array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.2 10473 {"bits": [24, 24], "name": "ENABLE1"} array in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.3 10478 {"bits": [0, 7], "name": "STENCILTESTVAL"}, array in object:register_types.DB_STENCILREFMASK.fields.0 10479 {"bits": [8, 15], "name": "STENCILMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.1 10480 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, array in object:register_types.DB_STENCILREFMASK.fields.2 10481 {"bits": [24, 31], "name": "STENCILOPVAL"} array in object:register_types.DB_STENCILREFMASK.fields.3 10486 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.0 10487 {"bits": [8, 15], "name": "STENCILMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.1 10488 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, array in object:register_types.DB_STENCILREFMASK_BF.fields.2 10489 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} array in object:register_types.DB_STENCILREFMASK_BF.fields.3 10494 {"bits": [0, 7], "name": "CLEAR"} array in object:register_types.DB_STENCIL_CLEAR.fields.0 10499 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.0 10500 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, array in object:register_types.DB_STENCIL_CONTROL.fields.1 10501 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, array in object:register_types.DB_STENCIL_CONTROL.fields.2 10502 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.3 10503 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, array in object:register_types.DB_STENCIL_CONTROL.fields.4 10504 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} array in object:register_types.DB_STENCIL_CONTROL.fields.5 10509 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, array in object:register_types.DB_STENCIL_INFO.fields.0 10510 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.DB_STENCIL_INFO.fields.1 10511 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, array in object:register_types.DB_STENCIL_INFO.fields.2 10512 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_STENCIL_INFO.fields.3 10513 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}, array in object:register_types.DB_STENCIL_INFO.fields.4 10514 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"} array in object:register_types.DB_STENCIL_INFO.fields.5 10519 {"bits": [0, 30], "name": "COUNT_HI"} array in object:register_types.DB_ZPASS_COUNT_HI.fields.0 10524 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, array in object:register_types.DB_Z_INFO.fields.0 10525 {"bits": [2, 3], "name": "NUM_SAMPLES"}, array in object:register_types.DB_Z_INFO.fields.1 10526 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.DB_Z_INFO.fields.2 10527 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, array in object:register_types.DB_Z_INFO.fields.3 10528 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"}, array in object:register_types.DB_Z_INFO.fields.4 10529 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, array in object:register_types.DB_Z_INFO.fields.5 10530 {"bits": [28, 28], "name": "READ_SIZE"}, array in object:register_types.DB_Z_INFO.fields.6 10531 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, array in object:register_types.DB_Z_INFO.fields.7 10532 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}, array in object:register_types.DB_Z_INFO.fields.8 10533 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} array in object:register_types.DB_Z_INFO.fields.9 10538 {"bits": [0, 2], "name": "NUM_PIPES"}, array in object:register_types.GB_ADDR_CONFIG.fields.0 10539 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.1 10540 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.2 10541 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"}, array in object:register_types.GB_ADDR_CONFIG.fields.3 10542 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.4 10543 {"bits": [20, 22], "name": "NUM_GPUS"}, array in object:register_types.GB_ADDR_CONFIG.fields.5 10544 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.6 10545 {"bits": [28, 29], "name": "ROW_SIZE"}, array in object:register_types.GB_ADDR_CONFIG.fields.7 10546 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"} array in object:register_types.GB_ADDR_CONFIG.fields.8 10551 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, array in object:register_types.GB_MACROTILE_MODE0.fields.0 10552 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.1 10553 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, array in object:register_types.GB_MACROTILE_MODE0.fields.2 10554 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} array in object:register_types.GB_MACROTILE_MODE0.fields.3 10559 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, array in object:register_types.GB_TILE_MODE0.fields.0 10560 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, array in object:register_types.GB_TILE_MODE0.fields.1 10561 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, array in object:register_types.GB_TILE_MODE0.fields.2 10562 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, array in object:register_types.GB_TILE_MODE0.fields.3 10563 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} array in object:register_types.GB_TILE_MODE0.fields.4 10568 {"bits": [0, 15], "name": "BASE"}, array in object:register_types.GDS_ATOM_BASE.fields.0 10569 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_BASE.fields.1 10574 {"bits": [0, 5], "name": "AINC"}, array in object:register_types.GDS_ATOM_CNTL.fields.0 10575 {"bits": [6, 7], "name": "UNUSED1"}, array in object:register_types.GDS_ATOM_CNTL.fields.1 10576 {"bits": [8, 9], "name": "DMODE"}, array in object:register_types.GDS_ATOM_CNTL.fields.2 10577 {"bits": [10, 31], "name": "UNUSED2"} array in object:register_types.GDS_ATOM_CNTL.fields.3 10582 {"bits": [0, 0], "name": "COMPLETE"}, array in object:register_types.GDS_ATOM_COMPLETE.fields.0 10583 {"bits": [1, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_COMPLETE.fields.1 10588 {"bits": [0, 7], "name": "OFFSET0"}, array in object:register_types.GDS_ATOM_OFFSET0.fields.0 10589 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET0.fields.1 10594 {"bits": [0, 7], "name": "OFFSET1"}, array in object:register_types.GDS_ATOM_OFFSET1.fields.0 10595 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OFFSET1.fields.1 10600 {"bits": [0, 7], "name": "OP"}, array in object:register_types.GDS_ATOM_OP.fields.0 10601 {"bits": [8, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_OP.fields.1 10606 {"bits": [0, 15], "name": "SIZE"}, array in object:register_types.GDS_ATOM_SIZE.fields.0 10607 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_ATOM_SIZE.fields.1 10612 {"bits": [0, 0], "name": "FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.0 10613 {"bits": [1, 12], "name": "COUNTER"}, array in object:register_types.GDS_GWS_RESOURCE.fields.1 10614 {"bits": [13, 13], "name": "TYPE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.2 10615 {"bits": [14, 14], "name": "DED"}, array in object:register_types.GDS_GWS_RESOURCE.fields.3 10616 {"bits": [15, 15], "name": "RELEASE_ALL"}, array in object:register_types.GDS_GWS_RESOURCE.fields.4 10617 {"bits": [16, 27], "name": "HEAD_QUEUE"}, array in object:register_types.GDS_GWS_RESOURCE.fields.5 10618 {"bits": [28, 28], "name": "HEAD_VALID"}, array in object:register_types.GDS_GWS_RESOURCE.fields.6 10619 {"bits": [29, 29], "name": "HEAD_FLAG"}, array in object:register_types.GDS_GWS_RESOURCE.fields.7 10620 {"bits": [30, 31], "name": "UNUSED1"} array in object:register_types.GDS_GWS_RESOURCE.fields.8 10625 {"bits": [0, 15], "name": "RESOURCE_CNT"}, array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.0 10626 {"bits": [16, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNT.fields.1 10631 {"bits": [0, 5], "name": "INDEX"}, array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.0 10632 {"bits": [6, 31], "name": "UNUSED"} array in object:register_types.GDS_GWS_RESOURCE_CNTL.fields.1 10637 {"bits": [0, 15], "name": "DS_ADDRESS"}, array in object:register_types.GDS_OA_ADDRESS.fields.0 10638 {"bits": [16, 19], "name": "CRAWLER"}, array in object:register_types.GDS_OA_ADDRESS.fields.1 10639 {"bits": [20, 21], "name": "CRAWLER_TYPE"}, array in object:register_types.GDS_OA_ADDRESS.fields.2 10640 {"bits": [22, 29], "name": "UNUSED"}, array in object:register_types.GDS_OA_ADDRESS.fields.3 10641 {"bits": [30, 30], "name": "NO_ALLOC"}, array in object:register_types.GDS_OA_ADDRESS.fields.4 10642 {"bits": [31, 31], "name": "ENABLE"} array in object:register_types.GDS_OA_ADDRESS.fields.5 10647 {"bits": [0, 3], "name": "INDEX"}, array in object:register_types.GDS_OA_CNTL.fields.0 10648 {"bits": [4, 31], "name": "UNUSED"} array in object:register_types.GDS_OA_CNTL.fields.1 10653 {"bits": [0, 30], "name": "VALUE"}, array in object:register_types.GDS_OA_INCDEC.fields.0 10654 {"bits": [31, 31], "name": "INCDEC"} array in object:register_types.GDS_OA_INCDEC.fields.1 10659 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.0 10660 {"bits": [8, 15], "name": "SH_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.1 10661 {"bits": [16, 23], "name": "SE_INDEX"}, array in object:register_types.GRBM_GFX_INDEX.fields.2 10662 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.3 10663 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, array in object:register_types.GRBM_GFX_INDEX.fields.4 10664 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} array in object:register_types.GRBM_GFX_INDEX.fields.5 10669 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.0 10670 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.1 10671 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.2 10672 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.3 10673 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.4 10674 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.5 10675 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.6 10676 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.7 10677 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.8 10678 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.9 10679 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.10 10680 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.11 10681 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.12 10682 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.13 10683 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.14 10684 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.15 10685 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.16 10686 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.17 10687 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_PERFCOUNTER0_SELECT.fields.18 10692 {"bits": [0, 5], "name": "PERF_SEL"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.0 10693 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.1 10694 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.2 10695 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.3 10696 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.4 10697 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.5 10698 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.6 10699 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.7 10700 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.8 10701 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.9 10702 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.10 10703 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"} array in object:register_types.GRBM_SE0_PERFCOUNTER_SELECT.fields.11 10708 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS.fields.0 10709 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.1 10710 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.2 10711 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.3 10712 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, array in object:register_types.GRBM_STATUS.fields.4 10713 {"bits": [12, 12], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.5 10714 {"bits": [13, 13], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS.fields.6 10715 {"bits": [14, 14], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.7 10716 {"bits": [15, 15], "name": "GDS_BUSY"}, array in object:register_types.GRBM_STATUS.fields.8 10717 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.9 10718 {"bits": [17, 17], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS.fields.10 10719 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, array in object:register_types.GRBM_STATUS.fields.11 10720 {"bits": [19, 19], "name": "IA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.12 10721 {"bits": [20, 20], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS.fields.13 10722 {"bits": [21, 21], "name": "WD_BUSY"}, array in object:register_types.GRBM_STATUS.fields.14 10723 {"bits": [22, 22], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.15 10724 {"bits": [23, 23], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS.fields.16 10725 {"bits": [24, 24], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS.fields.17 10726 {"bits": [25, 25], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS.fields.18 10727 {"bits": [26, 26], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.19 10728 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, array in object:register_types.GRBM_STATUS.fields.20 10729 {"bits": [29, 29], "name": "CP_BUSY"}, array in object:register_types.GRBM_STATUS.fields.21 10730 {"bits": [30, 30], "name": "CB_BUSY"}, array in object:register_types.GRBM_STATUS.fields.22 10731 {"bits": [31, 31], "name": "GUI_ACTIVE"} array in object:register_types.GRBM_STATUS.fields.23 10736 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, array in object:register_types.GRBM_STATUS2.fields.0 10737 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.1 10738 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.2 10739 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.3 10740 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.4 10741 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.5 10742 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.6 10743 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.7 10744 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.8 10745 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.9 10746 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.10 10747 {"bits": [14, 14], "name": "RLC_RQ_PENDING"}, array in object:register_types.GRBM_STATUS2.fields.11 10748 {"bits": [24, 24], "name": "RLC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.12 10749 {"bits": [25, 25], "name": "TC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.13 10750 {"bits": [26, 26], "name": "TCC_CC_RESIDENT"}, array in object:register_types.GRBM_STATUS2.fields.14 10751 {"bits": [28, 28], "name": "CPF_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.15 10752 {"bits": [29, 29], "name": "CPC_BUSY"}, array in object:register_types.GRBM_STATUS2.fields.16 10753 {"bits": [30, 30], "name": "CPG_BUSY"} array in object:register_types.GRBM_STATUS2.fields.17 10758 {"bits": [1, 1], "name": "DB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.0 10759 {"bits": [2, 2], "name": "CB_CLEAN"}, array in object:register_types.GRBM_STATUS_SE0.fields.1 10760 {"bits": [22, 22], "name": "BCI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.2 10761 {"bits": [23, 23], "name": "VGT_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.3 10762 {"bits": [24, 24], "name": "PA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.4 10763 {"bits": [25, 25], "name": "TA_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.5 10764 {"bits": [26, 26], "name": "SX_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.6 10765 {"bits": [27, 27], "name": "SPI_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.7 10766 {"bits": [29, 29], "name": "SC_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.8 10767 {"bits": [30, 30], "name": "DB_BUSY"}, array in object:register_types.GRBM_STATUS_SE0.fields.9 10768 {"bits": [31, 31], "name": "CB_BUSY"} array in object:register_types.GRBM_STATUS_SE0.fields.10 10773 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.0 10774 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.1 10775 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.2 10776 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.3 10777 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.4 10778 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}, array in object:register_types.IA_MULTI_VGT_PARAM.fields.5 10779 {"bits": [28, 31], "name": "MAX_PRIMGRP_IN_WAVE"} array in object:register_types.IA_MULTI_VGT_PARAM.fields.6 10784 {"bits": [0, 0], "name": "UCP_ENA_0"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.0 10785 {"bits": [1, 1], "name": "UCP_ENA_1"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.1 10786 {"bits": [2, 2], "name": "UCP_ENA_2"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.2 10787 {"bits": [3, 3], "name": "UCP_ENA_3"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.3 10788 {"bits": [4, 4], "name": "UCP_ENA_4"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.4 10789 {"bits": [5, 5], "name": "UCP_ENA_5"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.5 10790 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.6 10791 {"bits": [14, 15], "name": "PS_UCP_MODE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.7 10792 {"bits": [16, 16], "name": "CLIP_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.8 10793 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.9 10794 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.10 10795 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.11 10796 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.12 10797 {"bits": [21, 21], "name": "VTX_KILL_OR"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.13 10798 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.14 10799 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.15 10800 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.16 10801 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, array in object:register_types.PA_CL_CLIP_CNTL.fields.17 10802 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"} array in object:register_types.PA_CL_CLIP_CNTL.fields.18 10807 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.0 10808 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.1 10809 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.2 10810 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.3 10811 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.4 10812 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.5 10813 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.6 10814 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.7 10815 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.8 10816 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.9 10817 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.10 10818 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.11 10819 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.12 10820 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.13 10821 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, array in object:register_types.PA_CL_NANINF_CNTL.fields.14 10822 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} array in object:register_types.PA_CL_NANINF_CNTL.fields.15 10827 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.0 10828 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.1 10829 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.2 10830 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.3 10831 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.4 10832 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.5 10833 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.6 10834 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.7 10835 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.8 10836 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.9 10837 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.10 10838 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.11 10839 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.12 10840 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.13 10841 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.14 10842 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.15 10843 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.16 10844 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.17 10845 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.18 10846 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.19 10847 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.20 10848 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.21 10849 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.22 10850 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.23 10851 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.24 10852 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}, array in object:register_types.PA_CL_VS_OUT_CNTL.fields.25 10853 {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"} array in object:register_types.PA_CL_VS_OUT_CNTL.fields.26 10858 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.0 10859 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.1 10860 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.2 10861 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.3 10862 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.4 10863 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, array in object:register_types.PA_CL_VTE_CNTL.fields.5 10864 {"bits": [8, 8], "name": "VTX_XY_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.6 10865 {"bits": [9, 9], "name": "VTX_Z_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.7 10866 {"bits": [10, 10], "name": "VTX_W0_FMT"}, array in object:register_types.PA_CL_VTE_CNTL.fields.8 10867 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} array in object:register_types.PA_CL_VTE_CNTL.fields.9 10872 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.0 10873 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, array in object:register_types.PA_SC_AA_CONFIG.fields.1 10874 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, array in object:register_types.PA_SC_AA_CONFIG.fields.2 10875 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, array in object:register_types.PA_SC_AA_CONFIG.fields.3 10876 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"} array in object:register_types.PA_SC_AA_CONFIG.fields.4 10881 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.0 10882 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} array in object:register_types.PA_SC_AA_MASK_X0Y0_X1Y0.fields.1 10887 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.0 10888 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} array in object:register_types.PA_SC_AA_MASK_X0Y1_X1Y1.fields.1 10893 {"bits": [0, 3], "name": "S0_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.0 10894 {"bits": [4, 7], "name": "S0_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.1 10895 {"bits": [8, 11], "name": "S1_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.2 10896 {"bits": [12, 15], "name": "S1_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.3 10897 {"bits": [16, 19], "name": "S2_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.4 10898 {"bits": [20, 23], "name": "S2_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.5 10899 {"bits": [24, 27], "name": "S3_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.6 10900 {"bits": [28, 31], "name": "S3_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0.fields.7 10905 {"bits": [0, 3], "name": "S4_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.0 10906 {"bits": [4, 7], "name": "S4_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.1 10907 {"bits": [8, 11], "name": "S5_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.2 10908 {"bits": [12, 15], "name": "S5_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.3 10909 {"bits": [16, 19], "name": "S6_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.4 10910 {"bits": [20, 23], "name": "S6_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.5 10911 {"bits": [24, 27], "name": "S7_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.6 10912 {"bits": [28, 31], "name": "S7_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1.fields.7 10917 {"bits": [0, 3], "name": "S8_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.0 10918 {"bits": [4, 7], "name": "S8_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.1 10919 {"bits": [8, 11], "name": "S9_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.2 10920 {"bits": [12, 15], "name": "S9_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.3 10921 {"bits": [16, 19], "name": "S10_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.4 10922 {"bits": [20, 23], "name": "S10_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.5 10923 {"bits": [24, 27], "name": "S11_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.6 10924 {"bits": [28, 31], "name": "S11_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2.fields.7 10929 {"bits": [0, 3], "name": "S12_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.0 10930 {"bits": [4, 7], "name": "S12_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.1 10931 {"bits": [8, 11], "name": "S13_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.2 10932 {"bits": [12, 15], "name": "S13_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.3 10933 {"bits": [16, 19], "name": "S14_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.4 10934 {"bits": [20, 23], "name": "S14_Y"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.5 10935 {"bits": [24, 27], "name": "S15_X"}, array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.6 10936 {"bits": [28, 31], "name": "S15_Y"} array in object:register_types.PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3.fields.7 10941 {"bits": [0, 3], "name": "DISTANCE_0"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.0 10942 {"bits": [4, 7], "name": "DISTANCE_1"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.1 10943 {"bits": [8, 11], "name": "DISTANCE_2"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.2 10944 {"bits": [12, 15], "name": "DISTANCE_3"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.3 10945 {"bits": [16, 19], "name": "DISTANCE_4"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.4 10946 {"bits": [20, 23], "name": "DISTANCE_5"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.5 10947 {"bits": [24, 27], "name": "DISTANCE_6"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.6 10948 {"bits": [28, 31], "name": "DISTANCE_7"} array in object:register_types.PA_SC_CENTROID_PRIORITY_0.fields.7 10953 {"bits": [0, 3], "name": "DISTANCE_8"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.0 10954 {"bits": [4, 7], "name": "DISTANCE_9"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.1 10955 {"bits": [8, 11], "name": "DISTANCE_10"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.2 10956 {"bits": [12, 15], "name": "DISTANCE_11"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.3 10957 {"bits": [16, 19], "name": "DISTANCE_12"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.4 10958 {"bits": [20, 23], "name": "DISTANCE_13"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.5 10959 {"bits": [24, 27], "name": "DISTANCE_14"}, array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.6 10960 {"bits": [28, 31], "name": "DISTANCE_15"} array in object:register_types.PA_SC_CENTROID_PRIORITY_1.fields.7 10965 {"bits": [0, 14], "name": "BR_X"}, array in object:register_types.PA_SC_CLIPRECT_0_BR.fields.0 10966 {"bits": [16, 30], "name": "BR_Y"} array in object:register_types.PA_SC_CLIPRECT_0_BR.fields.1 10971 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.0 10972 {"bits": [16, 30], "name": "TL_Y"} array in object:register_types.PA_SC_CLIPRECT_0_TL.fields.1 10977 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} array in object:register_types.PA_SC_CLIPRECT_RULE.fields.0 10982 {"bits": [0, 3], "name": "ER_TRI"}, array in object:register_types.PA_SC_EDGERULE.fields.0 10983 {"bits": [4, 7], "name": "ER_POINT"}, array in object:register_types.PA_SC_EDGERULE.fields.1 10984 {"bits": [8, 11], "name": "ER_RECT"}, array in object:register_types.PA_SC_EDGERULE.fields.2 10985 {"bits": [12, 17], "name": "ER_LINE_LR"}, array in object:register_types.PA_SC_EDGERULE.fields.3 10986 {"bits": [18, 23], "name": "ER_LINE_RL"}, array in object:register_types.PA_SC_EDGERULE.fields.4 10987 {"bits": [24, 27], "name": "ER_LINE_TB"}, array in object:register_types.PA_SC_EDGERULE.fields.5 10988 {"bits": [28, 31], "name": "ER_LINE_BT"} array in object:register_types.PA_SC_EDGERULE.fields.6 10993 {"bits": [0, 14], "name": "TL_X"}, array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.0 10994 {"bits": [16, 30], "name": "TL_Y"}, array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.1 10995 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} array in object:register_types.PA_SC_GENERIC_SCISSOR_TL.fields.2 11000 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, array in object:register_types.PA_SC_LINE_CNTL.fields.0 11001 {"bits": [10, 10], "name": "LAST_PIXEL"}, array in object:register_types.PA_SC_LINE_CNTL.fields.1 11002 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, array in object:register_types.PA_SC_LINE_CNTL.fields.2 11003 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"} array in object:register_types.PA_SC_LINE_CNTL.fields.3 11008 {"bits": [0, 15], "name": "LINE_PATTERN"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.0 11009 {"bits": [16, 23], "name": "REPEAT_COUNT"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.1 11010 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, array in object:register_types.PA_SC_LINE_STIPPLE.fields.2 11011 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} array in object:register_types.PA_SC_LINE_STIPPLE.fields.3 11016 {"bits": [0, 3], "name": "CURRENT_PTR"}, array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.0 11017 {"bits": [8, 15], "name": "CURRENT_COUNT"} array in object:register_types.PA_SC_LINE_STIPPLE_STATE.fields.1 11022 {"bits": [0, 0], "name": "MSAA_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.0 11023 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.1 11024 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_0.fields.2 11025 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"} array in object:register_types.PA_SC_MODE_CNTL_0.fields.3 11030 {"bits": [0, 0], "name": "WALK_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.0 11031 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.1 11032 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.2 11033 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.3 11034 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.4 11035 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.5 11036 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.6 11037 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.7 11038 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.8 11039 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.9 11040 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.10 11041 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.11 11042 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.12 11043 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.13 11044 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.14 11045 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.15 11046 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.16 11047 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.17 11048 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.18 11049 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.19 11050 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.20 11051 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.21 11052 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, array in object:register_types.PA_SC_MODE_CNTL_1.fields.22 11053 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} array in object:register_types.PA_SC_MODE_CNTL_1.fields.23 11058 {"bits": [0, 13], "name": "X_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_H.fields.0 11063 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"}, array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.0 11064 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_HV_EN.fields.1 11069 {"bits": [0, 13], "name": "Y_COORD"} array in object:register_types.PA_SC_P3D_TRAP_SCREEN_V.fields.0 11074 {"bits": [0, 9], "name": "PERF_SEL"} array in object:register_types.PA_SC_PERFCOUNTER1_SELECT.fields.0 11079 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.0 11080 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.1 11081 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.2 11082 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.3 11083 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.4 11084 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.5 11085 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.6 11086 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.7 11087 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.8 11088 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.9 11089 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.10 11090 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.11 11091 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.12 11092 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG.fields.13 11093 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG.fields.14 11098 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0 11099 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1 11100 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} array in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2 11105 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"}, array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.0 11106 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"} array in object:register_types.PA_SC_SCREEN_EXTENT_CONTROL.fields.1 11111 {"bits": [0, 15], "name": "X"}, array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.0 11112 {"bits": [16, 31], "name": "Y"} array in object:register_types.PA_SC_SCREEN_EXTENT_MIN_0.fields.1 11117 {"bits": [0, 15], "name": "BR_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.0 11118 {"bits": [16, 31], "name": "BR_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_BR.fields.1 11123 {"bits": [0, 15], "name": "TL_X"}, array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.0 11124 {"bits": [16, 31], "name": "TL_Y"} array in object:register_types.PA_SC_SCREEN_SCISSOR_TL.fields.1 11129 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"} array in object:register_types.PA_SC_SHADER_CONTROL.fields.0 11134 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, array in object:register_types.PA_SC_WINDOW_OFFSET.fields.0 11135 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} array in object:register_types.PA_SC_WINDOW_OFFSET.fields.1 11140 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.0 11141 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} array in object:register_types.PA_SU_HARDWARE_SCREEN_OFFSET.fields.1 11146 {"bits": [0, 15], "name": "WIDTH"} array in object:register_types.PA_SU_LINE_CNTL.fields.0 11151 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.0 11152 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.1 11153 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.2 11154 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} array in object:register_types.PA_SU_LINE_STIPPLE_CNTL.fields.3 11159 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} array in object:register_types.PA_SU_LINE_STIPPLE_VALUE.fields.0 11164 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} array in object:register_types.PA_SU_PERFCOUNTER0_HI.fields.0 11169 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.0 11170 {"bits": [10, 19], "name": "PERF_SEL1"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.1 11171 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT.fields.2 11176 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.0 11177 {"bits": [10, 19], "name": "PERF_SEL3"} array in object:register_types.PA_SU_PERFCOUNTER0_SELECT1.fields.1 11182 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.0 11183 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.PA_SU_PERFCOUNTER2_SELECT.fields.1 11188 {"bits": [0, 15], "name": "MIN_SIZE"}, array in object:register_types.PA_SU_POINT_MINMAX.fields.0 11189 {"bits": [16, 31], "name": "MAX_SIZE"} array in object:register_types.PA_SU_POINT_MINMAX.fields.1 11194 {"bits": [0, 15], "name": "HEIGHT"}, array in object:register_types.PA_SU_POINT_SIZE.fields.0 11195 {"bits": [16, 31], "name": "WIDTH"} array in object:register_types.PA_SU_POINT_SIZE.fields.1 11200 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.0 11201 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} array in object:register_types.PA_SU_POLY_OFFSET_DB_FMT_CNTL.fields.1 11206 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.0 11207 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.1 11208 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.2 11209 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.3 11210 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.4 11211 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.5 11212 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.6 11213 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.7 11214 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.8 11215 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.9 11216 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} array in object:register_types.PA_SU_PRIM_FILTER_CNTL.fields.10 11221 {"bits": [0, 0], "name": "CULL_FRONT"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.0 11222 {"bits": [1, 1], "name": "CULL_BACK"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.1 11223 {"bits": [2, 2], "name": "FACE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.2 11224 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.3 11225 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ array in object:register_types.PA_SU_SC_MODE_CNTL.fields.4 11226 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE array in object:register_types.PA_SU_SC_MODE_CNTL.fields.5 11227 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.6 11228 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.7 11229 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.8 11230 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.9 11231 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.10 11232 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, array in object:register_types.PA_SU_SC_MODE_CNTL.fields.11 11233 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"} array in object:register_types.PA_SU_SC_MODE_CNTL.fields.12 11238 {"bits": [0, 0], "name": "PIX_CENTER"}, array in object:register_types.PA_SU_VTX_CNTL.fields.0 11239 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, array in object:register_types.PA_SU_VTX_CNTL.fields.1 11240 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} array in object:register_types.PA_SU_VTX_CNTL.fields.2 11245 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"} array in object:register_types.RLC_PERFCOUNTER0_SELECT.fields.0 11250 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"} array in object:register_types.RLC_PERFMON_CLK_CNTL.fields.0 11255 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, array in object:register_types.RLC_PERFMON_CNTL.fields.0 11256 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} array in object:register_types.RLC_PERFMON_CNTL.fields.1 11261 {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"}, array in object:register_types.RLC_SPM_CPG_PERFMON_SAMPLE_DELAY.fields.0 11262 {"bits": [8, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_CPG_PERFMON_SAMPLE_DELAY.fields.1 11267 {"bits": [0, 11], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.0 11268 {"bits": [12, 13], "name": "PERFMON_RING_MODE"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.1 11269 {"bits": [14, 15], "name": "RESERVED"}, array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.2 11270 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"} array in object:register_types.RLC_SPM_PERFMON_CNTL.fields.3 11275 {"bits": [0, 15], "name": "RING_BASE_HI"}, array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.0 11276 {"bits": [16, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_RING_BASE_HI.fields.1 11281 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.0 11282 {"bits": [8, 10], "name": "RESERVED1"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.1 11283 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.2 11284 {"bits": [16, 20], "name": "SE0_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.3 11285 {"bits": [21, 25], "name": "SE1_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.4 11286 {"bits": [26, 30], "name": "SE2_NUM_LINE"}, array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.5 11287 {"bits": [31, 31], "name": "RESERVED"} array in object:register_types.RLC_SPM_PERFMON_SEGMENT_SIZE.fields.6 11292 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, array in object:register_types.SCRATCH_UMSK.fields.0 11293 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} array in object:register_types.SCRATCH_UMSK.fields.1 11298 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.0 11299 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.1 11300 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.2 11301 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, array in object:register_types.SPI_BARYC_CNTL.fields.3 11302 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, array in object:register_types.SPI_BARYC_CNTL.fields.4 11303 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, array in object:register_types.SPI_BARYC_CNTL.fields.5 11304 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} array in object:register_types.SPI_BARYC_CNTL.fields.6 11309 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, array in object:register_types.SPI_CONFIG_CNTL.fields.0 11310 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, array in object:register_types.SPI_CONFIG_CNTL.fields.1 11311 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.2 11312 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, array in object:register_types.SPI_CONFIG_CNTL.fields.3 11313 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, array in object:register_types.SPI_CONFIG_CNTL.fields.4 11314 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"} array in object:register_types.SPI_CONFIG_CNTL.fields.5 11319 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.0 11320 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.1 11321 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.2 11322 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.3 11323 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.4 11324 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, array in object:register_types.SPI_INTERP_CONTROL_0.fields.5 11325 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} array in object:register_types.SPI_INTERP_CONTROL_0.fields.6 11330 {"bits": [0, 7], "name": "PERF_SEL"} array in object:register_types.SPI_PERFCOUNTER4_SELECT.fields.0 11335 {"bits": [0, 3], "name": "BIN0_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.0 11336 {"bits": [4, 7], "name": "BIN0_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.1 11337 {"bits": [8, 11], "name": "BIN1_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.2 11338 {"bits": [12, 15], "name": "BIN1_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.3 11339 {"bits": [16, 19], "name": "BIN2_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.4 11340 {"bits": [20, 23], "name": "BIN2_MAX"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.5 11341 {"bits": [24, 27], "name": "BIN3_MIN"}, array in object:register_types.SPI_PERFCOUNTER_BINS.fields.6 11342 {"bits": [28, 31], "name": "BIN3_MAX"} array in object:register_types.SPI_PERFCOUNTER_BINS.fields.7 11347 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.0 11348 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.1 11349 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.2 11350 {"bits": [13, 16], "name": "CYL_WRAP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.3 11351 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.4 11352 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.5 11353 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.6 11354 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.7 11355 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.8 11356 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.9 11357 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.10 11358 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_0.fields.11 11363 {"bits": [0, 5], "name": "OFFSET"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.0 11364 {"bits": [8, 9], "name": "DEFAULT_VAL"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.1 11365 {"bits": [10, 10], "name": "FLAT_SHADE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.2 11366 {"bits": [18, 18], "name": "DUP"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.3 11367 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.4 11368 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.5 11369 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.6 11370 {"bits": [24, 24], "name": "ATTR0_VALID"}, array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.7 11371 {"bits": [25, 25], "name": "ATTR1_VALID"} array in object:register_types.SPI_PS_INPUT_CNTL_20.fields.8 11376 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.0 11377 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.1 11378 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.2 11379 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.3 11380 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.4 11381 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.5 11382 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.6 11383 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.7 11384 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.8 11385 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.9 11386 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.10 11387 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.11 11388 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.12 11389 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.13 11390 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, array in object:register_types.SPI_PS_INPUT_ENA.fields.14 11391 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} array in object:register_types.SPI_PS_INPUT_ENA.fields.15 11396 {"bits": [0, 5], "name": "NUM_INTERP"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.0 11397 {"bits": [6, 6], "name": "PARAM_GEN"}, array in object:register_types.SPI_PS_IN_CONTROL.fields.1 11398 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} array in object:register_types.SPI_PS_IN_CONTROL.fields.2 11403 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.0 11404 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.1 11405 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.2 11406 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.3 11407 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.4 11408 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.5 11409 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_COL_FORMAT.fields.6 11410 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_COL_FORMAT.fields.7 11415 {"bits": [0, 5], "name": "LIMIT"} array in object:register_types.SPI_SHADER_LATE_ALLOC_VS.fields.0 11420 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.0 11421 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.1 11422 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.2 11423 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3 11424 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.4 11425 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.5 11426 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.6 11427 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.7 11428 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.8 11429 {"bits": [25, 27], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.9 11430 {"bits": [28, 28], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.10 11435 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.0 11436 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.1 11437 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.2 11438 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3 11439 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.4 11440 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.5 11441 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.6 11442 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.7 11443 {"bits": [24, 26], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.8 11444 {"bits": [27, 27], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.9 11449 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.0 11450 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.1 11451 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.2 11452 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3 11453 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.4 11454 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.5 11455 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.6 11456 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.7 11457 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.8 11458 {"bits": [26, 28], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.9 11459 {"bits": [29, 29], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.10 11464 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.0 11465 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.1 11466 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.2 11467 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3 11468 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.4 11469 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.5 11470 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.6 11471 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.7 11472 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.8 11473 {"bits": [25, 27], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.9 11474 {"bits": [28, 28], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.10 11479 {"bits": [0, 5], "name": "VGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.0 11480 {"bits": [6, 9], "name": "SGPRS"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.1 11481 {"bits": [10, 11], "name": "PRIORITY"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.2 11482 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3 11483 {"bits": [20, 20], "name": "PRIV"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.4 11484 {"bits": [21, 21], "name": "DX10_CLAMP"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.5 11485 {"bits": [22, 22], "name": "DEBUG_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.6 11486 {"bits": [23, 23], "name": "IEEE_MODE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.7 11487 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.8 11488 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.9 11489 {"bits": [27, 29], "name": "CACHE_CTL"}, array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.10 11490 {"bits": [30, 30], "name": "CDBG_USER"} array in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.11 11495 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.0 11496 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.1 11497 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.2 11498 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.3 11499 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.4 11500 {"bits": [20, 28], "name": "LDS_SIZE"} array in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.5 11505 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.0 11506 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.1 11507 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.2 11508 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3 11513 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.0 11514 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.1 11515 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.2 11516 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.3 11517 {"bits": [8, 8], "name": "TG_SIZE_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.4 11518 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5 11523 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.0 11524 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.1 11525 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.2 11526 {"bits": [7, 15], "name": "LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.3 11527 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.4 11532 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.0 11533 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.1 11534 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.2 11535 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.3 11536 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.4 11537 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5 11542 {"bits": [0, 0], "name": "SCRATCH_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.0 11543 {"bits": [1, 5], "name": "USER_SGPR"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.1 11544 {"bits": [6, 6], "name": "TRAP_PRESENT"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.2 11545 {"bits": [7, 7], "name": "OC_LDS_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.3 11546 {"bits": [8, 8], "name": "SO_BASE0_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.4 11547 {"bits": [9, 9], "name": "SO_BASE1_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.5 11548 {"bits": [10, 10], "name": "SO_BASE2_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.6 11549 {"bits": [11, 11], "name": "SO_BASE3_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.7 11550 {"bits": [12, 12], "name": "SO_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.8 11551 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9 11552 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"} array in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.10 11557 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.0 11558 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.1 11559 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.2 11560 {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"} array in object:register_types.SPI_SHADER_PGM_RSRC3_GS.fields.3 11565 {"bits": [0, 5], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.0 11566 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.1 11567 {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"} array in object:register_types.SPI_SHADER_PGM_RSRC3_HS.fields.2 11572 {"bits": [0, 15], "name": "CU_EN"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.0 11573 {"bits": [16, 21], "name": "WAVE_LIMIT"}, array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.1 11574 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"} array in object:register_types.SPI_SHADER_PGM_RSRC3_PS.fields.2 11579 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.0 11580 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.1 11581 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, array in object:register_types.SPI_SHADER_POS_FORMAT.fields.2 11582 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_POS_FORMAT.fields.3 11587 {"bits": [0, 7], "name": "MEM_BASE"} array in object:register_types.SPI_SHADER_TBA_HI_PS.fields.0 11592 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} array in object:register_types.SPI_SHADER_Z_FORMAT.fields.0 11597 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, array in object:register_types.SPI_VS_OUT_CONFIG.fields.0 11598 {"bits": [6, 6], "name": "VS_HALF_PACK"} array in object:register_types.SPI_VS_OUT_CONFIG.fields.1 11603 {"bits": [0, 0], "name": "TARGET_INST"}, array in object:register_types.SQC_CACHES.fields.0 11604 {"bits": [1, 1], "name": "TARGET_DATA"}, array in object:register_types.SQC_CACHES.fields.1 11605 {"bits": [2, 2], "name": "INVALIDATE"}, array in object:register_types.SQC_CACHES.fields.2 11606 {"bits": [3, 3], "name": "WRITEBACK"}, array in object:register_types.SQC_CACHES.fields.3 11607 {"bits": [4, 4], "name": "VOL"}, array in object:register_types.SQC_CACHES.fields.4 11608 {"bits": [16, 16], "name": "COMPLETE"} array in object:register_types.SQC_CACHES.fields.5 11613 {"bits": [0, 0], "name": "DWB"}, array in object:register_types.SQC_WRITEBACK.fields.0 11614 {"bits": [1, 1], "name": "DIRTY"} array in object:register_types.SQC_WRITEBACK.fields.1 11619 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.0 11620 {"bits": [16, 29], "name": "STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.1 11621 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, array in object:register_types.SQ_BUF_RSRC_WORD1.fields.2 11622 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} array in object:register_types.SQ_BUF_RSRC_WORD1.fields.3 11627 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.0 11628 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.1 11629 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.2 11630 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.3 11631 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.4 11632 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.5 11633 {"bits": [19, 20], "name": "ELEMENT_SIZE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.6 11634 {"bits": [21, 22], "name": "INDEX_STRIDE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.7 11635 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.8 11636 {"bits": [24, 24], "name": "ATC"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.9 11637 {"bits": [25, 25], "name": "HASH_ENABLE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.10 11638 {"bits": [26, 26], "name": "HEAP"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.11 11639 {"bits": [27, 29], "name": "MTYPE"}, array in object:register_types.SQ_BUF_RSRC_WORD3.fields.12 11640 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} array in object:register_types.SQ_BUF_RSRC_WORD3.fields.13 11645 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.0 11646 {"bits": [8, 19], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.1 11647 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.2 11648 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, array in object:register_types.SQ_IMG_RSRC_WORD1.fields.3 11649 {"bits": [30, 31], "name": "MTYPE"} array in object:register_types.SQ_IMG_RSRC_WORD1.fields.4 11654 {"bits": [0, 13], "name": "WIDTH"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.0 11655 {"bits": [14, 27], "name": "HEIGHT"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.1 11656 {"bits": [28, 30], "name": "PERF_MOD"}, array in object:register_types.SQ_IMG_RSRC_WORD2.fields.2 11657 {"bits": [31, 31], "name": "INTERLACED"} array in object:register_types.SQ_IMG_RSRC_WORD2.fields.3 11662 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.0 11663 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.1 11664 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.2 11665 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.3 11666 {"bits": [12, 15], "name": "BASE_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.4 11667 {"bits": [16, 19], "name": "LAST_LEVEL"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.5 11668 {"bits": [20, 24], "name": "TILING_INDEX"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.6 11669 {"bits": [25, 25], "name": "POW2_PAD"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.7 11670 {"bits": [26, 26], "name": "MTYPE"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.8 11671 {"bits": [27, 27], "name": "ATC"}, array in object:register_types.SQ_IMG_RSRC_WORD3.fields.9 11672 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} array in object:register_types.SQ_IMG_RSRC_WORD3.fields.10 11677 {"bits": [0, 12], "name": "DEPTH"}, array in object:register_types.SQ_IMG_RSRC_WORD4.fields.0 11678 {"bits": [13, 26], "name": "PITCH"} array in object:register_types.SQ_IMG_RSRC_WORD4.fields.1 11683 {"bits": [0, 12], "name": "BASE_ARRAY"}, array in object:register_types.SQ_IMG_RSRC_WORD5.fields.0 11684 {"bits": [13, 25], "name": "LAST_ARRAY"} array in object:register_types.SQ_IMG_RSRC_WORD5.fields.1 11689 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.0 11690 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.1 11691 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.2 11692 {"bits": [21, 21], "name": "COMPRESSION_EN"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.3 11693 {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.4 11694 {"bits": [23, 23], "name": "COLOR_TRANSFORM"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.5 11695 {"bits": [24, 27], "name": "LOST_ALPHA_BITS"}, array in object:register_types.SQ_IMG_RSRC_WORD6.fields.6 11696 {"bits": [28, 31], "name": "LOST_COLOR_BITS"} array in object:register_types.SQ_IMG_RSRC_WORD6.fields.7 11701 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.0 11702 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.1 11703 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.2 11704 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.3 11705 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.4 11706 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.5 11707 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.6 11708 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.7 11709 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.8 11710 {"bits": [21, 26], "name": "ANISO_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.9 11711 {"bits": [27, 27], "name": "TRUNC_COORD"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.10 11712 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.11 11713 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}, array in object:register_types.SQ_IMG_SAMP_WORD0.fields.12 11714 {"bits": [31, 31], "name": "COMPAT_MODE"} array in object:register_types.SQ_IMG_SAMP_WORD0.fields.13 11719 {"bits": [0, 11], "name": "MIN_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.0 11720 {"bits": [12, 23], "name": "MAX_LOD"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.1 11721 {"bits": [24, 27], "name": "PERF_MIP"}, array in object:register_types.SQ_IMG_SAMP_WORD1.fields.2 11722 {"bits": [28, 31], "name": "PERF_Z"} array in object:register_types.SQ_IMG_SAMP_WORD1.fields.3 11727 {"bits": [0, 13], "name": "LOD_BIAS"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.0 11728 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.1 11729 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.2 11730 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.3 11731 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.4 11732 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.5 11733 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.6 11734 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.7 11735 {"bits": [30, 30], "name": "FILTER_PREC_FIX"}, array in object:register_types.SQ_IMG_SAMP_WORD2.fields.8 11736 {"bits": [31, 31], "name": "ANISO_OVERRIDE"} array in object:register_types.SQ_IMG_SAMP_WORD2.fields.9 11741 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.0 11742 {"bits": [29, 29], "name": "UPGRADED_DEPTH"}, array in object:register_types.SQ_IMG_SAMP_WORD3.fields.1 11743 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} array in object:register_types.SQ_IMG_SAMP_WORD3.fields.2 11748 {"bits": [0, 8], "name": "PERF_SEL"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.0 11749 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.1 11750 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.2 11751 {"bits": [20, 23], "name": "SPM_MODE"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.3 11752 {"bits": [24, 27], "name": "SIMD_MASK"}, array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.4 11753 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.SQ_PERFCOUNTER0_SELECT.fields.5 11758 {"bits": [0, 0], "name": "PS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.0 11759 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1 11760 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2 11761 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3 11762 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4 11763 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5 11764 {"bits": [6, 6], "name": "CS_EN"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.6 11765 {"bits": [8, 12], "name": "CNTR_RATE"}, array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.7 11766 {"bits": [13, 13], "name": "DISABLE_FLUSH"} array in object:register_types.SQ_PERFCOUNTER_CTRL.fields.8 11771 {"bits": [0, 0], "name": "FORCE_EN"} array in object:register_types.SQ_PERFCOUNTER_CTRL2.fields.0 11776 {"bits": [0, 15], "name": "SH0_MASK"}, array in object:register_types.SQ_PERFCOUNTER_MASK.fields.0 11777 {"bits": [16, 31], "name": "SH1_MASK"} array in object:register_types.SQ_PERFCOUNTER_MASK.fields.1 11782 {"bits": [0, 3], "name": "ADDR_HI"} array in object:register_types.SQ_THREAD_TRACE_BASE2.fields.0 11787 {"bits": [31, 31], "name": "RESET_BUFFER"} array in object:register_types.SQ_THREAD_TRACE_CTRL.fields.0 11792 {"bits": [0, 2], "name": "HIWATER"} array in object:register_types.SQ_THREAD_TRACE_HIWATER.fields.0 11797 {"bits": [0, 4], "name": "CU_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.0 11798 {"bits": [5, 5], "name": "SH_SEL"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.1 11799 {"bits": [7, 7], "name": "REG_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.2 11800 {"bits": [8, 11], "name": "SIMD_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.3 11801 {"bits": [12, 13], "name": "VM_ID_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.4 11802 {"bits": [14, 14], "name": "SPI_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.5 11803 {"bits": [15, 15], "name": "SQ_STALL_EN"}, array in object:register_types.SQ_THREAD_TRACE_MASK.fields.6 11804 {"bits": [16, 31], "name": "RANDOM_SEED"} array in object:register_types.SQ_THREAD_TRACE_MASK.fields.7 11809 {"bits": [0, 2], "name": "MASK_PS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.0 11810 {"bits": [3, 5], "name": "MASK_VS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.1 11811 {"bits": [6, 8], "name": "MASK_GS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.2 11812 {"bits": [9, 11], "name": "MASK_ES"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.3 11813 {"bits": [12, 14], "name": "MASK_HS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.4 11814 {"bits": [15, 17], "name": "MASK_LS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.5 11815 {"bits": [18, 20], "name": "MASK_CS"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.6 11816 {"bits": [21, 22], "name": "MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.7 11817 {"bits": [23, 24], "name": "CAPTURE_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.8 11818 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.9 11819 {"bits": [26, 26], "name": "PRIV"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.10 11820 {"bits": [27, 28], "name": "ISSUE_MASK"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.11 11821 {"bits": [29, 29], "name": "TEST_MODE"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.12 11822 {"bits": [30, 30], "name": "INTERRUPT_EN"}, array in object:register_types.SQ_THREAD_TRACE_MODE.fields.13 11823 {"bits": [31, 31], "name": "WRAP"} array in object:register_types.SQ_THREAD_TRACE_MODE.fields.14 11828 {"bits": [0, 21], "name": "SIZE"} array in object:register_types.SQ_THREAD_TRACE_SIZE.fields.0 11833 {"bits": [0, 9], "name": "FINISH_PENDING"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.0 11834 {"bits": [16, 25], "name": "FINISH_DONE"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.1 11835 {"bits": [29, 29], "name": "NEW_BUF"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.2 11836 {"bits": [30, 30], "name": "BUSY"}, array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.3 11837 {"bits": [31, 31], "name": "FULL"} array in object:register_types.SQ_THREAD_TRACE_STATUS.fields.4 11842 {"bits": [0, 15], "name": "TOKEN_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0 11843 {"bits": [16, 23], "name": "REG_MASK"}, array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.1 11844 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} array in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.2 11849 {"bits": [0, 29], "name": "WPTR"}, array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.0 11850 {"bits": [30, 31], "name": "READ_OFFSET"} array in object:register_types.SQ_THREAD_TRACE_WPTR.fields.1 11855 {"bits": [0, 5], "name": "VGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.0 11856 {"bits": [8, 13], "name": "VGPR_SIZE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.1 11857 {"bits": [16, 21], "name": "SGPR_BASE"}, array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.2 11858 {"bits": [24, 27], "name": "SGPR_SIZE"} array in object:register_types.SQ_WAVE_GPR_ALLOC.fields.3 11863 {"bits": [0, 3], "name": "WAVE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.0 11864 {"bits": [4, 5], "name": "SIMD_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.1 11865 {"bits": [6, 7], "name": "PIPE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.2 11866 {"bits": [8, 11], "name": "CU_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.3 11867 {"bits": [12, 12], "name": "SH_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.4 11868 {"bits": [13, 14], "name": "SE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.5 11869 {"bits": [16, 19], "name": "TG_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.6 11870 {"bits": [20, 23], "name": "VM_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.7 11871 {"bits": [24, 26], "name": "QUEUE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.8 11872 {"bits": [27, 29], "name": "STATE_ID"}, array in object:register_types.SQ_WAVE_HW_ID.fields.9 11873 {"bits": [30, 31], "name": "ME_ID"} array in object:register_types.SQ_WAVE_HW_ID.fields.10 11878 {"bits": [0, 2], "name": "IBUF_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.0 11879 {"bits": [3, 3], "name": "PC_INVALID"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.1 11880 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.2 11881 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.3 11882 {"bits": [8, 9], "name": "IBUF_RPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.4 11883 {"bits": [10, 11], "name": "IBUF_WPTR"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.5 11884 {"bits": [16, 19], "name": "INST_STR_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.6 11885 {"bits": [20, 23], "name": "MISC_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.7 11886 {"bits": [24, 25], "name": "ECC_ST"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.8 11887 {"bits": [26, 26], "name": "IS_HYB"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.9 11888 {"bits": [27, 28], "name": "HYB_CNT"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.10 11889 {"bits": [29, 29], "name": "KILL"}, array in object:register_types.SQ_WAVE_IB_DBG0.fields.11 11890 {"bits": [30, 30], "name": "NEED_KILL_IFETCH"} array in object:register_types.SQ_WAVE_IB_DBG0.fields.12 11895 {"bits": [0, 0], "name": "IXNACK"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.0 11896 {"bits": [1, 1], "name": "XNACK"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.1 11897 {"bits": [2, 2], "name": "TA_NEED_RESET"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.2 11898 {"bits": [4, 7], "name": "XCNT"}, array in object:register_types.SQ_WAVE_IB_DBG1.fields.3 11899 {"bits": [8, 11], "name": "QCNT"} array in object:register_types.SQ_WAVE_IB_DBG1.fields.4 11904 {"bits": [0, 3], "name": "VM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.0 11905 {"bits": [4, 6], "name": "EXP_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.1 11906 {"bits": [8, 11], "name": "LGKM_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.2 11907 {"bits": [12, 14], "name": "VALU_CNT"}, array in object:register_types.SQ_WAVE_IB_STS.fields.3 11908 {"bits": [15, 15], "name": "FIRST_REPLAY"}, array in object:register_types.SQ_WAVE_IB_STS.fields.4 11909 {"bits": [16, 19], "name": "RCNT"} array in object:register_types.SQ_WAVE_IB_STS.fields.5 11914 {"bits": [0, 7], "name": "LDS_BASE"}, array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.0 11915 {"bits": [12, 20], "name": "LDS_SIZE"} array in object:register_types.SQ_WAVE_LDS_ALLOC.fields.1 11920 {"bits": [0, 3], "name": "FP_ROUND"}, array in object:register_types.SQ_WAVE_MODE.fields.0 11921 {"bits": [4, 7], "name": "FP_DENORM"}, array in object:register_types.SQ_WAVE_MODE.fields.1 11922 {"bits": [8, 8], "name": "DX10_CLAMP"}, array in object:register_types.SQ_WAVE_MODE.fields.2 11923 {"bits": [9, 9], "name": "IEEE"}, array in object:register_types.SQ_WAVE_MODE.fields.3 11924 {"bits": [10, 10], "name": "LOD_CLAMPED"}, array in object:register_types.SQ_WAVE_MODE.fields.4 11925 {"bits": [11, 11], "name": "DEBUG_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.5 11926 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.6 11927 {"bits": [27, 27], "name": "GPR_IDX_EN"}, array in object:register_types.SQ_WAVE_MODE.fields.7 11928 {"bits": [28, 28], "name": "VSKIP"}, array in object:register_types.SQ_WAVE_MODE.fields.8 11929 {"bits": [29, 31], "name": "CSP"} array in object:register_types.SQ_WAVE_MODE.fields.9 11934 {"bits": [0, 15], "name": "PC_HI"} array in object:register_types.SQ_WAVE_PC_HI.fields.0 11939 {"bits": [0, 0], "name": "SCC"}, array in object:register_types.SQ_WAVE_STATUS.fields.0 11940 {"bits": [1, 2], "name": "SPI_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.1 11941 {"bits": [3, 4], "name": "USER_PRIO"}, array in object:register_types.SQ_WAVE_STATUS.fields.2 11942 {"bits": [5, 5], "name": "PRIV"}, array in object:register_types.SQ_WAVE_STATUS.fields.3 11943 {"bits": [6, 6], "name": "TRAP_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.4 11944 {"bits": [7, 7], "name": "TTRACE_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.5 11945 {"bits": [8, 8], "name": "EXPORT_RDY"}, array in object:register_types.SQ_WAVE_STATUS.fields.6 11946 {"bits": [9, 9], "name": "EXECZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.7 11947 {"bits": [10, 10], "name": "VCCZ"}, array in object:register_types.SQ_WAVE_STATUS.fields.8 11948 {"bits": [11, 11], "name": "IN_TG"}, array in object:register_types.SQ_WAVE_STATUS.fields.9 11949 {"bits": [12, 12], "name": "IN_BARRIER"}, array in object:register_types.SQ_WAVE_STATUS.fields.10 11950 {"bits": [13, 13], "name": "HALT"}, array in object:register_types.SQ_WAVE_STATUS.fields.11 11951 {"bits": [14, 14], "name": "TRAP"}, array in object:register_types.SQ_WAVE_STATUS.fields.12 11952 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.13 11953 {"bits": [16, 16], "name": "VALID"}, array in object:register_types.SQ_WAVE_STATUS.fields.14 11954 {"bits": [17, 17], "name": "ECC_ERR"}, array in object:register_types.SQ_WAVE_STATUS.fields.15 11955 {"bits": [18, 18], "name": "SKIP_EXPORT"}, array in object:register_types.SQ_WAVE_STATUS.fields.16 11956 {"bits": [19, 19], "name": "PERF_EN"}, array in object:register_types.SQ_WAVE_STATUS.fields.17 11957 {"bits": [20, 20], "name": "COND_DBG_USER"}, array in object:register_types.SQ_WAVE_STATUS.fields.18 11958 {"bits": [21, 21], "name": "COND_DBG_SYS"}, array in object:register_types.SQ_WAVE_STATUS.fields.19 11959 {"bits": [22, 22], "name": "ALLOW_REPLAY"}, array in object:register_types.SQ_WAVE_STATUS.fields.20 11960 {"bits": [23, 23], "name": "INST_ATC"}, array in object:register_types.SQ_WAVE_STATUS.fields.21 11961 {"bits": [27, 27], "name": "MUST_EXPORT"} array in object:register_types.SQ_WAVE_STATUS.fields.22 11966 {"bits": [0, 7], "name": "ADDR_HI"} array in object:register_types.SQ_WAVE_TBA_HI.fields.0 11971 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.0 11972 {"bits": [10, 10], "name": "SAVECTX"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.1 11973 {"bits": [16, 21], "name": "EXCP_CYCLE"}, array in object:register_types.SQ_WAVE_TRAPSTS.fields.2 11974 {"bits": [29, 31], "name": "DP_RATE"} array in object:register_types.SQ_WAVE_TRAPSTS.fields.3 11979 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.0 11980 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.1 11981 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.2 11982 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.3 11983 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.4 11984 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.5 11985 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.6 11986 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.7 11987 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.8 11988 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.9 11989 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.10 11990 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.11 11991 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.12 11992 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.13 11993 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.14 11994 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"}, array in object:register_types.SX_BLEND_OPT_CONTROL.fields.15 11995 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"} array in object:register_types.SX_BLEND_OPT_CONTROL.fields.16 12000 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.0 12001 {"bits": [4, 7], "name": "MRT1_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.1 12002 {"bits": [8, 11], "name": "MRT2_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.2 12003 {"bits": [12, 15], "name": "MRT3_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.3 12004 {"bits": [16, 19], "name": "MRT4_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.4 12005 {"bits": [20, 23], "name": "MRT5_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.5 12006 {"bits": [24, 27], "name": "MRT6_EPSILON"}, array in object:register_types.SX_BLEND_OPT_EPSILON.fields.6 12007 {"bits": [28, 31], "name": "MRT7_EPSILON"} array in object:register_types.SX_BLEND_OPT_EPSILON.fields.7 12012 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.0 12013 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.1 12014 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.2 12015 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.3 12016 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, array in object:register_types.SX_MRT0_BLEND_OPT.fields.4 12017 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} array in object:register_types.SX_MRT0_BLEND_OPT.fields.5 12022 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"}, array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.0 12023 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"}, array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.1 12024 {"bits": [20, 23], "name": "CNTR_MODE"} array in object:register_types.SX_PERFCOUNTER0_SELECT.fields.2 12029 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"}, array in object:register_types.SX_PERFCOUNTER0_SELECT1.fields.0 12030 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"} array in object:register_types.SX_PERFCOUNTER0_SELECT1.fields.1 12035 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.0 12036 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.1 12037 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.2 12038 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.3 12039 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.4 12040 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.5 12041 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, array in object:register_types.SX_PS_DOWNCONVERT.fields.6 12042 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} array in object:register_types.SX_PS_DOWNCONVERT.fields.7 12047 {"bits": [0, 7], "name": "ADDRESS"} array in object:register_types.TA_BC_BASE_ADDR_HI.fields.0 12052 {"bits": [0, 9], "name": "PERF_SEL2"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.0 12053 {"bits": [10, 19], "name": "PERF_SEL3"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.1 12054 {"bits": [24, 27], "name": "PERF_MODE2"}, array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.2 12055 {"bits": [28, 31], "name": "PERF_MODE3"} array in object:register_types.TCC_PERFCOUNTER0_SELECT1.fields.3 12060 {"bits": [0, 9], "name": "PERF_SEL"}, array in object:register_types.TCC_PERFCOUNTER2_SELECT.fields.0 12061 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TCC_PERFCOUNTER2_SELECT.fields.1 12062 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TCC_PERFCOUNTER2_SELECT.fields.2 12067 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.0 12068 {"bits": [10, 17], "name": "PERF_SEL1"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.1 12069 {"bits": [20, 23], "name": "CNTR_MODE"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.2 12070 {"bits": [24, 27], "name": "PERF_MODE1"}, array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.3 12071 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.TD_PERFCOUNTER0_SELECT.fields.4 12076 {"bits": [0, 7], "name": "PERF_SEL2"}, array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.0 12077 {"bits": [10, 17], "name": "PERF_SEL3"}, array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.1 12078 {"bits": [24, 27], "name": "PERF_MODE3"}, array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.2 12079 {"bits": [28, 31], "name": "PERF_MODE2"} array in object:register_types.TD_PERFCOUNTER0_SELECT1.fields.3 12084 {"bits": [0, 7], "name": "BASE_ADDR"} array in object:register_types.VGT_DMA_BASE_HI.fields.0 12089 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.0 12090 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.1 12091 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.2 12092 {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.3 12093 {"bits": [9, 9], "name": "NOT_EOP"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.4 12094 {"bits": [10, 10], "name": "REQ_PATH"}, array in object:register_types.VGT_DMA_INDEX_TYPE.fields.5 12095 {"bits": [11, 12], "name": "MTYPE"} array in object:register_types.VGT_DMA_INDEX_TYPE.fields.6 12100 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.0 12101 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.1 12102 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.2 12103 {"bits": [5, 5], "name": "NOT_EOP"}, array in object:register_types.VGT_DRAW_INITIATOR.fields.3 12104 {"bits": [6, 6], "name": "USE_OPAQUE"} array in object:register_types.VGT_DRAW_INITIATOR.fields.4 12109 {"bits": [0, 14], "name": "ITEMSIZE"} array in object:register_types.VGT_ESGS_RING_ITEMSIZE.fields.0 12114 {"bits": [0, 10], "name": "ES_PER_GS"} array in object:register_types.VGT_ES_PER_GS.fields.0 12119 {"bits": [0, 27], "name": "ADDRESS_LOW"} array in object:register_types.VGT_EVENT_ADDRESS_REG.fields.0 12124 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.0 12125 {"bits": [18, 26], "name": "ADDRESS_HI"}, array in object:register_types.VGT_EVENT_INITIATOR.fields.1 12126 {"bits": [27, 27], "name": "EXTENDED_EVENT"} array in object:register_types.VGT_EVENT_INITIATOR.fields.2 12131 {"bits": [0, 3], "name": "DECR"} array in object:register_types.VGT_GROUP_DECR.fields.0 12136 {"bits": [0, 3], "name": "FIRST_DECR"} array in object:register_types.VGT_GROUP_FIRST_DECR.fields.0 12141 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0 12142 {"bits": [14, 14], "name": "RETAIN_ORDER"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.1 12143 {"bits": [15, 15], "name": "RETAIN_QUADS"}, array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.2 12144 {"bits": [16, 18], "name": "PRIM_ORDER"} array in object:register_types.VGT_GROUP_PRIM_TYPE.fields.3 12149 {"bits": [0, 0], "name": "COMP_X_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.0 12150 {"bits": [1, 1], "name": "COMP_Y_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.1 12151 {"bits": [2, 2], "name": "COMP_Z_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.2 12152 {"bits": [3, 3], "name": "COMP_W_EN"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.3 12153 {"bits": [8, 15], "name": "STRIDE"}, array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.4 12154 {"bits": [16, 23], "name": "SHIFT"} array in object:register_types.VGT_GROUP_VECT_0_CNTL.fields.5 12159 {"bits": [0, 3], "name": "X_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.0 12160 {"bits": [4, 7], "name": "X_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.1 12161 {"bits": [8, 11], "name": "Y_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.2 12162 {"bits": [12, 15], "name": "Y_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.3 12163 {"bits": [16, 19], "name": "Z_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.4 12164 {"bits": [20, 23], "name": "Z_OFFSET"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.5 12165 {"bits": [24, 27], "name": "W_CONV"}, array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.6 12166 {"bits": [28, 31], "name": "W_OFFSET"} array in object:register_types.VGT_GROUP_VECT_0_FMT_CNTL.fields.7 12171 {"bits": [0, 14], "name": "OFFSET"} array in object:register_types.VGT_GSVS_RING_OFFSET_1.fields.0 12176 {"bits": [0, 0], "name": "ENABLE"}, array in object:register_types.VGT_GS_INSTANCE_CNT.fields.0 12177 {"bits": [2, 8], "name": "CNT"} array in object:register_types.VGT_GS_INSTANCE_CNT.fields.1 12182 {"bits": [0, 10], "name": "MAX_VERT_OUT"} array in object:register_types.VGT_GS_MAX_VERT_OUT.fields.0 12187 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, array in object:register_types.VGT_GS_MODE.fields.0 12188 {"bits": [3, 3], "name": "RESERVED_0"}, array in object:register_types.VGT_GS_MODE.fields.1 12189 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, array in object:register_types.VGT_GS_MODE.fields.2 12190 {"bits": [6, 10], "name": "RESERVED_1"}, array in object:register_types.VGT_GS_MODE.fields.3 12191 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, array in object:register_types.VGT_GS_MODE.fields.4 12192 {"bits": [12, 12], "name": "RESERVED_2"}, array in object:register_types.VGT_GS_MODE.fields.5 12193 {"bits": [13, 13], "name": "ES_PASSTHRU"}, array in object:register_types.VGT_GS_MODE.fields.6 12194 {"bits": [14, 14], "name": "RESERVED_3"}, array in object:register_types.VGT_GS_MODE.fields.7 12195 {"bits": [15, 15], "name": "RESERVED_4"}, array in object:register_types.VGT_GS_MODE.fields.8 12196 {"bits": [16, 16], "name": "RESERVED_5"}, array in object:register_types.VGT_GS_MODE.fields.9 12197 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, array in object:register_types.VGT_GS_MODE.fields.10 12198 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, array in object:register_types.VGT_GS_MODE.fields.11 12199 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.12 12200 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, array in object:register_types.VGT_GS_MODE.fields.13 12201 {"bits": [21, 22], "name": "ONCHIP"} array in object:register_types.VGT_GS_MODE.fields.14 12206 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"}, array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.0 12207 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"} array in object:register_types.VGT_GS_ONCHIP_CNTL.fields.1 12212 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0 12213 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1 12214 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2 12215 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3 12216 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} array in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.4 12221 {"bits": [0, 10], "name": "GS_PER_ES"} array in object:register_types.VGT_GS_PER_ES.fields.0 12226 {"bits": [0, 3], "name": "GS_PER_VS"} array in object:register_types.VGT_GS_PER_VS.fields.0 12231 {"bits": [0, 1], "name": "TESS_MODE"} array in object:register_types.VGT_HOS_CNTL.fields.0 12236 {"bits": [0, 7], "name": "REUSE_DEPTH"} array in object:register_types.VGT_HOS_REUSE_DEPTH.fields.0 12241 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"}, array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.0 12242 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP array in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1 12247 {"bits": [0, 7], "name": "NUM_PATCHES"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.0 12248 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, array in object:register_types.VGT_LS_HS_CONFIG.fields.1 12249 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} array in object:register_types.VGT_LS_HS_CONFIG.fields.2 12254 {"bits": [0, 0], "name": "RESET_EN"} array in object:register_types.VGT_MULTI_PRIM_IB_RESET_EN.fields.0 12259 {"bits": [0, 2], "name": "PATH_SELECT"} array in object:register_types.VGT_OUTPUT_PATH_CNTL.fields.0 12264 {"bits": [0, 6], "name": "DEALLOC_DIST"} array in object:register_types.VGT_OUT_DEALLOC_CNTL.fields.0 12269 {"bits": [0, 7], "name": "PERF_SEL"}, array in object:register_types.VGT_PERFCOUNTER2_SELECT.fields.0 12270 {"bits": [28, 31], "name": "PERF_MODE"} array in object:register_types.VGT_PERFCOUNTER2_SELECT.fields.1 12275 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} array in object:register_types.VGT_PERFCOUNTER_SEID_MASK.fields.0 12280 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, array in object:register_types.VGT_PRIMITIVEID_EN.fields.0 12281 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"} array in object:register_types.VGT_PRIMITIVEID_EN.fields.1 12286 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} array in object:register_types.VGT_PRIMITIVE_TYPE.fields.0 12291 {"bits": [0, 0], "name": "REUSE_OFF"} array in object:register_types.VGT_REUSE_OFF.fields.0 12296 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.0 12297 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.1 12298 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.2 12299 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.3 12300 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.4 12301 {"bits": [8, 8], "name": "DYNAMIC_HS"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.5 12302 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.6 12303 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.7 12304 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"}, array in object:register_types.VGT_SHADER_STAGES_EN.fields.8 12305 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"} array in object:register_types.VGT_SHADER_STAGES_EN.fields.9 12310 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.0 12311 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.1 12312 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.2 12313 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} array in object:register_types.VGT_STRMOUT_BUFFER_CONFIG.fields.3 12318 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.0 12319 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.1 12320 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.2 12321 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.3 12322 {"bits": [4, 6], "name": "RAST_STREAM"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.4 12323 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, array in object:register_types.VGT_STRMOUT_CONFIG.fields.5 12324 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} array in object:register_types.VGT_STRMOUT_CONFIG.fields.6 12329 {"bits": [0, 8], "name": "VERTEX_STRIDE"} array in object:register_types.VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE.fields.0 12334 {"bits": [0, 9], "name": "STRIDE"} array in object:register_types.VGT_STRMOUT_VTX_STRIDE_0.fields.0 12339 {"bits": [0, 7], "name": "ACCUM_ISOLINE"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.0 12340 {"bits": [8, 15], "name": "ACCUM_TRI"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.1 12341 {"bits": [16, 23], "name": "ACCUM_QUAD"}, array in object:register_types.VGT_TESS_DISTRIBUTION.fields.2 12342 {"bits": [24, 31], "name": "DONUT_SPLIT"} array in object:register_types.VGT_TESS_DISTRIBUTION.fields.3 12347 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, array in object:register_types.VGT_TF_PARAM.fields.0 12348 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, array in object:register_types.VGT_TF_PARAM.fields.1 12349 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, array in object:register_types.VGT_TF_PARAM.fields.2 12350 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, array in object:register_types.VGT_TF_PARAM.fields.3 12351 {"bits": [9, 9], "name": "DEPRECATED"}, array in object:register_types.VGT_TF_PARAM.fields.4 12352 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, array in object:register_types.VGT_TF_PARAM.fields.5 12353 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, array in object:register_types.VGT_TF_PARAM.fields.6 12354 {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, array in object:register_types.VGT_TF_PARAM.fields.7 12355 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, array in object:register_types.VGT_TF_PARAM.fields.8 12356 {"bits": [19, 20], "name": "MTYPE"} array in object:register_types.VGT_TF_PARAM.fields.9 12361 {"bits": [0, 15], "name": "SIZE"} array in object:register_types.VGT_TF_RING_SIZE.fields.0 12366 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} array in object:register_types.VGT_VERTEX_REUSE_BLOCK_CNTL.fields.0 12371 {"bits": [0, 0], "name": "VTX_CNT_EN"} array in object:register_types.VGT_VTX_CNT_EN.fields.0 [all...]
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A D	gfx6_multisample_state.c	36 uint8_t bits; local in function:gfx6_get_sample_position 43 bits = brw_multisample_positions_1x_2x >> (8 * index); 46 bits = brw_multisample_positions_4x >> (8 * index); 49 bits = brw_multisample_positions_8x[index >> 2] >> (8 * (index & 3)); 52 bits = brw_multisample_positions_16x[index >> 2] >> (8 * (index & 3)); 59 result[0] = ((bits >> 4) & 0xf) / 16.0f; 60 result[1] = (bits & 0xf) / 16.0f;
/xsrc/external/mit/xf86-video-siliconmotion/dist/src/
H A D	smi_501.h	41 #define bits(lo, hi) hi + 1 - lo macro 69 int32_t address : bits( 0, 27); 70 int32_t u0 : bits(28, 29); 71 int32_t idle : bits(30, 30); 72 int32_t start : bits(31, 31); 129 int32_t engine : bits( 0, 0); 130 int32_t cmdfifo : bits( 1, 1); 131 int32_t setup : bits( 2, 2); 132 int32_t u0 : bits( 3, 10); 133 int32_t pvsync : bits(1 [all...]
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A D	anv_util.c	60 anv_dump_pipe_bits(enum anv_pipe_bits bits) argument 62 if (bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) 64 if (bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT) 66 if (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT) 68 if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT) 70 if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT) 72 if (bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT) 74 if (bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT) 76 if (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT) 78 if (bits [all...]
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/xaa/
H A D	xaaTEGlyph.c	238 reversing the bits and sending them to the screen 272 CARD32 bits; local in function:EXPNAME 281 bits = SHIFT_R(glyphs[0][line++],skipleft); 283 WRITE_BITS3(bits); 285 WRITE_BITS2(bits); 287 WRITE_BITS1(bits); 448 CARD32 bits; local in function:EXPNAME 459 bits = SHIFT_R(glyphs[0][line++],skipleft); 461 WRITE_BITS3(bits); 463 WRITE_BITS2(bits); 557 CARD32 bits = (*glyphp)[line]; local in function:DrawTETextScanlineGeneric 604 unsigned int bits; local in function:DrawTETextScanlineWidth6 646 unsigned int bits; local in function:DrawTETextScanlineWidth7 717 unsigned int bits; local in function:DrawTETextScanlineWidth8 748 unsigned int bits; local in function:DrawTETextScanlineWidth9 824 unsigned int bits; local in function:DrawTETextScanlineWidth10 871 unsigned int bits; local in function:DrawTETextScanlineWidth12 906 unsigned int bits; local in function:DrawTETextScanlineWidth14 960 unsigned int bits; local in function:DrawTETextScanlineWidth16 995 unsigned int bits; local in function:DrawTETextScanlineWidth18 1055 unsigned int bits; local in function:DrawTETextScanlineWidth24 [all...]
/xsrc/external/mit/MesaLib/src/panfrost/bifrost/
H A D	bifrost_gen_disasm.c	3 #define _BITS(bits, pos, width) (((bits) >> (pos)) & ((1 << (width)) - 1)) 5 bi_disasm_fma_arshift_i32(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_regs *next_regs, unsigned staging_register, unsigned branch_offset, struct bi_constants *consts, bool last) argument 11 const char *lane2 = lane2_table[_BITS(bits, 9, 2)]; 17 dump_src(fp, _BITS(bits, 0, 3), *srcs, branch_offset, consts, true); 18 if (!(0xfb & (1 << _BITS(bits, 0, 3)))) fputs("(INVALID)", fp); 20 dump_src(fp, _BITS(bits, 3, 3), *srcs, branch_offset, consts, true); 21 if (!(0x8 & (1 << _BITS(bits, 3, 3)))) fputs("(INVALID)", fp); 23 dump_src(fp, _BITS(bits, 6, 3), *srcs, branch_offset, consts, true); 28 bi_disasm_fma_arshift_v2i16_0(FILE *fp, unsigned bits, struc argument 49 bi_disasm_fma_arshift_v2i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 70 bi_disasm_fma_arshift_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 91 bi_disasm_fma_arshift_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 112 bi_disasm_fma_arshift_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 149 bi_disasm_fma_atom_c_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 173 bi_disasm_fma_atom_c_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 197 bi_disasm_fma_atom_c1_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 218 bi_disasm_fma_atom_c1_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 239 bi_disasm_fma_atom_c1_return_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 260 bi_disasm_fma_atom_c1_return_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 281 bi_disasm_fma_atom_c_return_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 305 bi_disasm_fma_atom_c_return_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 329 bi_disasm_fma_atom_post_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 350 bi_disasm_fma_atom_post_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 371 bi_disasm_fma_atom_pre_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 394 bi_disasm_fma_bitrev_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 405 bi_disasm_fma_clz_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 423 bi_disasm_fma_clz_v2u16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 448 bi_disasm_fma_clz_v4u8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 466 bi_disasm_fma_csel_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 489 bi_disasm_fma_csel_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 512 bi_disasm_fma_csel_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 535 bi_disasm_fma_csel_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 558 bi_disasm_fma_csel_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 581 bi_disasm_fma_csel_v2i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 604 bi_disasm_fma_csel_v2s16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 627 bi_disasm_fma_csel_v2u16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 650 bi_disasm_fma_cubeface1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 681 bi_disasm_fma_dtsel_imm(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 699 bi_disasm_fma_f16_to_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 717 bi_disasm_fma_fadd_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 783 bi_disasm_fma_fadd_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 856 bi_disasm_fma_fadd_lscale_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 898 bi_disasm_fma_fcmp_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 964 bi_disasm_fma_fcmp_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1038 bi_disasm_fma_flshift_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1068 bi_disasm_fma_fma_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1146 bi_disasm_fma_fma_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1214 bi_disasm_fma_fma_rscale_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1271 bi_disasm_fma_fma_rscale_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1328 bi_disasm_fma_fmul_cslice(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1363 bi_disasm_fma_fmul_slice_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1377 bi_disasm_fma_frexpe_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1414 bi_disasm_fma_frexpe_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1447 bi_disasm_fma_frexpe_v2f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1484 bi_disasm_fma_frexpe_v2f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1517 bi_disasm_fma_frexpm_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1559 bi_disasm_fma_frexpm_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1601 bi_disasm_fma_frexpm_v2f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1643 bi_disasm_fma_frexpm_v2f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1685 bi_disasm_fma_fround_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1722 bi_disasm_fma_fround_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1759 bi_disasm_fma_fround_v2f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1796 bi_disasm_fma_fround_v2f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1833 bi_disasm_fma_frshift_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1863 bi_disasm_fma_iaddc_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1879 bi_disasm_fma_idp_v4i8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1907 bi_disasm_fma_imul_i32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1931 bi_disasm_fma_imul_i32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1955 bi_disasm_fma_imul_i32_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 1979 bi_disasm_fma_imul_v2i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2007 bi_disasm_fma_imul_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2031 bi_disasm_fma_imul_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2055 bi_disasm_fma_imuld(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2076 bi_disasm_fma_isubb_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2092 bi_disasm_fma_jump_ex(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2122 bi_disasm_fma_lrot_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2159 bi_disasm_fma_lshift_and_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2196 bi_disasm_fma_lshift_and_v2i16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2231 bi_disasm_fma_lshift_and_v2i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2266 bi_disasm_fma_lshift_and_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2301 bi_disasm_fma_lshift_and_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2336 bi_disasm_fma_lshift_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2373 bi_disasm_fma_lshift_or_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2410 bi_disasm_fma_lshift_or_v2i16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2445 bi_disasm_fma_lshift_or_v2i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2480 bi_disasm_fma_lshift_or_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2515 bi_disasm_fma_lshift_or_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2550 bi_disasm_fma_lshift_xor_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2580 bi_disasm_fma_lshift_xor_v2i16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2608 bi_disasm_fma_lshift_xor_v2i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2636 bi_disasm_fma_lshift_xor_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2664 bi_disasm_fma_lshift_xor_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2692 bi_disasm_fma_mkvec_v2i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2720 bi_disasm_fma_mkvec_v4i8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2766 bi_disasm_fma_mov_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2777 bi_disasm_fma_nop(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2785 bi_disasm_fma_popcount_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2796 bi_disasm_fma_quiet_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2807 bi_disasm_fma_quiet_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2825 bi_disasm_fma_rrot_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2862 bi_disasm_fma_rshift_and_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2899 bi_disasm_fma_rshift_and_v2i16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2934 bi_disasm_fma_rshift_and_v2i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 2969 bi_disasm_fma_rshift_and_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3004 bi_disasm_fma_rshift_and_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3039 bi_disasm_fma_rshift_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3076 bi_disasm_fma_rshift_or_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3113 bi_disasm_fma_rshift_or_v2i16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3148 bi_disasm_fma_rshift_or_v2i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3183 bi_disasm_fma_rshift_or_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3218 bi_disasm_fma_rshift_or_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3253 bi_disasm_fma_rshift_xor_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3283 bi_disasm_fma_rshift_xor_v2i16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3311 bi_disasm_fma_rshift_xor_v2i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3339 bi_disasm_fma_rshift_xor_v4i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3367 bi_disasm_fma_rshift_xor_v4i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3395 bi_disasm_fma_s16_to_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3413 bi_disasm_fma_s8_to_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3431 bi_disasm_fma_seg_add(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3456 bi_disasm_fma_seg_sub(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3481 bi_disasm_fma_shaddxl_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3496 bi_disasm_fma_shaddxl_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3518 bi_disasm_fma_shaddxl_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3540 bi_disasm_fma_u16_to_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3558 bi_disasm_fma_u8_to_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3576 bi_disasm_fma_v2f32_to_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3624 bi_disasm_fma_vn_asst1_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3661 bi_disasm_fma_vn_asst1_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3686 bi_disasm_add_acmpstore_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3706 bi_disasm_add_acmpstore_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3726 bi_disasm_add_acmpxchg_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3746 bi_disasm_add_acmpxchg_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3766 bi_disasm_add_atest(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3788 bi_disasm_add_atom_cx(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3803 bi_disasm_add_axchg_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3823 bi_disasm_add_axchg_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3843 bi_disasm_add_barrier(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3851 bi_disasm_add_blend(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3868 bi_disasm_add_branch_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3908 bi_disasm_add_branch_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3948 bi_disasm_add_branch_i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 3988 bi_disasm_add_branch_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4028 bi_disasm_add_branch_s16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4068 bi_disasm_add_branch_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4108 bi_disasm_add_branch_u16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4148 bi_disasm_add_branch_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4188 bi_disasm_add_branchc_i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4213 bi_disasm_add_branchc_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4233 bi_disasm_add_branchz_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4256 bi_disasm_add_branchz_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4274 bi_disasm_add_branchz_i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4297 bi_disasm_add_branchz_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4315 bi_disasm_add_branchz_s16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4338 bi_disasm_add_branchz_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4356 bi_disasm_add_branchz_u16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4379 bi_disasm_add_branchz_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4397 bi_disasm_add_branch_diverg(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4408 bi_disasm_add_branch_lowbits_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4421 bi_disasm_add_branch_no_diverg(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4432 bi_disasm_add_clper_v6_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4445 bi_disasm_add_clper_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4479 bi_disasm_add_cubeface2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4489 bi_disasm_add_cube_ssel(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4513 bi_disasm_add_cube_tsel(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4537 bi_disasm_add_discard_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4564 bi_disasm_add_doorbell(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4574 bi_disasm_add_eureka(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4584 bi_disasm_add_f16_to_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4601 bi_disasm_add_f16_to_s32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4623 bi_disasm_add_f16_to_s32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4645 bi_disasm_add_f16_to_u32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4667 bi_disasm_add_f16_to_u32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4689 bi_disasm_add_f32_to_s32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4704 bi_disasm_add_f32_to_s32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4719 bi_disasm_add_f32_to_u32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4734 bi_disasm_add_f32_to_u32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4749 bi_disasm_add_fadd_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4811 bi_disasm_add_fadd_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4863 bi_disasm_add_fadd_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4924 bi_disasm_add_fadd_rscale_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 4981 bi_disasm_add_fatan_assist_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5009 bi_disasm_add_fatan_assist_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5023 bi_disasm_add_fatan_table_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5051 bi_disasm_add_fatan_table_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5065 bi_disasm_add_fcmp_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5125 bi_disasm_add_fcmp_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5175 bi_disasm_add_fcos_table_u6(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5193 bi_disasm_add_fexp_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5207 bi_disasm_add_fexp_table_u4(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5225 bi_disasm_add_flogd_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5236 bi_disasm_add_flog_table_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5283 bi_disasm_add_flog_table_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5330 bi_disasm_add_flog_table_f32_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5375 bi_disasm_add_flog_table_f32_3(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5420 bi_disasm_add_flog_table_f32_4(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5461 bi_disasm_add_fmax_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5515 bi_disasm_add_fmax_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5579 bi_disasm_add_fmin_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5633 bi_disasm_add_fmin_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5697 bi_disasm_add_fpclass_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5715 bi_disasm_add_fpclass_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5726 bi_disasm_add_fpow_sc_apply(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5738 bi_disasm_add_fpow_sc_det_f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5769 bi_disasm_add_fpow_sc_det_f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5800 bi_disasm_add_fpow_sc_det_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5821 bi_disasm_add_frcbrt_approx_a_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5858 bi_disasm_add_frcbrt_approx_a_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5895 bi_disasm_add_frcbrt_approx_b_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5906 bi_disasm_add_frcbrt_approx_c_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5917 bi_disasm_add_frcp_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5956 bi_disasm_add_frcp_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 5986 bi_disasm_add_frcp_approx_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6023 bi_disasm_add_frcp_approx_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6060 bi_disasm_add_frexpe_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6096 bi_disasm_add_frexpe_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6128 bi_disasm_add_frexpe_v2f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6164 bi_disasm_add_frexpe_v2f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6196 bi_disasm_add_frexpm_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6237 bi_disasm_add_frexpm_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6278 bi_disasm_add_frexpm_v2f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6319 bi_disasm_add_frexpm_v2f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6360 bi_disasm_add_fround_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6398 bi_disasm_add_fround_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6436 bi_disasm_add_frsq_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6475 bi_disasm_add_frsq_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6505 bi_disasm_add_frsq_approx_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6542 bi_disasm_add_frsq_approx_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6579 bi_disasm_add_fsincos_offset_u6(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6597 bi_disasm_add_fsin_table_u6(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6615 bi_disasm_add_hadd_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6634 bi_disasm_add_hadd_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6653 bi_disasm_add_hadd_v2s16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6686 bi_disasm_add_hadd_v2u16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6719 bi_disasm_add_hadd_v4s8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6738 bi_disasm_add_hadd_v4u8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6757 bi_disasm_add_iabs_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6767 bi_disasm_add_iabs_v2s16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6784 bi_disasm_add_iabs_v4s8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6794 bi_disasm_add_iadd_s32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6818 bi_disasm_add_iadd_s32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6842 bi_disasm_add_iadd_s32_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6866 bi_disasm_add_iadd_u32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6890 bi_disasm_add_iadd_u32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6914 bi_disasm_add_iadd_u32_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6938 bi_disasm_add_iadd_v2s16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6967 bi_disasm_add_iadd_v2s16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 6996 bi_disasm_add_iadd_v2s16_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7025 bi_disasm_add_iadd_v2u16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7054 bi_disasm_add_iadd_v2u16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7083 bi_disasm_add_iadd_v2u16_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7112 bi_disasm_add_iadd_v4s8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7141 bi_disasm_add_iadd_v4s8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7170 bi_disasm_add_iadd_v4s8_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7199 bi_disasm_add_iadd_v4u8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7228 bi_disasm_add_iadd_v4u8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7257 bi_disasm_add_iadd_v4u8_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7286 bi_disasm_add_icmp_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7312 bi_disasm_add_icmp_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7336 bi_disasm_add_icmp_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7360 bi_disasm_add_icmp_v2i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7400 bi_disasm_add_icmp_v2s16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7438 bi_disasm_add_icmp_v2u16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7476 bi_disasm_add_icmp_v4i8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7502 bi_disasm_add_icmp_v4s8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7526 bi_disasm_add_icmp_v4u8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7550 bi_disasm_add_icmpf_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7564 bi_disasm_add_icmpi_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7590 bi_disasm_add_icmpi_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7616 bi_disasm_add_icmpi_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7642 bi_disasm_add_icmpm_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7656 bi_disasm_add_ilogb_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7673 bi_disasm_add_ilogb_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7690 bi_disasm_add_imov_fma(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7705 bi_disasm_add_isub_s32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7729 bi_disasm_add_isub_s32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7753 bi_disasm_add_isub_s32_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7777 bi_disasm_add_isub_u32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7801 bi_disasm_add_isub_u32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7825 bi_disasm_add_isub_u32_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7849 bi_disasm_add_isub_v2s16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7878 bi_disasm_add_isub_v2s16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7907 bi_disasm_add_isub_v2s16_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7936 bi_disasm_add_isub_v2u16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7965 bi_disasm_add_isub_v2u16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 7994 bi_disasm_add_isub_v2u16_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8023 bi_disasm_add_isub_v4s8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8052 bi_disasm_add_isub_v4s8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8081 bi_disasm_add_isub_v4s8_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8110 bi_disasm_add_isub_v4u8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8139 bi_disasm_add_isub_v4u8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8168 bi_disasm_add_isub_v4u8_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8197 bi_disasm_add_jump(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8208 bi_disasm_add_kaboom(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8218 bi_disasm_add_ldexp_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8237 bi_disasm_add_ldexp_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8256 bi_disasm_add_ld_attr_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8283 bi_disasm_add_ld_attr_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8310 bi_disasm_add_ld_attr_imm_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8336 bi_disasm_add_ld_attr_imm_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8362 bi_disasm_add_ld_attr_tex_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8389 bi_disasm_add_ld_attr_tex_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8416 bi_disasm_add_ld_cvt(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8439 bi_disasm_add_ld_gclk_u64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8455 bi_disasm_add_ld_tile(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8478 bi_disasm_add_ld_var_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8513 bi_disasm_add_ld_var_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8548 bi_disasm_add_ld_var_flat_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8578 bi_disasm_add_ld_var_flat_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8608 bi_disasm_add_ld_var_flat_imm_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8637 bi_disasm_add_ld_var_flat_imm_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8666 bi_disasm_add_ld_var_imm_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8700 bi_disasm_add_ld_var_imm_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8734 bi_disasm_add_ld_var_special_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8770 bi_disasm_add_ld_var_special_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8806 bi_disasm_add_lea_attr_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8826 bi_disasm_add_lea_attr_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8846 bi_disasm_add_lea_attr_imm_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8865 bi_disasm_add_lea_attr_imm_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8884 bi_disasm_add_lea_attr_tex_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8904 bi_disasm_add_lea_attr_tex_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8924 bi_disasm_add_lea_tex(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8946 bi_disasm_add_lea_tex_imm(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8967 bi_disasm_add_load_i128(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 8987 bi_disasm_add_load_i16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9017 bi_disasm_add_load_i16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9047 bi_disasm_add_load_i16_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9077 bi_disasm_add_load_i24(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9097 bi_disasm_add_load_i32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9127 bi_disasm_add_load_i32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9157 bi_disasm_add_load_i48(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9177 bi_disasm_add_load_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9197 bi_disasm_add_load_i8_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9227 bi_disasm_add_load_i8_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9257 bi_disasm_add_load_i8_2(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9287 bi_disasm_add_load_i8_3(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9317 bi_disasm_add_load_i96(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9337 bi_disasm_add_logb_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9354 bi_disasm_add_logb_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9371 bi_disasm_add_mkvec_v2i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9397 bi_disasm_add_mov_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9407 bi_disasm_add_mux_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9428 bi_disasm_add_mux_v2i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9470 bi_disasm_add_mux_v4i8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9491 bi_disasm_add_nop(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9499 bi_disasm_add_quiet_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9509 bi_disasm_add_quiet_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9526 bi_disasm_add_s16_to_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9543 bi_disasm_add_s16_to_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9560 bi_disasm_add_s32_to_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9575 bi_disasm_add_s32_to_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9590 bi_disasm_add_s8_to_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9607 bi_disasm_add_s8_to_s32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9624 bi_disasm_add_seg_add(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9648 bi_disasm_add_seg_sub(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9672 bi_disasm_add_shaddxh_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9684 bi_disasm_add_shift_double_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9698 bi_disasm_add_store_i128(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9718 bi_disasm_add_store_i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9738 bi_disasm_add_store_i24(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9758 bi_disasm_add_store_i32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9778 bi_disasm_add_store_i48(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9798 bi_disasm_add_store_i64(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9818 bi_disasm_add_store_i8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9838 bi_disasm_add_store_i96(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9858 bi_disasm_add_st_cvt(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9881 bi_disasm_add_st_tile(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9904 bi_disasm_add_swz_v2i16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9921 bi_disasm_add_swz_v4i8(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9938 bi_disasm_add_texc(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9961 bi_disasm_add_texs_2d_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 9990 bi_disasm_add_texs_2d_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10019 bi_disasm_add_texs_cube_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10043 bi_disasm_add_texs_cube_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10067 bi_disasm_add_u16_to_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10084 bi_disasm_add_u16_to_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10101 bi_disasm_add_u32_to_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10116 bi_disasm_add_u32_to_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10131 bi_disasm_add_u8_to_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10148 bi_disasm_add_u8_to_u32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10165 bi_disasm_add_v2f16_to_v2s16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10187 bi_disasm_add_v2f16_to_v2s16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10209 bi_disasm_add_v2f16_to_v2u16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10231 bi_disasm_add_v2f16_to_v2u16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10253 bi_disasm_add_v2f32_to_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10299 bi_disasm_add_v2s16_to_v2f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10321 bi_disasm_add_v2s16_to_v2f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10343 bi_disasm_add_v2s8_to_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10360 bi_disasm_add_v2s8_to_v2s16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10377 bi_disasm_add_v2u16_to_v2f16_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10399 bi_disasm_add_v2u16_to_v2f16_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10421 bi_disasm_add_v2u8_to_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10438 bi_disasm_add_v2u8_to_v2u16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10455 bi_disasm_add_var_tex_f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10490 bi_disasm_add_var_tex_f32(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10525 bi_disasm_add_vn_asst2_f32_0(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10547 bi_disasm_add_vn_asst2_f32_1(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10569 bi_disasm_add_vn_asst2_v2f16(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10586 bi_disasm_add_wmask(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10604 bi_disasm_add_zs_emit(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10629 bi_disasm_fma(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument 10905 bi_disasm_add(FILE * fp,unsigned bits,struct bifrost_regs * srcs,struct bifrost_regs * next_regs,unsigned staging_register,unsigned branch_offset,struct bi_constants * consts,bool last) argument [all...]
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A D	gen6_multisample_state.c	36 uint8_t bits; local in function:gen6_get_sample_position 43 bits = brw_multisample_positions_1x_2x >> (8 * index); 46 bits = brw_multisample_positions_4x >> (8 * index); 49 bits = brw_multisample_positions_8x[index >> 2] >> (8 * (index & 3)); 52 bits = brw_multisample_positions_16x[index >> 2] >> (8 * (index & 3)); 59 result[0] = ((bits >> 4) & 0xf) / 16.0f; 60 result[1] = (bits & 0xf) / 16.0f;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/state_trackers/va/
H A D	picture_vc1.c	38 context->desc.vc1.picture_type = vc1->picture_fields.bits.picture_type; 39 context->desc.vc1.frame_coding_mode = vc1->picture_fields.bits.frame_coding_mode; 41 context->desc.vc1.pulldown = vc1->sequence_fields.bits.pulldown; 42 context->desc.vc1.interlace = vc1->sequence_fields.bits.interlace; 43 context->desc.vc1.tfcntrflag = vc1->sequence_fields.bits.tfcntrflag; 44 context->desc.vc1.finterpflag = vc1->sequence_fields.bits.finterpflag; 45 context->desc.vc1.psf = vc1->sequence_fields.bits.psf; 46 context->desc.vc1.dquant = vc1->pic_quantizer_fields.bits.dquant; 47 context->desc.vc1.panscan_flag = vc1->entrypoint_fields.bits.panscan_flag; 49 vc1->reference_fields.bits [all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/va/
H A D	picture_vc1.c	38 context->desc.vc1.picture_type = vc1->picture_fields.bits.picture_type; 39 context->desc.vc1.frame_coding_mode = vc1->picture_fields.bits.frame_coding_mode; 41 context->desc.vc1.pulldown = vc1->sequence_fields.bits.pulldown; 42 context->desc.vc1.interlace = vc1->sequence_fields.bits.interlace; 43 context->desc.vc1.tfcntrflag = vc1->sequence_fields.bits.tfcntrflag; 44 context->desc.vc1.finterpflag = vc1->sequence_fields.bits.finterpflag; 45 context->desc.vc1.psf = vc1->sequence_fields.bits.psf; 46 context->desc.vc1.dquant = vc1->pic_quantizer_fields.bits.dquant; 47 context->desc.vc1.panscan_flag = vc1->entrypoint_fields.bits.panscan_flag; 49 vc1->reference_fields.bits [all...]
/xsrc/external/mit/xorg-server/dist/dix/
H A D	cursor.c	66 CursorBitsPtr bits; member in struct:_GlyphShare 77 FreeCursorBits(CursorBitsPtr bits) argument 79 if (--bits->refcnt > 0) 81 free(bits->source); 82 free(bits->mask); 83 free(bits->argb); 84 dixFiniPrivates(bits, PRIVATE_CURSOR_BITS); 85 if (bits->refcnt == 0) { 89 (this = *prev) && (this->bits != bits); pre 157 CheckForEmptyMask(CursorBitsPtr bits) argument 244 CursorBitsPtr bits; local in function:AllocARGBCursor 335 CursorBitsPtr bits; local in function:AllocGlyphCursor [all...]
/xsrc/external/mit/xorg-server/dist/test/xi2/
H A D	protocol-xiselectevents.c	48 * BadValue for invalid mask bits 122 _set_bit(unsigned char *bits, int bit) argument 124 SetBit(bits, bit); 126 SetBit(bits, XI_TouchBegin); 127 SetBit(bits, XI_TouchUpdate); 128 SetBit(bits, XI_TouchEnd); 131 SetBit(bits, XI_GesturePinchBegin); 132 SetBit(bits, XI_GesturePinchUpdate); 133 SetBit(bits, XI_GesturePinchEnd); 136 SetBit(bits, XI_GestureSwipeBegi 143 _clear_bit(unsigned char * bits,int bit) argument 169 unsigned char *bits; local in function:request_XISelectEvents_masks [all...]
/xsrc/external/mit/xorg-server.old/dist/dix/
H A D	cursor.c	69 CursorBitsPtr bits; member in struct:_GlyphShare 82 FreeCursorBits(CursorBitsPtr bits) argument 84 if (--bits->refcnt > 0) 86 free(bits->source); 87 free(bits->mask); 89 free(bits->argb); 91 dixFiniPrivates(bits, PRIVATE_CURSOR_BITS); 92 if (bits->refcnt == 0) 97 (this = *prev) && (this->bits != bits); 143 CheckForEmptyMask(CursorBitsPtr bits) argument 237 CursorBitsPtr bits; local in function:AllocARGBCursor 312 CursorBitsPtr bits; local in function:AllocGlyphCursor [all...]
/xsrc/external/mit/xorg-server/dist/glamor/
H A D	glamor_transfer.h	30 uint8_t *bits, uint32_t byte_stride); 35 uint8_t *bits, uint32_t byte_stride); 44 uint8_t *bits, uint32_t byte_stride); 47 glamor_download_rect(PixmapPtr pixmap, int x, int y, int w, int h, uint8_t *bits);
/xsrc/external/mit/brotli/dist/c/enc/
H A D	write_bits.h	7 /* Write bits into a byte array. */ 19 /* This function writes bits into bytes in increasing addresses, and within 22 The function can write up to 56 bits in one go with WriteBits 23 Example: let's assume that 3 bits (Rs below) have been written already: 29 Now, we could write 5 or less bits in MSB by just shifting by 3 32 For n bits, we take the last 5 bits, OR that with high bits in BYTE-0, 35 uint64_t bits, 39 (uint32_t)(bits >> 3 34 BrotliWriteBits(size_t n_bits,uint64_t bits,size_t * BROTLI_RESTRICT pos,uint8_t * BROTLI_RESTRICT array) argument [all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/vl/
H A D	vl_rbsp.h	84 * Make at least 16 more bits available 89 unsigned i, bits; local in function:vl_rbsp_fillbits 91 /* abort if we still have enough bits */ 97 /* abort if we have less than 24 bits left in this nal */ 101 /* check that we have enough bits left from the last fillbits */ 104 /* handle the already escaped bits */ 109 bits = vl_vlc_valid_bits(&rbsp->nal); 110 for (i = valid + 24; i <= bits; i += 8) { 113 rbsp->escaped = bits - i; 114 bits 137 unsigned bits = 0; local in function:vl_rbsp_ue 163 unsigned bits, value; local in function:vl_rbsp_more_data [all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/vl/
H A D	vl_rbsp.h	84 * Make at least 16 more bits available 89 unsigned i, bits; local in function:vl_rbsp_fillbits 91 /* abort if we still have enough bits */ 97 /* abort if we have less than 24 bits left in this nal */ 101 /* check that we have enough bits left from the last fillbits */ 104 /* handle the already escaped bits */ 109 bits = vl_vlc_valid_bits(&rbsp->nal); 110 for (i = valid + 24; i <= bits; i += 8) { 113 rbsp->escaped = bits - i; 114 bits 137 unsigned bits = 0; local in function:vl_rbsp_ue 163 unsigned bits, value; local in function:vl_rbsp_more_data [all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/fb/
H A D	fbblt.c	90 FbBits bits, bits1; local in function:fbBlt__rop 126 bits = READ(--src); 128 FbDoRightMaskByteMergeRop(dst, bits, endbyte, endmask); 136 bits = READ(--src); 138 WRITE(dst, FbDoMergeRop(bits, READ(dst))); 142 bits = READ(--src); 144 FbDoLeftMaskByteMergeRop(dst, bits, startbyte, startmask); 148 bits = READ(src++); 149 FbDoLeftMaskByteMergeRop(dst, bits, startbyte, startmask); 158 bits [all...]

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