Searched refs:cat2 (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Ddisasm-a3xx.c247 instr_cat2_t *cat2 = &instr->cat2; local in function:print_instr_cat2
258 switch (_OPC(2, cat2->opc)) {
265 fprintf(ctx->out, ".%s", cond[cat2->cond]);
270 if (cat2->ei)
272 print_reg_dst(ctx, (reg_t)(cat2->dst), cat2->full ^ cat2->dst_half, false);
275 unsigned src1_r = cat2->repeat ? cat2
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H A Dir3.c211 instr_cat2_t *cat2 = ptr; local in function:emit_cat2
220 cat2->src1_r = instr->nop & 0x1;
221 cat2->src2_r = (instr->nop >> 1) & 0x1;
223 cat2->src1_r = !!(src1->flags & IR3_REG_R);
225 cat2->src2_r = !!(src2->flags & IR3_REG_R);
230 cat2->rel1.src1 = reg(src1, info, instr->repeat,
233 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
234 cat2->rel1.src1_rel = 1;
237 cat2->c1.src1 = reg(src1, info, instr->repeat,
239 cat2
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H A Dinstr-a3xx.h793 instr_cat2_t cat2; member in union:PACKED
807 uint32_t ul : 1; /* cat2-cat4 (and cat1 in blob.. which may be bug??) */
821 case 2: return instr->cat2.repeat;
831 case 2: return instr->cat2.sat;
865 case 2: return instr->cat2.opc;
H A Dir3_compiler_nir.c390 dst[0]->cat2.condition = IR3_COND_NE;
404 dst[0]->cat2.condition = IR3_COND_NE;
435 * similar (generating a cat2 mov using max.f)
464 dst[0]->cat2.condition = IR3_COND_LT;
469 dst[0]->cat2.condition = IR3_COND_GE;
474 dst[0]->cat2.condition = IR3_COND_EQ;
479 dst[0]->cat2.condition = IR3_COND_NE;
578 dst[0]->cat2.condition = IR3_COND_LT;
583 dst[0]->cat2.condition = IR3_COND_GE;
588 dst[0]->cat2
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H A Dir3_cp.c135 * (note that some cat2 actually only have a single src)
604 instr->cat2 = cond->cat2;
H A Dir3_context.c500 cond->cat2.condition = IR3_COND_NE;
H A Dir3.h244 } cat2; member in union:ir3_instruction::__anond9a07c73060a
816 /* some cat2 instructions (ie. those which are not float) can embed an
860 /* map cat2 instruction to valid abs/neg flags: */
1236 /* cat2 instructions, most 2 src but some 1 src: */
/xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/
H A Disaspec.rst76 <bitset name="#instruction-cat2" extends="#instruction">
96 <pattern low="61" high="63">010</pattern> <!-- cat2 -->
99 SRC2_R is still a valid bit for (nopN) (REPEAT==0) for cat2
112 For example, cat2 instructions (ALU instructions with up to two src
117 <bitset name="#instruction-cat2-1src" extends="#instruction-cat2">
118 <override expr="#cat2-cat3-nop-encoding">
122 <derived name="NOP" expr="#cat2-cat3-nop-value" type="uint"/>
139 <bitset name="absneg.f" extends="#instruction-cat2-1src">
143 In this example, ``absneg.f`` is a concrete cat2 instructio
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H A Dir3-notes.rst6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or NOPs). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_cp.c106 (cmp->cat2.condition == IR3_COND_NE) &&
601 instr->cat2 = cond->cat2;
H A Dir3_compiler_nir.c402 dst[0]->cat2.condition = IR3_COND_NE;
412 dst[0]->cat2.condition = IR3_COND_NE;
459 * similar (generating a cat2 mov using max.f)
498 dst[0]->cat2.condition = IR3_COND_LT;
502 dst[0]->cat2.condition = IR3_COND_GE;
506 dst[0]->cat2.condition = IR3_COND_EQ;
510 dst[0]->cat2.condition = IR3_COND_NE;
620 dst[0]->cat2.condition = IR3_COND_LT;
624 dst[0]->cat2.condition = IR3_COND_GE;
628 dst[0]->cat2
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H A Dir3_parser.y902 cond: T_LT { instr->cat2.condition = IR3_COND_LT; }
903 | T_LE { instr->cat2.condition = IR3_COND_LE; }
904 | T_GT { instr->cat2.condition = IR3_COND_GT; }
905 | T_GE { instr->cat2.condition = IR3_COND_GE; }
906 | T_EQ { instr->cat2.condition = IR3_COND_EQ; }
907 | T_NE { instr->cat2.condition = IR3_COND_NE; }
1232 /* cat1 immediates differ slighly in the floating point case from the cat2
H A Dir3_print.c194 cond[instr->cat2.condition & 0x7]);
H A Dir3_context.c517 cond->cat2.condition = IR3_COND_NE;
H A Dir3.h328 } cat2; member in union:ir3_instruction::__anon3fdcb7e6050a
1227 /* some cat2 instructions (ie. those which are not float) can embed an
1271 /* map cat2 instruction to valid abs/neg flags: */
2023 /* cat2 instructions, most 2 src but some 1 src: */
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/freedreno/
H A Dir3-notes.rst6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or nops). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.1.0.rst1679 - freedreno/ir3: Add support for disasm of cat2 float32 immediates.
H A D20.2.0.rst4040 - freedreno/ir3/print: print cat2 condition

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