| /xsrc/external/mit/xf86-video-mach64/dist/src/ |
| H A D | atidri.c | 592 unsigned long cntl; local in function:ATIDRIAgpInit
719 cntl = inm( AGP_CNTL );
720 cntl &= ~AGP_APER_SIZE_MASK;
722 case 256: cntl |= AGP_APER_SIZE_256MB; break;
723 case 128: cntl |= AGP_APER_SIZE_128MB; break;
724 case 64: cntl |= AGP_APER_SIZE_64MB; break;
725 case 32: cntl |= AGP_APER_SIZE_32MB; break;
726 case 16: cntl |= AGP_APER_SIZE_16MB; break;
727 case 8: cntl |= AGP_APER_SIZE_8MB; break;
728 case 4: cntl |
[all...] |
| /xsrc/external/mit/xf86-video-r128/dist/src/ |
| H A D | r128_dri.c | 252 unsigned long cntl, chunk; local in function:R128DRIAgpInit
411 cntl = INREG(R128_AGP_CNTL);
412 cntl &= ~R128_AGP_APER_SIZE_MASK;
414 case 256: cntl |= R128_AGP_APER_SIZE_256MB; break;
415 case 128: cntl |= R128_AGP_APER_SIZE_128MB; break;
416 case 64: cntl |= R128_AGP_APER_SIZE_64MB; break;
417 case 32: cntl |= R128_AGP_APER_SIZE_32MB; break;
418 case 16: cntl |= R128_AGP_APER_SIZE_16MB; break;
419 case 8: cntl |= R128_AGP_APER_SIZE_8MB; break;
420 case 4: cntl |
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/ |
| H A D | fd6_gmem.c | 301 uint32_t cntl = 0; local in function:update_render_cntl
324 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
326 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
331 OUT_RING(ring, cntl |
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | radeon_uvd.c | 98 unsigned cntl; member in struct:ruvd_decoder::__anon99f448330108
1018 set_reg(dec, dec->reg.cntl, 1);
1134 dec->reg.cntl = RUVD_ENGINE_CNTL;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/ |
| H A D | radeon_uvd.c | 92 unsigned cntl; member in struct:ruvd_decoder::__anone03bbef10108
1200 set_reg(dec, dec->reg.cntl, 1);
1337 dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
1342 dec->reg.cntl = RUVD_ENGINE_CNTL;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/ |
| H A D | fd6_gmem.c | 337 uint32_t cntl = 0; local in function:update_render_cntl
361 cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
363 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
372 OUT_RING(ring, cntl |
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/ |
| H A D | radeon_uvd.c | 90 unsigned cntl; member in struct:ruvd_decoder::__anon6d6e80640108
1199 set_reg(dec, dec->reg.cntl, 1);
1333 dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
1338 dec->reg.cntl = RUVD_ENGINE_CNTL;
|
| H A D | radeon_vcn_dec.h | 1117 unsigned cntl; member in struct:radeon_decoder::__anone7b8034c1008
|
| H A D | radeon_vcn_dec.c | 2294 set_reg(dec, dec->reg.cntl, 1);
2468 dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
2478 dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
2492 dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | radeon_uvd.c | 98 unsigned cntl; member in struct:ruvd_decoder::__anon2b567f800108
1261 set_reg(dec, dec->reg.cntl, 1);
1378 dec->reg.cntl = RUVD_ENGINE_CNTL;
|
| /xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/ |
| H A D | tu_cmd_buffer.c | 570 uint32_t cntl = 0; local in function:tu6_emit_render_cntl
571 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
573 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
578 tu_cs_emit(cs, cntl);
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_state.c | 208 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & local in function:r200_set_blend_state
221 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
229 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_state.c | 208 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & local in function:r200_set_blend_state
221 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
229 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| H A D | tu_cmd_buffer.c | 360 uint32_t cntl = 0; local in function:tu6_emit_render_cntl
361 cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
365 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
378 cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
384 cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
389 tu_cs_emit(cs, cntl);
408 tu_cs_emit(cs, cntl);
|
| /xsrc/external/mit/libdrm/dist/tests/amdgpu/ |
| H A D | vcn_tests.c | 139 uint32_t cntl; member in struct:amdgpu_vcn_reg
668 ib_cpu[len++] = reg[vcn_reg_index].cntl;
|