Searched refs:cu_mask (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_shader_util.h106 bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask);
H A Dac_shader_util.c451 bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask)
454 *cu_mask = 0xffff;
488 *cu_mask &= info->chip_class == GFX10 ? ~BITFIELD_RANGE(2, 2) :
506 *cu_mask = 0xfffe; /* 1 CU disabled */
450 ac_compute_late_alloc(const struct radeon_info * info,bool ngg,bool ngg_culling,bool uses_scratch,unsigned * late_alloc_wave64,unsigned * cu_mask) argument
H A Dac_gpu_info.h192 uint32_t cu_mask[4][2]; member in struct:radeon_info
H A Dac_rgp.c360 uint16_t cu_mask[SQTT_MAX_NUM_SE][SQTT_SA_PER_SE]; member in struct:sqtt_file_chunk_asic_info
524 chunk->cu_mask[se][sa] = rad_info->cu_mask[se][sa];
H A Dac_gpu_info.c951 info->cu_mask[i % 4][j + i / 4] = amdinfo->cu_bitmap[i % 4][j + i / 4];
952 info->num_good_compute_units += util_bitcount(info->cu_mask[i][j]);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_sqtt.c42 return device->physical_device->rad_info.cu_mask[se][0] == 0;
72 int first_active_cu = ffs(device->physical_device->rad_info.cu_mask[se][0]);
635 int first_active_cu = ffs(device->physical_device->rad_info.cu_mask[se][0]);
H A Dradv_pipeline.c4456 unsigned late_alloc_wave64, cu_mask; local in function:radv_pipeline_generate_hw_vs
4458 shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask);
4462 S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F));
4619 unsigned late_alloc_wave64, cu_mask; local in function:radv_pipeline_generate_hw_ngg
4621 shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask);
4625 S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F));
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_sqtt.c74 return sctx->screen->info.cu_mask[se][0] == 0;
104 int first_active_cu = ffs(sctx->screen->info.cu_mask[se][0]);
545 int first_active_cu = ffs(sctx->screen->info.cu_mask[se][0]);
H A Dsi_state_shaders.c1211 unsigned late_alloc_wave64, cu_mask; local in function:gfx10_shader_ngg
1215 &late_alloc_wave64, &cu_mask);
1235 shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs = S_00B21C_CU_EN(cu_mask) |
1492 unsigned late_alloc_wave64, cu_mask; local in function:si_shader_vs
1495 &late_alloc_wave64, &cu_mask);
1505 S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F));
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.1.0.rst3885 - ac: add ac_gpu_info::cu_mask to store bitmask of compute units
3886 - radv/rgp: report correct cu_mask info
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json17689 "description": "ac/gpu_info: set cu_mask correctly for Arcturus",
[all...]

Completed in 141 milliseconds