| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_texture.c | 426 return tex->dcc_offset &&
442 tex->dcc_offset = 0;
574 tex->dcc_offset = new_tex->dcc_offset;
605 assert(!tex->dcc_offset);
631 if (tex->dcc_offset && !tex->dcc_separate_buffer) {
632 uint64_t dcc_offset = local in function:si_set_tex_bo_metadata
634 : tex->dcc_offset;
636 assert((dcc_offset >> 8) != 0 && (dcc_offset >>
[all...] |
| H A D | si_clear.c | 230 uint64_t dcc_offset, clear_size; local in function:vi_dcc_clear_level
236 dcc_offset = 0;
239 dcc_offset = tex->dcc_offset;
260 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
265 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
676 if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
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| H A D | si_compute_blit.c | 454 assert(tex->dcc_offset && tex->dcc_offset <= UINT_MAX);
469 img[1].u.buf.offset = tex->dcc_offset;
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| H A D | si_blit.c | 480 assert(tex->dcc_offset);
546 if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->dcc_offset)
609 if (!tex->dcc_offset)
867 } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->dcc_offset) {
923 !sdst->dcc_offset &&
1317 if (!tex->is_depth && (tex->cmask_buffer || tex->dcc_offset)) {
1362 if (!tex->dcc_offset || !sctx->has_graphics)
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| H A D | si_descriptors.c | 356 tex->dcc_offset;
359 meta_va += base_level_info->dcc_offset;
392 if (tex->dcc_offset)
481 (tex->cmask_buffer || tex->dcc_offset));
530 if (tex->dcc_offset &&
2455 if (tex->dcc_offset &&
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| H A D | si_pipe.h | 292 uint64_t dcc_offset; /* 0 = disabled */ member in struct:si_texture
333 * target == 2D and last_level == 0. If enabled, dcc_offset contains
1429 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
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| H A D | si_state.c | 3098 tex->dcc_offset) >> 8;
3105 if (tex->dcc_offset)
3158 cb_dcc_base += level_info->dcc_offset >> 8;
3884 if (tex->dcc_offset) {
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| H A D | ac_surface.h | 80 uint32_t dcc_offset; /* relative offset within DCC mip tree */ member in struct:legacy_surf_level
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| H A D | ac_surface.c | 374 surf_level->dcc_offset = 0;
393 surf_level->dcc_offset = surf->dcc_size;
395 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_image.c | 377 meta_va = gpu_address + image->dcc_offset;
379 meta_va += base_level_info->dcc_offset;
410 if (image->dcc_offset)
591 if (image->dcc_offset) {
722 desc[7] = image->dcc_offset >> 8;
884 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
886 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
889 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24;
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| H A D | radv_private.h | 1528 uint64_t dcc_offset; member in struct:radv_image
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| H A D | radv_meta_clear.c | 1344 image->offset + image->dcc_offset,
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| H A D | radv_device.c | 4256 if (iview->image->dcc_offset)
4308 va += iview->image->dcc_offset;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_clear.c | 297 uint64_t dcc_offset = tex->surface.meta_offset; local in function:vi_dcc_get_clear_info
312 dcc_offset += tex->surface.u.gfx9.meta_levels[level].offset;
354 dcc_offset += tex->surface.u.legacy.color.dcc_level[level].dcc_offset;
358 si_init_buffer_clear(out, dcc_buffer, dcc_offset, clear_size, clear_value);
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| H A D | si_texture.c | 838 i, i < tex->surface.num_meta_levels, tex->surface.u.legacy.color.dcc_level[i].dcc_offset,
1075 size = tex->surface.u.legacy.color.dcc_level[i].dcc_offset +
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| H A D | si_descriptors.c | 326 meta_va += tex->surface.u.legacy.color.dcc_level[base_level].dcc_offset;
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| H A D | si_state.c | 3219 cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8;
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| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| H A D | ac_surface.h | 101 uint32_t dcc_offset; /* relative offset within DCC mip tree */ member in struct:legacy_surf_dcc_level
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| H A D | ac_surface.c | 677 dcc_level->dcc_offset = 0;
692 dcc_level->dcc_offset = surf->meta_size;
694 surf->meta_size = dcc_level->dcc_offset + AddrDccOut->dccRamSize;
2558 uint64_t dcc_offset = 0; local in function:ac_surface_get_bo_metadata
2561 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset;
2562 assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24));
2566 *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8);
2687 /* Disable DCC. dcc_offset is always set by texture_from_handle
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_image.c | 754 meta_va += plane->surface.u.legacy.color.dcc_level[base_level].dcc_offset;
1268 uint64_t dcc_offset = local in function:radv_init_metadata
1272 metadata->u.gfx9.dcc_offset_256b = dcc_offset >> 8;
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| H A D | radv_meta_clear.c | 1494 dcc_level->dcc_offset + dcc_level->dcc_slice_fast_clear_size * range->baseArrayLayer;
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| H A D | radv_cmd_buffer.c | 7439 size = dcc_level->dcc_offset + dcc_fast_clear_size;
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| H A D | radv_device.c | 6680 va += plane->surface.u.legacy.color.dcc_level[iview->base_mip].dcc_offset;
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.2.0.rst | 3235 - radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly
|