Searched refs:dpb (Results 1 - 21 of 21) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dradeon_vce.c145 * get number of cpbs based on dpb
151 unsigned dpb; local in function:get_cpb_num
155 dpb = 396;
158 dpb = 900;
163 dpb = 2376;
166 dpb = 4752;
170 dpb = 8100;
173 dpb = 18000;
176 dpb = 20480;
180 dpb
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H A Dradeon_uvd.c90 struct rvid_buffer dpb; member in struct:ruvd_decoder
291 // always align them to MB size for dpb calculation
1046 rvid_destroy_buffer(&dec->dpb);
1187 if (dec->dpb.res)
1188 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1245 if (dec->dpb.res)
1246 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1368 if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1369 RVID_ERR("Can't allocated dpb.\n");
1372 rvid_clear_buffer(context, &dec->dpb);
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_vcn_enc.c120 unsigned dpb; local in function:get_cpb_num
124 dpb = 396;
127 dpb = 900;
132 dpb = 2376;
135 dpb = 4752;
139 dpb = 8100;
142 dpb = 18000;
145 dpb = 20480;
149 dpb = 32768;
152 dpb
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H A Dradeon_uvd_enc.c134 unsigned dpb; local in function:get_cpb_num
138 dpb = 36864;
142 dpb = 122880;
146 dpb = 245760;
150 dpb = 552960;
154 dpb = 983040;
159 dpb = 2228224;
165 dpb = 8912896;
172 dpb = 35651584;
176 return MIN2(dpb / (
[all...]
H A Dradeon_vce.c139 * get number of cpbs based on dpb
145 unsigned dpb; local in function:get_cpb_num
149 dpb = 396;
152 dpb = 900;
157 dpb = 2376;
160 dpb = 4752;
164 dpb = 8100;
167 dpb = 18000;
170 dpb = 20480;
174 dpb
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H A Dradeon_uvd.c84 struct rvid_buffer dpb; member in struct:ruvd_decoder
345 // always align them to MB size for dpb calculation
993 si_vid_destroy_buffer(&dec->dpb);
1120 if (dec->dpb.res)
1121 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1184 if (dec->dpb.res)
1185 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1307 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1308 RVID_ERR("Can't allocated dpb.\n");
1311 si_vid_clear_buffer(context, &dec->dpb);
[all...]
H A Dradeon_vcn_dec.c824 decode->dpb_size = dec->dpb.res->buf->size;
1141 // always align them to MB size for dpb calculation
1292 si_vid_destroy_buffer(&dec->dpb);
1400 send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1562 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1563 RVID_ERR("Can't allocated dpb.\n");
1566 si_vid_clear_buffer(context, &dec->dpb);
1610 si_vid_destroy_buffer(&dec->dpb);
H A Dradeon_vcn_dec.h752 struct rvid_buffer dpb; member in struct:radeon_decoder
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dradeon_vce.c149 * get number of cpbs based on dpb
155 unsigned dpb; local in function:get_cpb_num
159 dpb = 396;
162 dpb = 900;
167 dpb = 2376;
170 dpb = 4752;
174 dpb = 8100;
177 dpb = 18000;
180 dpb = 20480;
184 dpb
[all...]
H A Dradeon_uvd.c90 struct rvid_buffer dpb; member in struct:ruvd_decoder
240 // always align them to MB size for dpb calculation
819 rvid_destroy_buffer(&dec->dpb);
962 if (dec->dpb.res)
963 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1002 if (dec->dpb.res)
1003 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1124 if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1125 RVID_ERR("Can't allocated dpb.\n");
1128 rvid_clear_buffer(context, &dec->dpb);
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc.c124 unsigned dpb; local in function:get_cpb_num
128 dpb = 36864;
132 dpb = 122880;
136 dpb = 245760;
140 dpb = 552960;
144 dpb = 983040;
149 dpb = 2228224;
155 dpb = 8912896;
162 dpb = 35651584;
166 return MIN2(dpb / (
[all...]
H A Dradeon_vce.c136 * get number of cpbs based on dpb
142 unsigned dpb; local in function:get_cpb_num
146 dpb = 396;
149 dpb = 900;
154 dpb = 2376;
157 dpb = 4752;
161 dpb = 8100;
164 dpb = 18000;
167 dpb = 20480;
171 dpb
[all...]
H A Dradeon_vcn_enc.c232 unsigned dpb; local in function:get_cpb_num
236 dpb = 396;
239 dpb = 900;
244 dpb = 2376;
247 dpb = 4752;
251 dpb = 8100;
254 dpb = 18000;
257 dpb = 20480;
261 dpb = 32768;
264 dpb
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H A Dradeon_vcn_dec.c1342 struct rvcn_dec_dynamic_dpb_t2 *dpb = NULL, *dummy = NULL; local in function:rvcn_dec_dynamic_dpb_t2_message
1359 addr = dec->ws->buffer_get_virtual_address(d->dpb.res->buf);
1362 addr = dec->ws->buffer_get_virtual_address(dummy->dpb.res->buf);
1371 if (d->dpb.res->b.b.width0 * d->dpb.res->b.b.height0 != size) {
1381 if (d->dpb.res->b.b.width0 * d->dpb.res->b.b.height0 == size && d->index == dec->ref_codec.index) {
1382 dpb = d;
1387 if (!dpb) {
1391 dpb
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H A Dradeon_uvd.c82 struct rvid_buffer dpb; member in struct:ruvd_decoder
338 // always align them to MB size for dpb calculation
993 si_vid_destroy_buffer(&dec->dpb);
1116 if (dec->dpb.res)
1117 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1184 if (dec->dpb.res)
1185 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0, RADEON_USAGE_READWRITE,
1304 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1305 RVID_ERR("Can't allocated dpb.\n");
1308 si_vid_clear_buffer(context, &dec->dpb);
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H A Dradeon_vcn_dec.h1077 struct rvid_buffer dpb; member in struct:rvcn_dec_dynamic_dpb_t2
1103 struct rvid_buffer dpb; member in struct:radeon_decoder
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.1.0.rst1118 - frontends/omx/h265: search entire dpb list
3094 - radeon/vcn: add dynamic dpb interface
3095 - radeon/vcn: add dynamic dpb buffer Tier1 support
3096 - radeon/vcn: enable dynamic dpb Tier1 support
3097 - radeon/vcn: add dynamic dpb Tier2 message buffer interface
3098 - radeon/vcn: implement dynamic dpb Tier2 support
3099 - radeon/vcn: enable dynamic dpb Tier2 support
H A D21.0.0.rst1944 - radeon/vcn: add AV1 dpb buffer size
H A D21.3.0.rst2394 - radeon/vcn: reuse the dpb buffers when with the same size.
H A D20.3.0.rst3967 - radeon/vcn: delay dec->ctx and dec->dpb allocation
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json15286 "description": "radeon/vcn: enable dynamic dpb Tier2 for hevc dec vaapi path",
15295 "description": "radeon/vcn: enable dynamic dpb Tier2 support for h264 dec vaapi path",
23395 "description": "radeon/vcn: implement encoder dpb management",
23422 "description": "radeon/vcn: increase encoder dpb size",
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