| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_device.c | 2089 uint32_t esgs_ring_size,
2109 desc[2] = esgs_ring_size;
2127 desc[6] = esgs_ring_size;
2303 uint32_t esgs_ring_size,
2318 radeon_emit(cs, esgs_ring_size >> 8);
2322 radeon_emit(cs, esgs_ring_size >> 8);
2451 uint32_t esgs_ring_size,
2489 esgs_ring_size <= queue->esgs_ring_size &&
2496 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size
2920 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0; local
[all...] |
| radv_private.h | 648 uint32_t esgs_ring_size; member in struct:radv_queue
1394 unsigned esgs_ring_size; member in struct:radv_pipeline::__anon3259::__anon3260
|
| radv_pipeline.c | 1578 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size * local
1584 esgs_ring_size = align(esgs_ring_size, alignment);
1588 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
|
| radv_cmd_buffer.c | 3045 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3046 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_device.c | 3372 uint32_t esgs_ring_size, struct radeon_winsys_bo *esgs_ring_bo,
3386 desc[2] = esgs_ring_size;
3404 desc[6] = esgs_ring_size;
3582 struct radeon_winsys_bo *esgs_ring_bo, uint32_t esgs_ring_size,
3596 radeon_emit(cs, esgs_ring_size >> 8);
3600 radeon_emit(cs, esgs_ring_size >> 8);
3745 uint32_t compute_scratch_waves, uint32_t esgs_ring_size,
3807 esgs_ring_size <= queue->esgs_ring_size && gsvs_ring_size <= queue->gsvs_ring_size &&
3813 if (!scratch_size_per_wave && !compute_scratch_size_per_wave && !esgs_ring_size &
4399 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0; local
[all...] |
| radv_shader.h | 221 uint32_t esgs_ring_size; member in struct:gfx10_ngg_info
|
| radv_pipeline.c | 2200 ngg->esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) * esvert_lds_size * 4;
2239 unsigned esgs_ring_size = local
2244 esgs_ring_size = align(esgs_ring_size, alignment);
2248 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
|
| radv_private.h | 673 uint32_t esgs_ring_size; member in struct:radv_queue
1799 unsigned esgs_ring_size; member in struct:radv_pipeline::__anon570::__anon571
|
| radv_shader.c | 1021 info->ngg_info.esgs_ring_size,
1587 sym->size = binary->info.ngg_info.esgs_ring_size;
|
| radv_cmd_buffer.c | 4925 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
4926 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_shader.h | 735 unsigned esgs_ring_size; /* in bytes */ member in struct:gfx9_gs_info
|
| si_state_shaders.c | 760 out->esgs_ring_size = esgs_lds_size;
3589 unsigned esgs_ring_size = local
3594 esgs_ring_size = align(esgs_ring_size, alignment);
3597 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3605 bool update_esgs = sctx->chip_class <= GFX8 && esgs_ring_size &&
3606 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size);
3619 esgs_ring_size, sctx->screen->info.pte_fragment_size);
|
| si_shader.c | 792 sym->size = shader->gs_info.esgs_ring_size * 4;
|
| gfx10_shader_ngg.c | 2159 shader->gs_info.esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) *
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| si_state_shaders.c | 2930 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size * local
2936 esgs_ring_size = align(esgs_ring_size, alignment);
2939 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2948 esgs_ring_size &&
2950 sctx->esgs_ring->width0 < esgs_ring_size);
2964 esgs_ring_size, alignment);
|
