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  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
crocus_genx_protos.h 23 /* GenX-specific function declarations.
31 void genX(crocus_init_state)(struct crocus_context *ice);
32 void genX(crocus_init_screen_state)(struct crocus_screen *screen);
33 void genX(crocus_upload_urb)(struct crocus_batch *batch,
37 void genX(crocus_update_pma_fix)(struct crocus_context *ice,
41 void genX(crocus_init_blorp)(struct crocus_context *ice);
44 void genX(crocus_init_query)(struct crocus_context *ice);
45 void genX(crocus_init_screen_query)(struct crocus_screen *screen);
48 void genX(crocus_init_blt)(struct crocus_screen *screen);
crocus_context.h 621 /** GenX-specific current state */
622 struct crocus_genx_state *genx; member in struct:crocus_context::__anon1142
978 #ifdef genX
981 # define genX(x) gfx4_##x
983 # undef genX
984 # define genX(x) gfx45_##x
986 # undef genX
987 # define genX(x) gfx5_##x
989 # undef genX
990 # define genX(x) gfx6_##
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
iris_genx_protos.h 23 /* GenX-specific function declarations.
31 void genX(init_state)(struct iris_context *ice);
32 void genX(init_screen_state)(struct iris_screen *screen);
33 void genX(emit_hashing_mode)(struct iris_context *ice,
37 void genX(emit_depth_state_workarounds)(struct iris_context *ice,
40 void genX(update_pma_fix)(struct iris_context *ice,
44 void genX(invalidate_aux_map_state)(struct iris_batch *batch);
47 void genX(init_blorp)(struct iris_context *ice);
50 void genX(init_query)(struct iris_context *ice);
51 void genX(math_add32_gpr0)(struct iris_context *ice
    [all...]
iris_context.h 761 /** GenX-specific current state */
762 struct iris_genx_state *genx; member in struct:iris_context::__anon1236
837 /** Last rendering scale argument provided to genX(emit_hashing_mode). */
1071 #ifdef genX
1074 # define genX(x) gfx4_##x
1076 # undef genX
1077 # define genX(x) gfx5_##x
1079 # undef genX
1080 # define genX(x) gfx6_##x
1082 # undef genX
    [all...]
iris_blorp.c 30 * GenX specific code for working with BLORP (blitting, resolves, clears
289 genX(emit_depth_state_workarounds)(ice, batch, &params->depth.surf);
304 genX(update_pma_fix)(ice, batch, false);
309 genX(emit_hashing_mode)(ice, batch, params->x1 - params->x0,
314 genX(invalidate_aux_map_state)(batch);
406 genX(init_blorp)(struct iris_context *ice)
  /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
anv_genX.h 32 * In this header file, the usual genx() macro is available.
39 VkResult genX(init_device_state)(struct anv_device *device);
41 void genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer);
43 void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer);
45 void genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer);
47 void genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer);
48 void genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer);
50 void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
53 void genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer);
54 void genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
    [all...]
genX_blorp_exec.c 207 genX(emit_urb_setup)(device, &cmd_buffer->batch,
215 genX(blorp_exec)(struct blorp_batch *batch,
223 genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
243 * See genX(cmd_buffer_mi_memcpy) for more details.
250 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
252 genX(flush_pipeline_select_3d)(cmd_buffer);
254 genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
259 genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
genX_query.c 41 VkResult genX(CreateQueryPool)(
137 void genX(DestroyQueryPool)(
220 VkResult genX(GetQueryPoolResults)(
337 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
361 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
414 void genX(CmdResetQueryPool)(
448 void genX(ResetQueryPoolEXT)(
463 GENX(IA_VERTICES_COUNT_num),
464 GENX(IA_PRIMITIVES_COUNT_num),
465 GENX(VS_INVOCATION_COUNT_num)
    [all...]
genX_gpu_memcpy.c 55 genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
78 genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
81 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
83 genX(flush_pipeline_select_3d)(cmd_buffer);
86 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
87 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
88 &(struct GENX(VERTEX_BUFFER_STATE)) {
101 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
102 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,
103 &(struct GENX(VERTEX_ELEMENT_STATE))
    [all...]
genX_cmd_buffer.c 45 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
52 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
68 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
74 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
76 sba.GeneralStateMOCS = GENX(MOCS);
79 sba.StatelessDataPortAccessMOCS = GENX(MOCS);
83 sba.SurfaceStateMOCS = GENX(MOCS);
88 sba.DynamicStateMOCS = GENX(MOCS);
92 sba.IndirectObjectMOCS = GENX(MOCS);
97 sba.InstructionMOCS = GENX(MOCS)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
anv_genX.h 32 * In this header file, the usual genx() macro is available.
39 extern const uint32_t genX(vk_to_intel_cullmode)[];
41 extern const uint32_t genX(vk_to_intel_front_face)[];
43 extern const uint32_t genX(vk_to_intel_primitive_type)[];
45 extern const uint32_t genX(vk_to_intel_compare_op)[];
47 extern const uint32_t genX(vk_to_intel_stencil_op)[];
49 extern const uint32_t genX(vk_to_intel_logic_op)[];
51 void genX(init_physical_device_state)(struct anv_physical_device *device);
53 VkResult genX(init_device_state)(struct anv_device *device);
55 void genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
    [all...]
genX_blorp_exec.c 213 genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer,
217 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
223 genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL,
253 genX(blorp_exec)(struct blorp_batch *batch,
265 genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
269 genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, params->x1 - params->x0,
289 genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, &params->depth.surf);
294 * See genX(cmd_buffer_mi_memcpy) for more details.
304 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
307 genX(flush_pipeline_select_gpgpu)(cmd_buffer)
    [all...]
gfx7_cmd_buffer.c 156 void genX(CmdBindIndexBuffer)(
204 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
214 topology = genX(vk_to_intel_primitive_type)[d->primitive_topology];
238 genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
242 genX(ms_rasterization_mode)(pipeline, dynamic_raster_mode);
245 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
246 struct GENX(3DSTATE_SF) sf = {
247 GENX(3DSTATE_SF_header),
253 .FrontWinding = genX(vk_to_intel_front_face)[d->front_face],
254 .CullMode = genX(vk_to_intel_cullmode)[d->cull_mode]
    [all...]
gfx8_cmd_buffer.c 52 struct GENX(SF_CLIP_VIEWPORT) sfv = {
85 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv);
89 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
115 struct GENX(CC_VIEWPORT) cc_viewport = {
120 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
124 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
131 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
147 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
167 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri)
    [all...]
genX_gpu_memcpy.c 55 genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
78 genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
81 genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, 32, src, size);
82 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
84 genX(flush_pipeline_select_3d)(cmd_buffer);
87 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
88 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
89 &(struct GENX(VERTEX_BUFFER_STATE)) {
105 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
106 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1
    [all...]
genX_cmd_buffer.c 51 static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
55 convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
89 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
107 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
136 genX(flush_pipeline_select_3d)(cmd_buffer);
139 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
232 genX(flush_pipeline_select)(cmd_buffer, gfx12_wa_pipeline);
272 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
521 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
783 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi)
    [all...]
genX_pipeline.c 117 GENX(3DSTATE_VERTEX_ELEMENTS));
139 struct GENX(VERTEX_ELEMENT_STATE) element = {
146 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
167 struct GENX(VERTEX_ELEMENT_STATE) element = {
178 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
185 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
209 struct GENX(VERTEX_ELEMENT_STATE) element = {
223 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
226 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
233 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_SGVS), sgvs)
    [all...]
genX_query.c 60 VkResult genX(CreateQueryPool)(
219 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
234 void genX(DestroyQueryPool)(
431 VkResult genX(GetQueryPoolResults)(
609 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
611 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
636 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
638 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
715 void genX(CmdResetQueryPool)(
775 void genX(ResetQueryPool)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/genxml/
gen_macros.h 29 * The prefixing macros GENX() and genX() automatically prefix whatever you
63 # define GENX(X) GFX4_##X
64 # define genX(x) gfx4_##x
66 # define GENX(X) GFX45_##X
67 # define genX(x) gfx45_##x
69 # define GENX(X) GFX5_##X
70 # define genX(x) gfx5_##x
72 # define GENX(X) GFX6_##X
73 # define genX(x) gfx6_##
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/intel/genxml/
gen_macros.h 29 * The prefixing macros GENX() and genX() automatically prefix whatever you
65 # define GENX(X) GEN4_##X
66 # define genX(x) gen4_##x
68 # define GENX(X) GEN45_##X
69 # define genX(x) gen45_##x
71 # define GENX(X) GEN5_##X
72 # define genX(x) gen5_##x
74 # define GENX(X) GEN6_##X
75 # define genX(x) gen6_##
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/isl/
isl_priv.h 200 /* This is useful for adding the isl_prefix to genX functions */
203 #define isl_genX(x) __PASTE(isl_, genX(x))
205 #ifdef genX
208 # define genX(x) gfx4_##x
210 # undef genX
211 # define genX(x) gfx5_##x
213 # undef genX
214 # define genX(x) gfx6_##x
216 # undef genX
217 # define genX(x) gfx7_##
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/intel/isl/
isl_priv.h 200 /* This is useful for adding the isl_prefix to genX functions */
203 #define isl_genX(x) __PASTE(isl_, genX(x))
205 #ifdef genX
208 # define genX(x) gen4_##x
210 # undef genX
211 # define genX(x) gen5_##x
213 # undef genX
214 # define genX(x) gen6_##x
216 # undef genX
217 # define genX(x) gen7_##
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
genX_state_upload.c 82 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_MEM), lrm) {
93 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) {
104 genX(upload_polygon_stipple)(struct brw_context *brw)
112 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
130 static const struct brw_tracked_state genX(polygon_stipple) = {
136 .emit = genX(upload_polygon_stipple),
143 genX(upload_polygon_stipple_offset)(struct brw_context *brw)
151 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) {
167 static const struct brw_tracked_state genX(polygon_stipple_offset) = {
173 .emit = genX(upload_polygon_stipple_offset)
    [all...]
genX_pipe_control.c 83 genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
119 genX(emit_raw_pipe_control)(brw, 0, NULL, 0, 0);
132 genX(emit_raw_pipe_control)(brw, PIPE_CONTROL_CS_STALL, NULL, 0, 0);
465 brw_batch_emit(brw, GENX(PIPE_CONTROL), pc) {
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
genX_state_upload.c 79 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_MEM), lrm) {
89 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) {
99 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_REG), lrr) {
110 genX(upload_polygon_stipple)(struct brw_context *brw)
118 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
136 static const struct brw_tracked_state genX(polygon_stipple) = {
142 .emit = genX(upload_polygon_stipple),
149 genX(upload_polygon_stipple_offset)(struct brw_context *brw)
157 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) {
173 static const struct brw_tracked_state genX(polygon_stipple_offset) =
    [all...]

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