Searched refs:gfx_cs (Results 1 - 25 of 47) sorted by relevance

12

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_cp_dma.c160 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst), RADEON_USAGE_WRITE,
163 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src), RADEON_USAGE_READ,
170 sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
271 si_emit_cp_dma(sctx, &sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags, cache_policy);
334 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) {
360 si_emit_cp_dma(sctx, &sctx->gfx_cs, main_dst_offset, main_src_offset, byte_count, dma_flags,
375 si_emit_cp_dma(sctx, &sctx->gfx_cs, dst_offset, src_offset, skipped_size, dma_flags,
420 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
441 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, src, 0, 4, 0xabcdef01, SI_OP_SYNC_BEFORE_AFTER,
443 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, sr
[all...]
H A Dsi_cp_reg_shadowing.c168 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowed_regs->b.b,
177 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->shadowed_regs,
180 ac_emulate_clear_state(&sctx->screen->info, &sctx->gfx_cs, si_set_context_reg_array);
192 sctx->ws->cs_setup_preemption(&sctx->gfx_cs, shadowing_preamble->pm4,
H A Dsi_state_streamout.c211 sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
217 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
237 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_READ,
267 si_cp_release_mem(sctx, &sctx->gfx_cs, V_028A90_PS_DONE, 0, EOP_DST_SEL_TC_L2,
279 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
308 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
342 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_READ,
367 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
389 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size, RADEON_USAGE_WRITE,
416 radeon_begin(&sctx->gfx_cs);
[all...]
H A Dsi_gfx_cs.c36 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
116 si_cp_dma_wait_for_idle(ctx, &ctx->gfx_cs);
121 ctx->emit_cache_flush(ctx, &ctx->gfx_cs);
163 si_handle_thread_trace(ctx, &ctx->gfx_cs);
198 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
205 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds, RADEON_USAGE_READWRITE, 0, 0);
207 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->gds_oa, RADEON_USAGE_READWRITE, 0, 0);
322 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) {
357 is_secure = ctx->ws->cs_is_secure(&ctx->gfx_cs);
389 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ct
[all...]
H A Dsi_fence.c91 struct si_resource *scratch = unlikely(ctx->ws->cs_is_secure(&ctx->gfx_cs)) ?
100 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, RADEON_USAGE_WRITE,
129 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, scratch, RADEON_USAGE_WRITE,
144 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
176 ws->cs_add_fence_dependency(&sctx->gfx_cs, fence, 0);
181 sctx->ws->cs_add_syncobj_signal(&sctx->gfx_cs, fence);
257 radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
258 si_cp_release_mem(ctx, &ctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM,
468 if (!radeon_emitted(&sctx->gfx_cs, sctx->initial_gfx_cs_size)) {
472 ws->cs_sync_flush(&sctx->gfx_cs);
[all...]
H A Dsi_perfcounter.c63 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
90 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
103 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
129 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
131 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_DST_MEM, buffer, va - buffer->gpu_address,
148 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
169 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
225 radeon_begin(&sctx->gfx_cs);
253 si_inhibit_clockgating(sctx, &sctx->gfx_cs, true);
307 si_inhibit_clockgating(sctx, &sctx->gfx_cs, fals
[all...]
H A Dsi_compute.c403 if (cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics) {
423 (cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics)) {
479 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
526 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->scratch_bo, RADEON_USAGE_READWRITE,
537 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo, RADEON_USAGE_READ,
571 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
610 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
657 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf, RADEON_USAGE_READ,
714 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer, RADEON_USAGE_READ,
726 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
[all...]
H A Dsi_pm4.c118 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
121 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_shader*)state)->bo,
H A Dsi_state_viewport.c104 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf,
106 radeon_begin(&sctx->gfx_cs);
359 radeon_begin(&ctx->gfx_cs);
376 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
472 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
486 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
523 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
614 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
H A Dsi_test_dma_perf.c175 sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
188 si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, dst, 0, size, clear_value,
239 sctx->emit_cache_flush(sctx, &sctx->gfx_cs);
H A Dsi_state_draw.cpp102 radeon_begin(&sctx->gfx_cs);
678 uint64_t ring_va = (unlikely(sctx->ws->cs_is_secure(&sctx->gfx_cs)) ?
710 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1059 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1123 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1169 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1237 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1254 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1301 radeon_begin(&sctx->gfx_cs); \
1320 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
[all...]
H A Dsi_state_binning.c407 radeon_begin(&sctx->gfx_cs);
505 radeon_begin(&sctx->gfx_cs);
H A Dsi_buffer.c36 return sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, buf, usage);
42 return sctx->ws->buffer_map(sctx->ws, resource->buf, &sctx->gfx_cs, usage);
709 if (radeon_emitted(&ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
710 ctx->ws->cs_is_buffer_referenced(&ctx->gfx_cs, res->buf, RADEON_USAGE_READWRITE)) {
713 ctx->ws->cs_sync_flush(&ctx->gfx_cs);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_streamout.c194 struct radeon_cmdbuf *cs = sctx->gfx_cs;
220 struct radeon_cmdbuf *cs = sctx->gfx_cs;
254 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
275 struct radeon_cmdbuf *cs = sctx->gfx_cs;
296 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
323 radeon_set_context_reg_seq(sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
324 radeon_emit(sctx->gfx_cs,
330 radeon_emit(sctx->gfx_cs,
H A Dsi_cp_dma.c148 si_emit_cp_dma(sctx, sctx->gfx_cs, 0, 0, 0, CP_DMA_SYNC, L2_BYPASS);
177 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
181 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
295 si_emit_cp_dma(sctx, sctx->gfx_cs, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags,
378 si_emit_cp_dma(sctx, sctx->gfx_cs, main_dst_offset, main_src_offset,
394 si_emit_cp_dma(sctx, sctx->gfx_cs, dst_offset, src_offset, skipped_size,
558 si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 0, 4, 0xabcdef01, 0, SI_COHERENCY_SHADER, L2_BYPASS);
559 si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 4, 4, 0x23456789, 0, SI_COHERENCY_SHADER, L2_BYPASS);
560 si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, src, 8, 4, 0x87654321, 0, SI_COHERENCY_SHADER, L2_BYPASS);
561 si_cp_dma_clear_buffer(sctx, sctx->gfx_cs, sr
[all...]
H A Dsi_build_pm4.h123 struct radeon_cmdbuf *cs = sctx->gfx_cs;
144 struct radeon_cmdbuf *cs = sctx->gfx_cs;
166 struct radeon_cmdbuf *cs = sctx->gfx_cs;
192 struct radeon_cmdbuf *cs = sctx->gfx_cs;
220 struct radeon_cmdbuf *cs = sctx->gfx_cs;
H A Dsi_fence.c75 struct radeon_cmdbuf *cs = ctx->gfx_cs;
105 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, scratch,
134 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, scratch,
147 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, buf, RADEON_USAGE_WRITE,
182 ws->cs_add_fence_dependency(sctx->gfx_cs, fence);
188 sctx->ws->cs_add_syncobj_signal(sctx->gfx_cs, fence);
270 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf,
516 if (!radeon_emitted(sctx->gfx_cs, sctx->initial_gfx_cs_size)) {
520 ws->cs_sync_flush(sctx->gfx_cs);
531 gfx_fence = sctx->ws->cs_get_next_fence(sctx->gfx_cs);
[all...]
H A Dsi_state_binning.c313 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
323 if (initial_cdw != sctx->gfx_cs->current.cdw)
427 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
445 if (initial_cdw != sctx->gfx_cs->current.cdw)
H A Dsi_compute.c322 struct radeon_cmdbuf *cs = sctx->gfx_cs;
415 struct radeon_cmdbuf *cs = sctx->gfx_cs;
465 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
489 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
523 struct radeon_cmdbuf *cs = sctx->gfx_cs;
568 struct radeon_cmdbuf *cs = sctx->gfx_cs;
617 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
657 struct radeon_cmdbuf *cs = sctx->gfx_cs;
700 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
721 struct radeon_cmdbuf *cs = sctx->gfx_cs;
[all...]
H A Dsi_dma_cs.c144 radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
146 ws->cs_is_buffer_referenced(ctx->gfx_cs, dst->buf,
149 ws->cs_is_buffer_referenced(ctx->gfx_cs, src->buf,
H A Dsi_pm4.c126 struct radeon_cmdbuf *cs = sctx->gfx_cs;
129 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->bo[i],
138 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, ib,
H A Dsi_gfx_cs.c34 struct radeon_cmdbuf *cs = ctx->gfx_cs;
47 if (unlikely(!radeon_cs_memory_below_limit(ctx->screen, ctx->gfx_cs,
74 struct radeon_cmdbuf *cs = ctx->gfx_cs;
220 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, ctx->current_saved_cs->trace_buf,
249 ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
335 assert(!ctx->gfx_cs->prev_dw);
336 ctx->initial_gfx_cs_size = ctx->gfx_cs->current.cdw;
H A Dsi_state_viewport.c270 unsigned initial_cdw = ctx->gfx_cs->current.cdw;
284 if (initial_cdw != ctx->gfx_cs->current.cdw)
290 struct radeon_cmdbuf *cs = ctx->gfx_cs;
392 struct radeon_cmdbuf *cs = ctx->gfx_cs;
404 struct radeon_cmdbuf *cs = ctx->gfx_cs;
437 struct radeon_cmdbuf *cs = ctx->gfx_cs;
528 struct radeon_cmdbuf *cs = sctx->gfx_cs;
H A Dsi_state_draw.c73 struct radeon_cmdbuf *cs = sctx->gfx_cs;
545 struct radeon_cmdbuf *cs = sctx->gfx_cs;
582 struct radeon_cmdbuf *cs = sctx->gfx_cs;
616 struct radeon_cmdbuf *cs = sctx->gfx_cs;
672 struct radeon_cmdbuf *cs = sctx->gfx_cs;
732 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
755 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
789 sctx, sctx->gfx_cs, params_buf,
870 struct radeon_cmdbuf *cs = sctx->gfx_cs;
898 struct radeon_cmdbuf *cs = sctx->gfx_cs;
[all...]
H A Dsi_buffer.c36 if (sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs, buf, usage)) {
64 if (radeon_emitted(sctx->gfx_cs, sctx->initial_gfx_cs_size) &&
65 sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs,
93 sctx->ws->cs_sync_flush(sctx->gfx_cs);
788 if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
789 ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs,
800 ctx->ws->cs_sync_flush(ctx->gfx_cs);

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