Searched refs:gpu_address (Results 1 - 25 of 75) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_cp_reg_shadowing.c34 uint64_t gpu_address = shadow_regs->gpu_address; local in function:si_build_load_reg
43 gpu_address += SI_SHADOWED_UCONFIG_REG_OFFSET;
48 gpu_address += SI_SHADOWED_CONTEXT_REG_OFFSET;
53 gpu_address += SI_SHADOWED_SH_REG_OFFSET;
60 si_pm4_cmd_add(pm4, gpu_address);
61 si_pm4_cmd_add(pm4, gpu_address >> 32);
H A Dsi_cp_dma.c194 uint64_t va = (sdst ? sdst->gpu_address : 0) + offset;
270 va = sctx->scratch_buffer->gpu_address;
302 dst_offset += si_resource(dst)->gpu_address;
305 src_offset += si_resource(src)->gpu_address;
395 uint64_t address = si_resource(buf)->gpu_address + offset;
491 uint64_t va = buf->gpu_address + offset;
514 uint64_t dst_va = (dst ? dst->gpu_address : 0ull) + dst_offset;
515 uint64_t src_va = (src ? src->gpu_address : 0ull) + src_offset;
H A Dsi_state_streamout.c240 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
265 uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
331 uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
380 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
H A Dsi_buffer.c182 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
185 uint64_t start = res->gpu_address;
202 res->gpu_address, res->gpu_address + res->buf->size, res->buf->size);
286 sdst->gpu_address = ssrc->gpu_address;
649 buf->gpu_address = ws->buffer_get_virtual_address(buf->buf);
667 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
H A Dsi_compute.c316 uint64_t base_address = program->shader.bo->gpu_address;
359 va = si_resource(resources[i])->gpu_address;
390 uint64_t bc_va = sctx->border_color_buffer->gpu_address;
411 uint64_t bc_va = sctx->border_color_buffer->gpu_address;
464 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
530 shader_va = shader->bo->gpu_address + offset;
572 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
660 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
706 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
824 uint64_t base_va = si_resource(info->indirect)->gpu_address;
[all...]
H A Dsi_fence.c97 radeon_emit(scratch->gpu_address);
98 radeon_emit(scratch->gpu_address >> 32);
116 uint64_t va = scratch->gpu_address;
255 uint64_t fence_va = fine->buf->gpu_address + fine->offset;
H A Dsi_sdma_copy_image.c116 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset;
117 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset;
229 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.legacy.level[0].offset_256B * 256;
230 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.legacy.level[0].offset_256B * 256;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Devergreen_hw_context.c49 dst_offset += rdst->gpu_address;
50 src_offset += rsrc->gpu_address;
99 offset += r600_resource(dst)->gpu_address;
H A Dr600_buffer_common.c210 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
212 res->gpu_address = 0;
221 res->gpu_address, res->gpu_address + res->buf->size,
276 uint64_t old_gpu_address = rdst->gpu_address;
279 rdst->gpu_address = rsrc->gpu_address;
658 rbuffer->gpu_address =
661 rbuffer->gpu_address = 0;
H A Dr600_streamout.c196 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
221 uint64_t va = t[i]->buf_filled_size->gpu_address +
267 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
H A Dr600_uvd.c125 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Devergreen_hw_context.c49 dst_offset += rdst->gpu_address;
50 src_offset += rsrc->gpu_address;
99 offset += r600_resource(dst)->gpu_address;
H A Dr600_buffer_common.c209 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
211 res->gpu_address = 0;
220 res->gpu_address, res->gpu_address + res->buf->size,
274 uint64_t old_gpu_address = rdst->gpu_address;
277 rdst->gpu_address = rsrc->gpu_address;
660 rbuffer->gpu_address =
663 rbuffer->gpu_address = 0;
H A Dr600_streamout.c196 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
221 uint64_t va = t[i]->buf_filled_size->gpu_address +
267 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
H A Dr600_uvd.c128 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_cp_dma.c216 uint64_t va = (sdst ? sdst->gpu_address : 0) + offset;
294 va = sctx->scratch_buffer->gpu_address;
330 dst_offset += si_resource(dst)->gpu_address;
333 src_offset += si_resource(src)->gpu_address;
599 uint64_t va = buf->gpu_address + offset;
625 uint64_t dst_va = (dst ? dst->gpu_address : 0ull) + dst_offset;
626 uint64_t src_va = (src ? src->gpu_address : 0ull) + src_offset;
H A Dsi_dma.c49 dst_offset += sdst->gpu_address;
50 src_offset += ssrc->gpu_address;
148 base += tiled->buffer.gpu_address;
149 addr += linear->buffer.gpu_address;
H A Dsi_descriptors.c164 desc->gpu_address = si_desc_extract_buffer_address(descriptor);
176 desc->gpu_address = 0;
189 desc->gpu_address = desc->buffer->gpu_address + buffer_offset;
192 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
193 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
296 uint64_t va = buf->gpu_address + offset;
327 va = tex->buffer.gpu_address;
355 meta_va = (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
365 meta_va = tex->buffer.gpu_address
[all...]
H A Dsi_compute.c312 va = si_resource(resources[i])->gpu_address;
354 bc_va = sctx->border_color_buffer->gpu_address;
395 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
482 shader_va = shader->bo->gpu_address + offset;
524 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
620 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
680 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
829 uint64_t base_va = si_resource(info->indirect)->gpu_address;
H A Dsi_dma_cs.c43 uint64_t va = dst->gpu_address + offset;
88 offset += sdst->gpu_address;
H A Dsi_pm4.c143 radeon_emit(cs, ib->gpu_address);
144 radeon_emit(cs, ib->gpu_address >> 32);
H A Dsi_buffer.c222 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
225 uint64_t start = res->gpu_address;
242 res->gpu_address, res->gpu_address + res->buf->size,
310 sdst->gpu_address = ssrc->gpu_address;
756 buf->gpu_address = ws->buffer_get_virtual_address(buf->buf);
H A Dcik_sdma.c47 dst_offset += sdst->gpu_address;
48 src_offset += ssrc->gpu_address;
110 uint64_t dst_address = sdst->buffer.gpu_address +
112 uint64_t src_address = ssrc->buffer.gpu_address +
H A Dsi_fence.c102 radeon_emit(cs, scratch->gpu_address);
103 radeon_emit(cs, scratch->gpu_address >> 32);
121 uint64_t va = scratch->gpu_address;
268 uint64_t fence_va = fine->buf->gpu_address + fine->offset;
H A Dsi_uvd.c97 resources[i]->buffer.gpu_address = ctx->ws->buffer_get_virtual_address(

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