Searched refs:logicOpEnable (Results 1 - 25 of 37) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dblend_jit.h38 bool logicOpEnable; member in struct:RENDER_TARGET_BLEND_COMPILE_STATE
112 if (!blendState.logicOpEnable)
117 if (!blendState.blendEnable && !blendState.logicOpEnable)
H A Dblend_jit.cpp733 if (state.blendState.logicOpEnable)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/
H A Dblend_jit.h38 bool logicOpEnable; member in struct:RENDER_TARGET_BLEND_COMPILE_STATE
112 if (!blendState.logicOpEnable)
117 if (!blendState.blendEnable && !blendState.logicOpEnable)
H A Dblend_jit.cpp735 if (state.blendState.logicOpEnable)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/
H A Dsvga_pipe_blend.c119 perRT[i].logicOpEnable = 0;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_meta_decompress.c179 .logicOpEnable = false,
H A Dradv_meta_resolve.c196 .logicOpEnable = false,
H A Dradv_meta_fast_clear.c297 .logicOpEnable = false,
H A Dradv_meta_clear.c288 .logicOpEnable = false,
602 .logicOpEnable = false,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/
H A Dzink_pipeline.c114 blend_state.logicOpEnable = state->blend_state->logicop_enable;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/
H A Dswr_state.cpp102 compileState.logicOpEnable = state->pipe.logicop_enable;
103 if (compileState.logicOpEnable) {
1675 if (compileState.blendState.logicOpEnable &&
1677 compileState.blendState.logicOpEnable = false;
1684 compileState.blendState.logicOpEnable == false &&
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/
H A Dswr_state.cpp113 compileState.logicOpEnable = state->pipe.logicop_enable;
114 if (compileState.logicOpEnable) {
1953 if (compileState.blendState.logicOpEnable &&
1955 compileState.blendState.logicOpEnable = false;
1962 compileState.blendState.logicOpEnable == false &&
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/include/
H A Dsvga3d_dx.h1147 uint8 logicOpEnable; member in struct:SVGA3dDXBlendStatePerRT
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
H A Dsvga_pipe_blend.c163 perRT[i].logicOpEnable = bs->logicop_enabled;
/xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/
H A Dv3dv_meta_clear.c633 .logicOpEnable = false,
692 .logicOpEnable = false,
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/lavapipe/
H A Dlvp_pipeline.c211 dst->logicOpEnable = src->logicOpEnable;
/xsrc/external/mit/MesaLib/dist/src/virtio/venus-protocol/
H A Dvn_protocol_driver_pipeline.h944 size += vn_sizeof_VkBool32(&val->logicOpEnable);
983 vn_encode_VkBool32(enc, &val->logicOpEnable);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_meta_decompress.c321 .logicOpEnable = false,
H A Dradv_meta_fast_clear.c281 .logicOpEnable = false,
H A Dradv_meta_resolve.c219 .logicOpEnable = false,
H A Dradv_meta_clear.c287 .logicOpEnable = false,
623 .logicOpEnable = false,
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/
H A Dhelpers.cpp739 color_blend_state.logicOpEnable = false;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/include/
H A Dsvga3d_dx.h1188 uint8 logicOpEnable; member in struct:SVGA3dDXBlendStatePerRT
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/svga/svgadump/
H A Dsvga_dump.c1803 _debug_printf("\t\t.perRT[%u].logicOpEnable = %u\n", i, rt->logicOpEnable);
1804 if (rt->logicOpEnable) {
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/svgadump/
H A Dsvga_dump.c1803 _debug_printf("\t\t.perRT[%u].logicOpEnable = %u\n", i, rt->logicOpEnable);
1804 if (rt->logicOpEnable) {

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