Searched refs:num_sf_outputs (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_3d.c333 int num_sf_outputs,
337 OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
362 int num_sf_outputs,
366 OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
332 gen6_upload_sf_state(intel_screen_private * intel,int num_sf_outputs,int read_offset) argument
361 gen7_upload_sf_state(intel_screen_private * intel,int num_sf_outputs,int read_offset) argument
H A Dintel_uxa.h174 void gen6_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset);
175 void gen7_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset);
H A Di965_render.c2322 intel->gen6_render_state.num_sf_outputs = 0;
2651 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen6_composite_sf_state
2653 if (intel->gen6_render_state.num_sf_outputs == num_sf_outputs)
2656 intel->gen6_render_state.num_sf_outputs = num_sf_outputs;
2659 gen7_upload_sf_state(intel, num_sf_outputs, 1);
2661 gen6_upload_sf_state(intel, num_sf_outputs, 1);
2670 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen6_composite_wm_state
2688 OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIF
[all...]
H A Dintel.h246 int num_sf_outputs; member in struct:intel_screen_private::__anon0a8ca5a70308
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_3d.c333 int num_sf_outputs,
337 OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
362 int num_sf_outputs,
366 OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
332 gen6_upload_sf_state(intel_screen_private * intel,int num_sf_outputs,int read_offset) argument
361 gen7_upload_sf_state(intel_screen_private * intel,int num_sf_outputs,int read_offset) argument
H A Dintel_uxa.h174 void gen6_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset);
175 void gen7_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset);
H A Di965_render.c2322 intel->gen6_render_state.num_sf_outputs = 0;
2651 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen6_composite_sf_state
2653 if (intel->gen6_render_state.num_sf_outputs == num_sf_outputs)
2656 intel->gen6_render_state.num_sf_outputs = num_sf_outputs;
2659 gen7_upload_sf_state(intel, num_sf_outputs, 1);
2661 gen6_upload_sf_state(intel, num_sf_outputs, 1);
2670 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen6_composite_wm_state
2688 OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIF
[all...]
H A Dintel.h244 int num_sf_outputs; member in struct:intel_screen_private::__anonb9af6fdb0308
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_render.h470 uint16_t num_sf_outputs; member in struct:gen6_render_state
527 uint16_t num_sf_outputs; member in struct:gen7_render_state
586 uint16_t num_sf_outputs; member in struct:gen8_render_state
646 uint16_t num_sf_outputs; member in struct:gen9_render_state
H A Dgen6_render.c668 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen6_emit_sf
670 if (sna->render_state.gen6.num_sf_outputs == num_sf_outputs)
673 DBG(("%s: num_sf_outputs=%d, read_length=%d, read_offset=%d\n",
674 __FUNCTION__, num_sf_outputs, 1, 0));
676 sna->render_state.gen6.num_sf_outputs = num_sf_outputs;
679 OUT_BATCH(num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT |
3642 sna->render_state.gen6.num_sf_outputs = 0;
H A Dgen7_render.c879 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen7_emit_sf
881 if (sna->render_state.gen7.num_sf_outputs == num_sf_outputs)
884 DBG(("%s: num_sf_outputs=%d, read_length=%d, read_offset=%d\n",
885 __FUNCTION__, num_sf_outputs, 1, 0));
887 sna->render_state.gen7.num_sf_outputs = num_sf_outputs;
890 OUT_BATCH(num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT |
3855 sna->render_state.gen7.num_sf_outputs = 0;
H A Dgen8_render.c988 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen8_emit_sf
990 if (sna->render_state.gen8.num_sf_outputs == num_sf_outputs)
993 DBG(("%s: num_sf_outputs=%d\n", __FUNCTION__, num_sf_outputs));
995 sna->render_state.gen8.num_sf_outputs = num_sf_outputs;
998 OUT_BATCH(num_sf_outputs << SBE_NUM_OUTPUTS_SHIFT |
3990 sna->render_state.gen8.num_sf_outputs = 0;
H A Dgen9_render.c1050 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen9_emit_sf
1052 if (sna->render_state.gen9.num_sf_outputs == num_sf_outputs)
1055 DBG(("%s: num_sf_outputs=%d\n", __FUNCTION__, num_sf_outputs));
1057 sna->render_state.gen9.num_sf_outputs = num_sf_outputs;
1060 OUT_BATCH(num_sf_outputs << SBE_NUM_OUTPUTS_SHIFT |
4083 sna->render_state.gen9.num_sf_outputs = 0;
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_render.h456 uint16_t num_sf_outputs; member in struct:gen6_render_state
506 uint16_t num_sf_outputs; member in struct:gen7_render_state
558 uint16_t num_sf_outputs; member in struct:gen8_render_state
H A Dgen6_render.c634 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen6_emit_sf
636 if (sna->render_state.gen6.num_sf_outputs == num_sf_outputs)
639 DBG(("%s: num_sf_outputs=%d, read_length=%d, read_offset=%d\n",
640 __FUNCTION__, num_sf_outputs, 1, 0));
642 sna->render_state.gen6.num_sf_outputs = num_sf_outputs;
645 OUT_BATCH(num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT |
3561 sna->render_state.gen6.num_sf_outputs = 0;
H A Dgen7_render.c842 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen7_emit_sf
844 if (sna->render_state.gen7.num_sf_outputs == num_sf_outputs)
847 DBG(("%s: num_sf_outputs=%d, read_length=%d, read_offset=%d\n",
848 __FUNCTION__, num_sf_outputs, 1, 0));
850 sna->render_state.gen7.num_sf_outputs = num_sf_outputs;
853 OUT_BATCH(num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT |
3762 sna->render_state.gen7.num_sf_outputs = 0;
H A Dgen8_render.c922 int num_sf_outputs = has_mask ? 2 : 1; local in function:gen8_emit_sf
924 if (sna->render_state.gen8.num_sf_outputs == num_sf_outputs)
927 DBG(("%s: num_sf_outputs=%d\n", __FUNCTION__, num_sf_outputs));
929 sna->render_state.gen8.num_sf_outputs = num_sf_outputs;
932 OUT_BATCH(num_sf_outputs << SBE_NUM_OUTPUTS_SHIFT |
3863 sna->render_state.gen8.num_sf_outputs = 0;

Completed in 48 milliseconds