Searched refs:opcode (Results 1 - 25 of 651) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/
H A Dtgsi_info.c39 { .opcode = TGSI_OPCODE_ ## name, \
43 #define OPCODE_GAP(opc) { .opcode = opc },
54 tgsi_get_opcode_info(enum tgsi_opcode opcode) argument
58 ASSERT_BITFIELD_SIZE(struct tgsi_opcode_info, opcode, TGSI_OPCODE_LAST - 1);
66 assert(opcode_info[i].opcode == i);
69 if (opcode < TGSI_OPCODE_LAST)
70 return &opcode_info[opcode];
88 tgsi_get_opcode_name(enum tgsi_opcode opcode) argument
90 if (opcode >= ARRAY_SIZE(opcode_names))
92 return opcode_names[opcode];
123 tgsi_opcode_infer_type(enum tgsi_opcode opcode) argument
251 tgsi_opcode_infer_src_type(enum tgsi_opcode opcode,uint src_idx) argument
336 tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode,uint dst_idx) argument
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H A Dtgsi_info.h39 /* This enum describes how an opcode calculates its result. */
41 /** The opcode produces no result. */
44 /** When this opcode writes to a channel of the destination register,
52 /** This opcode writes the same value to all enabled channels of the
59 /** The operation performed by this opcode is dependent on which channel
82 enum tgsi_opcode opcode:10;
86 tgsi_get_opcode_info(enum tgsi_opcode opcode);
89 tgsi_get_opcode_name(enum tgsi_opcode opcode);
114 tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint src_idx);
117 tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode, uin
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/exts/
H A Dformatting.py20 opcode, desc = sig.split("-", 1)
21 opcode = opcode.strip().upper()
23 signode += sphinx.addnodes.desc_name(opcode, opcode)
25 return opcode
30 app.add_description_unit("opcode", "opcode", "%s (TGSI opcode)",
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/d3d10umd/
H A DShaderParse.c55 #define OP_SATURATE (1 << 1) /* saturate in opcode specific control */
56 #define OP_TEST_BOOLEAN (1 << 2) /* test boolean in opcode specific control */
57 #define OP_DCL (1 << 3) /* custom opcode specific control */
286 struct Shader_opcode *opcode)
298 memset(opcode, 0, sizeof *opcode);
301 opcode->type = DECODE_D3D10_SB_OPCODE_TYPE(*curr);
303 if (opcode->type == D3D10_SB_OPCODE_CUSTOMDATA) {
304 opcode->customdata._class = DECODE_D3D10_SB_CUSTOMDATA_CLASS(*curr);
307 assert(opcode
285 Shader_parse_opcode(struct Shader_parser * parser,struct Shader_opcode * opcode) argument
603 Shader_opcode_free(struct Shader_opcode * opcode) argument
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H A DShaderTGSI.c60 /* Opcodes which do not translate directly to a TGSI opcode, but which
1168 struct Shader_opcode *opcode,
1177 if (opcode->imm_texel_offset.u ||
1178 opcode->imm_texel_offset.v ||
1179 opcode->imm_texel_offset.w) {
1184 opcode->imm_texel_offset.u,
1185 opcode->imm_texel_offset.v,
1186 opcode->imm_texel_offset.w);
1207 struct Shader_xlate *sx, struct Shader_opcode *opcode)
1210 struct ureg_dst dst = translate_dst_operand(sx, &opcode
1165 sample_ureg_emit(struct ureg_program * ureg,unsigned tgsi_opcode,unsigned num_src,struct Shader_opcode * opcode,struct ureg_dst dst,struct ureg_src * src) argument
1206 expand_unary_to_scalarf(struct ureg_program * ureg,unary_ureg_func func,struct Shader_xlate * sx,struct Shader_opcode * opcode) argument
1247 struct Shader_opcode opcode; local in function:Shader_tgsi_translate
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/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dintel_disasm.c32 is_send(uint32_t opcode) argument
34 return (opcode == BRW_OPCODE_SEND ||
35 opcode == BRW_OPCODE_SENDC ||
36 opcode == BRW_OPCODE_SENDS ||
37 opcode == BRW_OPCODE_SENDSC );
46 /* This loop exits when send-with-EOT or when opcode is 0 */
57 uint32_t opcode = brw_inst_opcode(devinfo, insn); local in function:intel_disasm_find_end
58 if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) {
/xsrc/external/mit/MesaLib.old/dist/src/mesa/program/
H A Dprog_instruction.c157 * Return the number of src registers for the given instruction/opcode.
160 _mesa_num_inst_src_regs(enum prog_opcode opcode) argument
162 assert(opcode < MAX_OPCODE);
163 assert(opcode == InstInfo[opcode].Opcode);
165 return InstInfo[opcode].NumSrcRegs;
170 * Return the number of dst registers for the given instruction/opcode.
173 _mesa_num_inst_dst_regs(enum prog_opcode opcode) argument
175 assert(opcode < MAX_OPCODE);
176 assert(opcode
183 _mesa_is_tex_instruction(enum prog_opcode opcode) argument
247 _mesa_opcode_string(enum prog_opcode opcode) argument
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/tgsi/
H A Dtgsi_info.c39 { .opcode = TGSI_OPCODE_ ## name, \
43 #define OPCODE_GAP(opc) { .opcode = opc },
54 tgsi_get_opcode_info(enum tgsi_opcode opcode) argument
58 ASSERT_BITFIELD_SIZE(struct tgsi_opcode_info, opcode, TGSI_OPCODE_LAST - 1);
66 assert(opcode_info[i].opcode == i);
69 if (opcode < TGSI_OPCODE_LAST)
70 return &opcode_info[opcode];
88 tgsi_get_opcode_name(enum tgsi_opcode opcode) argument
90 if (opcode >= ARRAY_SIZE(opcode_names))
92 return opcode_names[opcode];
123 tgsi_opcode_infer_type(enum tgsi_opcode opcode) argument
251 tgsi_opcode_infer_src_type(enum tgsi_opcode opcode,uint src_idx) argument
323 tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode,uint dst_idx) argument
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H A Dtgsi_info.h39 /* This enum describes how an opcode calculates its result. */
41 /** The opcode produces no result. */
44 /** When this opcode writes to a channel of the destination register,
52 /** This opcode writes the same value to all enabled channels of the
59 /** The operation performed by this opcode is dependent on which channel
82 enum tgsi_opcode opcode:10;
86 tgsi_get_opcode_info(enum tgsi_opcode opcode);
89 tgsi_get_opcode_name(enum tgsi_opcode opcode);
114 tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint src_idx);
117 tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode, uin
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/xsrc/external/mit/MesaLib/dist/src/mesa/program/
H A Dprog_instruction.c159 * Return the number of src registers for the given instruction/opcode.
162 _mesa_num_inst_src_regs(enum prog_opcode opcode) argument
164 assert(opcode < MAX_OPCODE);
165 assert(opcode == InstInfo[opcode].Opcode);
167 return InstInfo[opcode].NumSrcRegs;
172 * Return the number of dst registers for the given instruction/opcode.
175 _mesa_num_inst_dst_regs(enum prog_opcode opcode) argument
177 assert(opcode < MAX_OPCODE);
178 assert(opcode
185 _mesa_is_tex_instruction(enum prog_opcode opcode) argument
249 _mesa_opcode_string(enum prog_opcode opcode) argument
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_debug_fp.c242 print_arith_op(GLuint opcode, const GLuint * program) argument
244 if (opcode != A0_NOP) {
252 printf("%s ", opcodes[opcode]);
255 if (args[opcode] == 1) {
262 if (args[opcode] == 2) {
275 print_tex_op(GLuint opcode, const GLuint * program) argument
280 printf("%s ", opcodes[opcode]);
291 print_dcl_op(GLuint opcode, const GLuint * program) argument
293 printf("%s ", opcodes[opcode]);
310 GLuint opcode local in function:i915_disassemble_program
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_debug_fp.c245 print_arith_op(GLuint opcode, const GLuint * program) argument
247 if (opcode != A0_NOP) {
255 printf("%s ", opcodes[opcode]);
258 if (args[opcode] == 1) {
265 if (args[opcode] == 2) {
278 print_tex_op(GLuint opcode, const GLuint * program) argument
283 printf("%s ", opcodes[opcode]);
294 print_dcl_op(GLuint opcode, const GLuint * program) argument
296 printf("%s ", opcodes[opcode]);
313 GLuint opcode local in function:i915_disassemble_program
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/xsrc/external/mit/xmodmap/dist/
H A Dwq.h38 enum opcode { doKeycode, doAddModifier, doRemoveModifier, doClearModifier, enum
42 enum opcode type; /* oneof enum opcode */
56 enum opcode type; /* doKeycode */
69 enum opcode type; /* doAddModifier */
85 enum opcode type; /* doRemoveModifier */
98 enum opcode type; /* doClearModifier */
112 enum opcode type; /* doPointer */
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/rbug/
H A Drbug_proto.h76 enum rbug_opcode opcode; member in struct:rbug_header
85 int32_t opcode; member in struct:rbug_proto_header
95 * Get printable string for opcode.
97 const char* rbug_proto_get_name(enum rbug_opcode opcode);
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/rbug/
H A Drbug_proto.h76 enum rbug_opcode opcode; member in struct:rbug_header
85 int32_t opcode; member in struct:rbug_proto_header
95 * Get printable string for opcode.
97 const char* rbug_proto_get_name(enum rbug_opcode opcode);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_swizzle.h44 * can be implemented natively by the hardware for this opcode.
46 * \return 1 if the swizzle is native for the given opcode
48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
H A Dradeon_opcodes.h273 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode) argument
275 assert((unsigned int)opcode < MAX_RC_OPCODE);
276 assert(rc_opcodes[opcode].Opcode == opcode);
278 return &rc_opcodes[opcode];
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_swizzle.h44 * can be implemented natively by the hardware for this opcode.
46 * \return 1 if the swizzle is native for the given opcode
48 int (*IsNative)(rc_opcode opcode, struct rc_src_register reg);
/xsrc/external/mit/MesaLib.old/dist/src/intel/common/
H A Dgen_disasm.c36 is_send(uint32_t opcode) argument
38 return (opcode == BRW_OPCODE_SEND ||
39 opcode == BRW_OPCODE_SENDC ||
40 opcode == BRW_OPCODE_SENDS ||
41 opcode == BRW_OPCODE_SENDSC );
51 /* This loop exits when send-with-EOT or when opcode is 0 */
62 uint32_t opcode = brw_inst_opcode(devinfo, insn); local in function:gen_disasm_find_end
63 if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) {
/xsrc/external/mit/MesaLib/dist/docs/_exts/
H A Dformatting.py22 opcode, desc = sig.split("-", 1)
23 opcode = opcode.strip().upper()
25 signode += sphinx.addnodes.desc_name(opcode, opcode)
27 return opcode
32 app.add_object_type("opcode", "opcode", "%s (TGSI opcode)",
/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_lower_bool_to_bitsize.c150 nir_op opcode = alu->op; local in function:lower_alu_instr
151 switch (opcode) {
167 opcode = bit_size == 8 ? nir_op_f2b8 :
172 opcode = bit_size == 8 ? nir_op_i2b8 :
178 opcode = nir_op_mov;
183 opcode = nir_op_i2i32;
187 opcode = bit_size == 8 ? nir_op_flt8 :
192 opcode = bit_size == 8 ? nir_op_fge8 :
197 opcode = bit_size == 8 ? nir_op_feq8 :
202 opcode
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_debug_fp.c258 unsigned opcode, const unsigned * program)
260 if (opcode != A0_NOP) {
268 PRINTF(stream, "%s ", opcodes[opcode]);
271 if (args[opcode] == 1) {
278 if (args[opcode] == 2) {
292 unsigned opcode, const unsigned * program)
297 PRINTF(stream, "%s ", opcodes[opcode]);
310 unsigned opcode, const unsigned * program)
323 unsigned opcode, const unsigned * program)
325 PRINTF(stream, "%s ", opcodes[opcode]);
257 print_arith_op(struct debug_stream * stream,unsigned opcode,const unsigned * program) argument
291 print_tex_op(struct debug_stream * stream,unsigned opcode,const unsigned * program) argument
309 print_texkil_op(struct debug_stream * stream,unsigned opcode,const unsigned * program) argument
322 print_dcl_op(struct debug_stream * stream,unsigned opcode,const unsigned * program) argument
343 unsigned opcode = program[0] & (0x1f << 24); local in function:i915_disassemble_program
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_debug_fp.c192 print_arith_op(char **stream, unsigned opcode, const unsigned *program) argument
194 if (opcode != A0_NOP) {
202 PRINTF(stream, "%s ", opcodes[opcode]);
205 if (args[opcode] == 1)
210 if (args[opcode] == 2)
219 print_tex_op(char **stream, unsigned opcode, const unsigned *program) argument
224 PRINTF(stream, "%s ", opcodes[opcode]);
234 print_texkil_op(char **stream, unsigned opcode, const unsigned *program) argument
244 print_dcl_op(char **stream, unsigned opcode, const unsigned *program) argument
248 PRINTF(stream, "%s ", opcodes[opcode]);
284 unsigned opcode = program[0] & (0x1f << 24); local in function:i915_disassemble_program
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/xsrc/external/mit/MesaLib.old/dist/src/glx/
H A Dpackrender.h76 #define __GLX_BEGIN_VARIABLE(opcode,size) \
81 __GLX_PUT_SHORT(2,opcode)
83 #define __GLX_BEGIN_VARIABLE_LARGE(opcode,size) \
86 __GLX_PUT_LONG(4,opcode)
88 #define __GLX_BEGIN_VARIABLE_WITH_PIXEL(opcode,size) \
93 __GLX_PUT_SHORT(2,opcode); \
98 #define __GLX_BEGIN_VARIABLE_LARGE_WITH_PIXEL(opcode,size) \
101 __GLX_PUT_LONG(4,opcode); \
106 #define __GLX_BEGIN_VARIABLE_WITH_PIXEL_3D(opcode,size) \
111 __GLX_PUT_SHORT(2,opcode); \
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/xsrc/external/mit/MesaLib/dist/src/glx/
H A Dpackrender.h76 #define __GLX_BEGIN_VARIABLE(opcode,size) \
81 __GLX_PUT_SHORT(2,opcode)
83 #define __GLX_BEGIN_VARIABLE_LARGE(opcode,size) \
86 __GLX_PUT_LONG(4,opcode)
88 #define __GLX_BEGIN_VARIABLE_WITH_PIXEL(opcode,size) \
93 __GLX_PUT_SHORT(2,opcode); \
98 #define __GLX_BEGIN_VARIABLE_LARGE_WITH_PIXEL(opcode,size) \
101 __GLX_PUT_LONG(4,opcode); \
106 #define __GLX_BEGIN_VARIABLE_WITH_PIXEL_3D(opcode,size) \
111 __GLX_PUT_SHORT(2,opcode); \
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