Searched refs:qpu (Results 1 - 25 of 38) sorted by relevance

12

/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dvir_opt_redundant_flags.c45 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
47 inst->qpu.flags.apf = V3D_QPU_PF_NONE;
48 inst->qpu.flags.mpf = V3D_QPU_PF_NONE;
80 if (a->qpu.flags.apf != b->qpu.flags.apf ||
81 a->qpu.flags.mpf != b->qpu.flags.mpf ||
82 a->qpu.alu.add.op != b->qpu.alu.add.op ||
83 a->qpu
[all...]
H A Dvir_to_qpu.c25 #include "qpu/qpu_instr.h"
26 #include "qpu/qpu_disasm.h"
137 if (qinst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
138 qinst->qpu.alu.mul.op != V3D_QPU_M_MOV ||
139 qinst->qpu.alu.add.op != V3D_QPU_A_NOP ||
140 memcmp(&qinst->qpu.sig, &no_sig, sizeof(no_sig)) != 0) {
145 enum v3d_qpu_waddr waddr = qinst->qpu.alu.mul.waddr;
146 if (qinst->qpu.alu.mul.magic_write) {
150 if (qinst->qpu.alu.mul.a !=
157 switch (qinst->qpu
339 struct v3d_qpu_instr qpu; local in function:reads_uniform
[all...]
H A Dvir_opt_copy_propagate.c43 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
44 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV &&
45 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) {
55 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
56 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
60 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
61 inst->qpu.flags.mc != V3D_QPU_COND_NONE) {
107 return inst->qpu.alu.add.a_unpack != V3D_QPU_UNPACK_NONE;
109 return inst->qpu.alu.add.b_unpack != V3D_QPU_UNPACK_NONE;
112 return inst->qpu
[all...]
H A Dvir_opt_dead_code.c50 assert(!v3d_qpu_writes_flags(&inst->qpu));
69 if (c->devinfo->ver >= 41 && v3d_qpu_uses_sfu(&inst->qpu))
85 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
87 inst->qpu.flags.apf = V3D_QPU_PF_NONE;
88 inst->qpu.flags.mpf = V3D_QPU_PF_NONE;
89 inst->qpu.flags.auf = V3D_QPU_UF_NONE;
90 inst->qpu.flags.muf = V3D_QPU_UF_NONE;
98 if (!inst->qpu.sig.ldunifa && !inst->qpu.sig.ldunifarf)
114 if (scan_inst->qpu
[all...]
H A Dvir_opt_constant_alu.c67 switch (inst->qpu.alu.add.op) {
74 assert(inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE);
105 if(inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU)
111 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
112 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
116 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
117 inst->qpu.flags.mc != V3D_QPU_COND_NONE) {
126 inst->qpu.raddr_b,
136 if ((def->qpu.sig.ldunif || def->qpu
[all...]
H A Dvir_opt_small_immediates.c41 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU)
63 if (!src_def || !src_def->qpu.sig.ldunif)
81 struct v3d_qpu_sig new_sig = inst->qpu.sig;
92 inst->qpu.sig.small_imm = true;
93 inst->qpu.raddr_b = packed;
H A Dqpu_schedule.c37 #include "qpu/qpu_disasm.h"
158 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
161 if (!n->inst->qpu.sig.small_imm) {
163 state->last_rf[n->inst->qpu.raddr_b], n);
282 struct v3d_qpu_instr *inst = &qinst->qpu;
526 const struct v3d_qpu_instr *inst = &qinst->qpu;
566 const struct v3d_qpu_instr *inst = &qinst->qpu;
1030 if (prev_inst->inst->qpu.sig.thrsw)
1040 const struct v3d_qpu_instr *inst = &n->inst->qpu;
1145 if ((prev_inst->inst->qpu
[all...]
H A Dvir.c33 switch (inst->qpu.type) {
37 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP)
38 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op);
40 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op);
53 switch (inst->qpu.type) {
57 switch (inst->qpu.alu.add.op) {
71 switch (inst->qpu.alu.mul.op) {
79 if (inst->qpu.sig.ldtmu ||
80 inst->qpu.sig.ldvary ||
81 inst->qpu
[all...]
H A Dvir_dump.c173 inst->qpu.raddr_b,
177 int8_t *p = (int8_t *)&inst->qpu.raddr_b;
218 struct v3d_qpu_sig *sig = &inst->qpu.sig;
224 vir_dump_sig_addr(c->devinfo, &inst->qpu);
230 vir_dump_sig_addr(c->devinfo, &inst->qpu);
234 vir_dump_sig_addr(c->devinfo, &inst->qpu);
238 vir_dump_sig_addr(c->devinfo, &inst->qpu);
244 vir_dump_sig_addr(c->devinfo, &inst->qpu);
250 vir_dump_sig_addr(c->devinfo, &inst->qpu);
259 struct v3d_qpu_instr *instr = &inst->qpu;
[all...]
H A Dvir_live_variables.c94 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU)
114 if ((inst->qpu.flags.ac == V3D_QPU_COND_NONE &&
115 inst->qpu.flags.mc == V3D_QPU_COND_NONE) &&
116 inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE &&
117 inst->qpu.alu.mul.output_pack == V3D_QPU_PACK_NONE) {
134 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
135 inst->qpu.flags.mc != V3D_QPU_COND_NONE) {
172 if (inst->qpu.flags.apf != V3D_QPU_PF_NONE ||
173 inst->qpu.flags.mpf != V3D_QPU_PF_NONE) {
177 if (inst->qpu
[all...]
H A Dvir_register_allocate.c42 inst->qpu.sig.wrtmuc;
49 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
50 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
54 if (!inst->qpu.sig.ldtmu)
59 if (scan_inst->qpu.sig.ldtmu)
62 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
63 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
79 return def && def->qpu.sig.ldunif;
142 if (inst->qpu.sig.ldvary) {
150 if (v3d_qpu_writes_vpm(&inst->qpu) ||
[all...]
H A Dqpu_validate.c35 #include "qpu/qpu_disasm.h"
65 v3d_qpu_dump(c->devinfo, &inst->qpu);
113 const struct v3d_qpu_instr *inst = &qinst->qpu;
299 state->last = &qinst->qpu;
H A Dv3d_compiler.h42 #include "qpu/qpu_instr.h"
160 struct v3d_qpu_instr qpu; member in struct:qinst
1378 ldtmu->qpu.sig.ldtmu = true;
1382 vir_NOP(c)->qpu.sig.ldtmu = true;
1402 ldtlb->qpu.sig.ldtlbu = true;
1414 ldtlb->qpu.sig.ldtlb = true;
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dvir_opt_redundant_flags.c45 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
47 inst->qpu.flags.apf = V3D_QPU_PF_NONE;
48 inst->qpu.flags.mpf = V3D_QPU_PF_NONE;
80 if (a->qpu.flags.apf != b->qpu.flags.apf ||
81 a->qpu.flags.mpf != b->qpu.flags.mpf ||
82 a->qpu.alu.add.op != b->qpu.alu.add.op ||
83 a->qpu
[all...]
H A Dvir_to_qpu.c25 #include "qpu/qpu_instr.h"
26 #include "qpu/qpu_disasm.h"
143 if (qinst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
144 qinst->qpu.alu.mul.op != V3D_QPU_M_MOV ||
145 qinst->qpu.alu.add.op != V3D_QPU_A_NOP ||
146 memcmp(&qinst->qpu.sig, &no_sig, sizeof(no_sig)) != 0) {
151 enum v3d_qpu_waddr waddr = qinst->qpu.alu.mul.waddr;
152 if (qinst->qpu.alu.mul.magic_write) {
156 if (qinst->qpu.alu.mul.a !=
163 switch (qinst->qpu
335 struct v3d_qpu_instr qpu; local in function:reads_uniform
[all...]
H A Dvir_opt_copy_propagate.c43 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
44 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV &&
45 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) {
55 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE ||
56 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) {
60 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE ||
61 inst->qpu.flags.mc != V3D_QPU_COND_NONE) {
107 return inst->qpu.alu.add.a_unpack != V3D_QPU_UNPACK_NONE;
109 return inst->qpu.alu.add.b_unpack != V3D_QPU_UNPACK_NONE;
112 return inst->qpu
[all...]
H A Dvir_opt_dead_code.c50 assert(!v3d_qpu_writes_flags(&inst->qpu));
69 if (c->devinfo->ver >= 41 && v3d_qpu_uses_sfu(&inst->qpu))
85 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
87 inst->qpu.flags.apf = V3D_QPU_PF_NONE;
88 inst->qpu.flags.mpf = V3D_QPU_PF_NONE;
89 inst->qpu.flags.auf = V3D_QPU_UF_NONE;
90 inst->qpu.flags.muf = V3D_QPU_UF_NONE;
119 if (v3d_qpu_reads_flags(&inst->qpu))
131 if (v3d_qpu_writes_flags(&inst->qpu)) {
136 (inst->qpu
[all...]
H A Dvir_opt_small_immediates.c41 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU)
63 if (!src_def || !src_def->qpu.sig.ldunif)
81 struct v3d_qpu_sig new_sig = inst->qpu.sig;
92 inst->qpu.sig.small_imm = true;
93 inst->qpu.raddr_b = packed;
H A Dvir.c30 switch (inst->qpu.type) {
34 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP)
35 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op);
37 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op);
50 switch (inst->qpu.type) {
54 switch (inst->qpu.alu.add.op) {
68 switch (inst->qpu.alu.mul.op) {
76 if (inst->qpu.sig.ldtmu ||
77 inst->qpu.sig.ldvary ||
78 inst->qpu
[all...]
H A Dvir_dump.c167 inst->qpu.raddr_b,
171 if ((int)inst->qpu.raddr_b >= -16 &&
172 (int)inst->qpu.raddr_b <= 15)
211 struct v3d_qpu_sig *sig = &inst->qpu.sig;
217 vir_dump_sig_addr(c->devinfo, &inst->qpu);
223 vir_dump_sig_addr(c->devinfo, &inst->qpu);
227 vir_dump_sig_addr(c->devinfo, &inst->qpu);
231 vir_dump_sig_addr(c->devinfo, &inst->qpu);
237 vir_dump_sig_addr(c->devinfo, &inst->qpu);
243 vir_dump_sig_addr(c->devinfo, &inst->qpu);
[all...]
H A Dvir_live_variables.c98 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU)
122 if ((inst->qpu.flags.ac == V3D_QPU_COND_NONE &&
123 inst->qpu.flags.mc == V3D_QPU_COND_NONE) &&
124 inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE &&
125 inst->qpu.alu.mul.output_pack == V3D_QPU_PACK_NONE) {
152 if (inst->qpu.flags.ac == V3D_QPU_COND_NONE &&
153 inst->qpu.flags.mc == V3D_QPU_COND_NONE) {
182 (state->insts[i]->qpu.flags.ac != V3D_QPU_COND_NONE ||
183 state->insts[i]->qpu.flags.mc != V3D_QPU_COND_NONE))
H A Dqpu_schedule.c37 #include "qpu/qpu_disasm.h"
153 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
156 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_b], n);
245 struct v3d_qpu_instr *inst = &qinst->qpu;
468 const struct v3d_qpu_instr *inst = &qinst->qpu;
508 const struct v3d_qpu_instr *inst = &qinst->qpu;
705 if (prev_inst->inst->qpu.sig.thrsw)
711 const struct v3d_qpu_instr *inst = &n->inst->qpu;
780 &prev_inst->inst->qpu, inst)) {
857 v3d_qpu_dump(devinfo, &n->inst->qpu);
[all...]
H A Dvir_register_allocate.c48 if (scan_inst->qpu.sig.ldtmu)
62 return def && def->qpu.sig.ldunif;
123 if (inst->qpu.sig.ldvary) {
131 if (v3d_qpu_writes_vpm(&inst->qpu) ||
132 v3d_qpu_uses_tlb(&inst->qpu))
140 if (inst->qpu.sig.ldtmu &&
144 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
145 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT)
282 (v3d_qpu_writes_vpm(&inst->qpu) ||
283 v3d_qpu_uses_tlb(&inst->qpu))) {
[all...]
H A Dqpu_validate.c35 #include "qpu/qpu_disasm.h"
65 v3d_qpu_dump(c->devinfo, &inst->qpu);
113 const struct v3d_qpu_instr *inst = &qinst->qpu;
285 state->last = &qinst->qpu;
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/
H A DMakefile.sources46 qpu/qpu_disasm.c \
47 qpu/qpu_disasm.h \
48 qpu/qpu_instr.c \
49 qpu/qpu_instr.h \
50 qpu/qpu_pack.c \

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