Searched refs:spi_baryc_cntl (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_shader.h655 unsigned spi_baryc_cntl; member in struct:si_shader::__anon05df395d140a::__anon05df395d1708
H A Dsi_state_shaders.c1181 shader->ctx_reg.ps.spi_baryc_cntl);
1205 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); local in function:si_shader_ps
1277 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1281 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1307 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_shader.h868 unsigned spi_baryc_cntl; member in struct:si_shader::__anon396a2930160a::__anon396a29301a08
H A Dsi_state_shaders.c1597 shader->ctx_reg.ps.spi_baryc_cntl);
1616 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); local in function:si_shader_ps
1682 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1685 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1721 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.3.4.rst99 - radv: move spi_baryc_cntl to pipeline
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Devergreen_state.c3337 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0; local in function:evergreen_update_ps_state
3370 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3377 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3468 if (!spi_baryc_cntl)
3469 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3499 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_private.h1392 uint32_t spi_baryc_cntl; member in struct:radv_pipeline::__anone2cea0a71a0a::__anone2cea0a71b08
H A Dradv_pipeline.c1138 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
3376 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
3710 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Devergreen_state.c3331 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0; local in function:evergreen_update_ps_state
3364 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3455 if (!spi_baryc_cntl)
3456 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3486 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_pipeline.c1144 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
5086 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
5518 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
H A Dradv_private.h1798 uint32_t spi_baryc_cntl; member in struct:radv_pipeline::__anon4674665a290a::__anon4674665a2a08

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