| /xsrc/external/mit/xf86-video-r128/dist/src/ |
| r128_exa.c | 108 int has_src = info->state_2d.src_pitch_offset;
113 OUTREG(R128_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
114 OUTREG(R128_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
115 OUTREG(R128_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
116 OUTREG(R128_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
117 OUTREG(R128_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr);
118 OUTREG(R128_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr);
119 OUTREG(R128_DP_WRITE_MASK, info->state_2d.dp_write_mask);
120 OUTREG(R128_DP_CNTL, info->state_2d.dp_cntl);
122 OUTREG(R128_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset)
[all...] |
| r128_exa_render.c | 363 info->state_2d.widths[unit] = 1 << l2w;
364 info->state_2d.heights[unit] = 1 << l2h;
370 info->state_2d.is_transform[unit] = TRUE;
371 info->state_2d.transform[unit] = pPict->transform;
373 info->state_2d.is_transform[unit] = FALSE;
457 info->state_2d.has_mask = TRUE;
463 info->state_2d.has_mask = FALSE;
472 info->state_2d.has_mask = FALSE;
478 info->state_2d.has_mask = TRUE;
481 info->state_2d.has_mask = FALSE
[all...] |
| r128.h | 347 struct r128_2d_state state_2d; member in struct:__anon170
|
| r128_dri.c | 108 if (info->have3DWindows) info->state_2d.composite_setup = FALSE;
|
| r128_driver.c | 2941 info->state_2d.composite_setup = FALSE;
|
| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| radeon_exa_funcs.c | 63 if (info->state_2d.op == 0 && op == 0)
66 has_src = info->state_2d.src_pitch_offset || info->state_2d.src_bo;
73 OUT_RING_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
74 OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
75 OUT_RING_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
76 OUT_RING_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
77 OUT_RING_REG(RADEON_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr);
78 OUT_RING_REG(RADEON_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr);
79 OUT_RING_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask)
[all...] |
| radeon.h | 574 struct radeon_2d_state state_2d; member in struct:__anon6929
|
| radeon_kms.c | 144 if (info->reemit_current2d && info->state_2d.op)
145 info->reemit_current2d(pScrn, info->state_2d.op);
|
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| radeon_exa_funcs.c | 97 if (info->state_2d.op == 0 && op == 0)
100 has_src = info->state_2d.src_pitch_offset || (info->cs && info->state_2d.src_bo);
107 OUT_ACCEL_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
108 OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
109 OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
110 OUT_ACCEL_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
111 OUT_ACCEL_REG(RADEON_DP_SRC_FRGD_CLR, info->state_2d.dp_src_frgd_clr);
112 OUT_ACCEL_REG(RADEON_DP_SRC_BKGD_CLR, info->state_2d.dp_src_bkgd_clr);
113 OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask)
[all...] |
| radeon_kms.c | 112 if (info->reemit_current2d && info->state_2d.op)
113 info->reemit_current2d(pScrn, info->state_2d.op);
|
| radeon.h | 1011 struct radeon_2d_state state_2d; member in struct:__anon6814
|
