Searched refs:x02 (Results 1 - 25 of 688) sorted by relevance

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/xsrc/external/mit/xf86-video-geode/dist/src/
H A Dcim_dev.h31 #define CIM_FREE_MEM 0x02
36 #define CIM_F_CMDBUF 0x02 /* GP command buffer flag */
/xsrc/external/mit/xf86-video-sis/dist/src/
H A Doem310.h84 0x02,0x02,0x02,
85 0x02,0x02,0x02,
86 0x02,0x02,0x02,
87 0x02,
[all...]
H A Dinit301.h90 0x7d,0x05,0x4b,0x00,0x00,0xe2,0x00,0x02,
93 0x00,0x40,0x44,0x00,0xdb,0x02,0x3b,0x00
130 0x7d,0x05,0x45,0x00,0x00,0xe8,0x00,0x02,
133 0x00,0x40,0x3e,0x00,0xe1,0x02,0x28,0x00
151 0x21,0xE4,0x2E,0x9B, /* 0x02 SiS_PALMPhase */
196 0x02,0xC0,0x00,0x04,0x00,0x03,0x40,0x05,0x26,0x03,0x10,0x00,0x88,
197 0x00,0x02,0x00,0x06,0x00,0x41,0x5A,0x64,0x00,0x00,0x00,0x00,0x04,
213 0x0E,0xE0,0x00,0x05,0xD0,0x02,0x80,0x05,0x26,0x03,0x10,0x00,0x20,
225 0x01,0xC0,0x20,0x03,0x58,0x02,0x20,0x04,0x74,0x02,
[all...]
H A Doem300.h582 {0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
583 {0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
584 {0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
585 {0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
586 {0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
587 {0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
588 {0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
593 {0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46},
594 {0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C},
595 {0xFF,0x03,0x02,
[all...]
/xsrc/external/mit/xf86-video-nsc/dist/src/panel/
H A Dpnl_defs.h160 #define PNL_9211_A 0x02
165 #define PNL_SSTN 0x02
171 #define PNL_COLOR_PANEL 0x02
175 #define PNL_PLATFORM 0x02
/xsrc/external/mit/xf86-video-geode/dist/src/panel/
H A Dpnl_defs.h50 #define PNL_9211_A 0x02
55 #define PNL_SSTN 0x02
61 #define PNL_COLOR_PANEL 0x02
65 #define PNL_PLATFORM 0x02
/xsrc/external/mit/brotli/dist/c/dec/
H A Dprefix.h28 { 0x00, 0x00, 0, 0x02, 0x0000, 0x0004 },
36 { 0x00, 0x00, 0, 0x02, 0x0001, 0x0004 },
44 { 0x00, 0x00, 0, 0x02, 0x0002, 0x0004 },
52 { 0x00, 0x00, 0, 0x02, 0x0003, 0x0004 },
60 { 0x00, 0x00, 0, 0x02, 0x0004, 0x0004 },
68 { 0x00, 0x00, 0, 0x02, 0x0005, 0x0004 },
76 { 0x01, 0x00, 0, 0x02, 0x0006, 0x0004 },
84 { 0x01, 0x00, 0, 0x02, 0x0008, 0x0004 },
92 { 0x00, 0x02, 0, 0x03, 0x0000, 0x000e },
93 { 0x00, 0x02,
[all...]
/xsrc/external/mit/freetype/dist/include/freetype/
H A Dftgasp.h96 #define FT_GASP_DO_GRAY 0x02
/xsrc/external/mit/xf86-video-vboxvideo/dist/src/
H A DHGSMIChannels.h44 #define HGSMI_CH_VBVA 0x02
H A DHGSMIChSetup.h47 #define HGSMIHOSTFLAGS_IRQ UINT32_C(0x02)
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_video_hwmc.h37 #define XVMC_I965_MPEG2_MC 0x02
/xsrc/external/mit/xf86-input-vmmouse/dist/shared/
H A Dvmmouse_defs.h77 #define VMMOUSE_RESTRICT_IOPL 0x02
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_video_hwmc.h37 #define XVMC_I965_MPEG2_MC 0x02
/xsrc/external/mit/xorgproto/dist/include/X11/extensions/
H A Drecordconst.h39 #define XRecordFromClientTime 0x02
H A DXvMC.h37 #define XVMC_MB_TYPE_MOTION_FORWARD 0x02
43 #define XVMC_PREDICTION_FRAME 0x02
45 #define XVMC_PREDICTION_16x8 0x02
49 #define XVMC_SELECT_FIRST_BACKWARD 0x02
/xsrc/external/mit/xf86-video-i740/dist/src/
H A Di740_reg.h77 #define EXTENDED_ATTR_CNTL 0x02
82 #define LINEAR_MODE_ENABLE 0x02
91 #define CHIP_RESET 0x02
95 #define VGA_WRAP_MODE 0x02
97 #define VGA_NO_WRAP 0x02
118 #define DRAM_REFRESH_FAST_TEST 0x02
128 #define HSYNC_CNTL 0x02
130 #define HSYNC_OFF 0x02
141 #define DISPLAY_8BPP_MODE 0x02
159 #define CURSOR_MODE_128_2C 0x02
[all...]
/xsrc/external/mit/libdrm/dist/nouveau/nvif/
H A Dcl0080.h17 #define NV_DEVICE_INFO_V0_AGP 0x02
24 #define NV_DEVICE_INFO_V0_CELSIUS 0x02
H A Dif0003.h18 #define NVIF_PERFDOM_V0_READ 0x02
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ramdac/
H A DBT.h11 #define BT485_RAMDAC (VENDOR_BT << 16) | 0x02
19 #define BT_PIXEL_MASK 0x02
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dintel_xvmc.h46 #define XVMC_I965_MPEG2_MC 0x02
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dintel_xvmc.h46 #define XVMC_I965_MPEG2_MC 0x02
/xsrc/external/mit/xf86-video-openchrome/dist/src/
H A Dvia_sii164.h35 #define VIA_SII164_EDGE 0x02
H A Dvia_vt1632.h32 #define VIA_VT1632_EDGE 0x02
/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_common.h51 #define DRM_R128_CCE_STOP 0x02
77 DRM_R128_CLEANUP_CCE = 0x02
125 DRM_R128_WRITE_PIXELS = 0x02,
158 DRM_R128_CLEANUP_FULLSCREEN = 0x02
/xsrc/external/mit/xf86-video-intel-old/dist/src/sil164/
H A Dsil164_reg.h35 #define SIL164_DID_LO 0x02

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