/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_vf_error.c | 59 u32 data1, data2, data3; local in function:amdgpu_vf_error_trans_all 84 data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF; 87 adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
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amdgpu_vf_error.c | 59 u32 data1, data2, data3; local in function:amdgpu_vf_error_trans_all 84 data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF; 87 adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
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amdgpu_mmhub_v1_0.c | 442 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; local in function:mmhub_v1_0_update_medium_grain_clock_gating 448 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 463 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 480 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 498 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 499 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
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amdgpu_uvd_v5_0.c | 655 uint32_t data, data2; local in function:uvd_v5_0_set_sw_clock_gating 658 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 690 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 697 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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amdgpu_mmhub_v1_0.c | 442 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; local in function:mmhub_v1_0_update_medium_grain_clock_gating 448 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 463 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 480 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 498 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 499 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
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amdgpu_uvd_v5_0.c | 655 uint32_t data, data2; local in function:uvd_v5_0_set_sw_clock_gating 658 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 690 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 697 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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amdgpu_uvd_v6_0.c | 1310 uint32_t data, data2; local in function:uvd_v6_0_set_sw_clock_gating 1313 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 1346 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1353 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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amdgpu_uvd_v6_0.c | 1310 uint32_t data, data2; local in function:uvd_v6_0_set_sw_clock_gating 1313 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 1346 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1353 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
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/src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/rtl/ |
tsan_string.cc | 43 char *data2 = new char[10]; local in function:__tsan::TEST 46 t2.Memcpy(data, data2, 10, true); 52 char *data2 = new char[10]; local in function:__tsan::TEST 55 t2.Memcpy(data+3, data2, 4, true); 61 char *data2 = new char[10]; local in function:__tsan::TEST 64 t2.Memcpy(data1, data2, 10, true);
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tsan_string.cc | 43 char *data2 = new char[10]; local in function:__tsan::TEST 46 t2.Memcpy(data, data2, 10, true); 52 char *data2 = new char[10]; local in function:__tsan::TEST 55 t2.Memcpy(data+3, data2, 4, true); 61 char *data2 = new char[10]; local in function:__tsan::TEST 64 t2.Memcpy(data1, data2, 10, true);
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/src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/ |
enum.h | 12 u32 data2; member in struct:nvkm_enum
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enum.h | 12 u32 data2; member in struct:nvkm_enum
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/src/sys/arch/macppc/dev/ |
ams.c | 265 static u_char data2[] = local in function:ems_init 276 adb_op_sync((Ptr)data2, NULL, (Ptr)0, ADBLISTEN(adbaddr, 2));
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ams.c | 265 static u_char data2[] = local in function:ems_init 276 adb_op_sync((Ptr)data2, NULL, (Ptr)0, ADBLISTEN(adbaddr, 2));
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/src/sys/dev/acpi/wmi/ |
wmi_acpivar.h | 60 uint16_t data2; member in struct:guid_t::__anon51c7cc390108 112 (a)->data2 == (b)->data2 && \
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wmi_acpivar.h | 60 uint16_t data2; member in struct:guid_t::__anon51c7cc390108 112 (a)->data2 == (b)->data2 && \
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/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
nouveau_nvkm_engine_gr_ctxgf117.c | 206 u32 data[6] = {}, data2[2] = {}; local in function:gf117_grctx_generate_rop_mapping 222 data2[0] = (ntpcv << 16); 223 data2[0] |= (shift << 21); 224 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); 226 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); 236 gr->screen_tile_row_offset | data2[0]); 237 nvkm_wr32(device, 0x41bfe4, data2[1]);
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nouveau_nvkm_engine_gr_ctxgf117.c | 206 u32 data[6] = {}, data2[2] = {}; local in function:gf117_grctx_generate_rop_mapping 222 data2[0] = (ntpcv << 16); 223 data2[0] |= (shift << 21); 224 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); 226 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); 236 gr->screen_tile_row_offset | data2[0]); 237 nvkm_wr32(device, 0x41bfe4, data2[1]);
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nouveau_nvkm_engine_gr_ctxgf100.c | 1123 u32 data[6] = {}, data2[2] = {}; local in function:gf100_grctx_generate_rop_mapping 1139 data2[0] = (ntpcv << 16); 1140 data2[0] |= (shift << 21); 1141 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); 1143 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); 1153 gr->screen_tile_row_offset | data2[0]); 1154 nvkm_wr32(device, 0x419be4, data2[1]);
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nouveau_nvkm_engine_gr_ctxgf100.c | 1123 u32 data[6] = {}, data2[2] = {}; local in function:gf100_grctx_generate_rop_mapping 1139 data2[0] = (ntpcv << 16); 1140 data2[0] |= (shift << 21); 1141 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); 1143 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); 1153 gr->screen_tile_row_offset | data2[0]); 1154 nvkm_wr32(device, 0x419be4, data2[1]);
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/src/sys/arch/hpcmips/vr/ |
vrc4172pwm.c | 156 int data2; local in function:vrc4172pwmprobe 181 if ((data2 = bus_space_read_2(va->va_iot, ioh, 189 data, data2, VRC2_PWM_LCDEN_MASK));
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vrc4172pwm.c | 156 int data2; local in function:vrc4172pwmprobe 181 if ((data2 = bus_space_read_2(va->va_iot, ioh, 189 data, data2, VRC2_PWM_LCDEN_MASK));
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/src/sys/dev/i2c/ |
lm87.c | 186 u_int8_t cmd, data, data2; local in function:lmenv_attach 207 sc->sc_addr, &cmd, sizeof cmd, &data2, sizeof data, 0)) { 212 printf(": %s rev %x\n", lmenv_ids[i].name, data2); 249 data2 = (data | LM87_CONFIG1_START); 250 data2 = data2 & ~LM87_CONFIG1_INTCLR; 252 if (data != data2) { 254 sc->sc_addr, &cmd, sizeof cmd, &data2, sizeof data2, 0)) {
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lm87.c | 186 u_int8_t cmd, data, data2; local in function:lmenv_attach 207 sc->sc_addr, &cmd, sizeof cmd, &data2, sizeof data, 0)) { 212 printf(": %s rev %x\n", lmenv_ids[i].name, data2); 249 data2 = (data | LM87_CONFIG1_START); 250 data2 = data2 & ~LM87_CONFIG1_INTCLR; 252 if (data != data2) { 254 sc->sc_addr, &cmd, sizeof cmd, &data2, sizeof data2, 0)) {
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/src/sys/dev/ic/ |
rtsx.c | 1029 uint8_t data0, data1, data2, data3, rwctl; local in function:rtsx_read_cfg 1045 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1047 *val = ((uint32_t)data3 << 24) | (data2 << 16) | (data1 << 8) | data0;
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