Searched refs:irq (Results 1 - 25 of 1082) sorted by relevance

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/src/sys/arch/i386/pci/
H A Dpiixreg.h44 #define PIIX_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
45 ((1 << (irq)) & PIIX_PIRQ_MASK) != 0)
H A Dopti82c558reg.h49 #define VIPER_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
50 ((1 << (irq)) & VIPER_PIRQ_MASK) != 0)
H A Dsis85c503reg.h51 #define SIS85C503_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
52 ((1 << (irq)) & SIS85C503_PIRQ_MASK) != 0)
H A Dopti82c700reg.h38 #define FIRESTAR_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
39 ((1 << (irq)) & FIRESTAR_PIRQ_MASK) != 0)
H A Dvia82c586reg.h64 #define VP3_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
65 ((1 << (irq)) & VP3_PIRQ_MASK) != 0)
/src/sys/dev/isa/
H A Dwssreg.h43 #define WSS_IRQ_VALID(irq) ((irq) == 7 || (irq) == 9 || \
44 (irq) == 10 || (irq) == 11)
/src/sys/external/bsd/drm2/include/linux/
H A Dhardirq.h40 * synchronize_irq(irq)
42 * Wait for all interrupt handlers servicing irq to complete on
48 synchronize_irq(int irq) argument
56 synchronize_hardirq(int irq) argument
/src/sys/external/gpl2/dts/dist/include/dt-bindings/interrupt-controller/
H A Dmips-gic.h7 #include <dt-bindings/interrupt-controller/irq.h>
H A Dapple-aic.h7 #include <dt-bindings/interrupt-controller/irq.h>
/src/sys/arch/ia64/include/
H A Disa_machdep.h34 isa_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level, argument
37 return intr_establish(irq, type, level, ih_func, ih_arg);
41 #define isa_intr_establish_xname(ic, irq, type, level, fun, arg, xname) \
42 isa_intr_establish(ic, irq, type, level, fun, arg)
/src/sys/arch/arm/ofw/
H A Dofw_irqhandler.c79 /* Clear all the IRQ handlers and the irq block masks */
104 * int irq_claim(int irq, irqhandler_t *handler)
110 irq_claim(int irq, irqhandler_t *handler, const char *group, const char *name) argument
123 * IRQ_INSTRUCT indicates that we should get the irq number
124 * from the irq structure
126 if (irq == IRQ_INSTRUCT)
127 irq = handler->ih_num;
129 /* Make sure the irq number is valid */
130 if (irq < 0 || irq >
207 irq_release(int irq,irqhandler_t * handler) argument
291 intr_claim(int irq,int level,int (* ih_func)(void *),void * ih_arg,const char * group,const char * name) argument
329 disable_irq(int irq) argument
349 enable_irq(int irq) argument
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/src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dinterrupt.c50 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
51 #define get_irq_info(irq, e) (irq->events[e].info)
53 #define irq_to_gvt(irq) \
54 container_of(irq, struct intel_gvt, irq)
155 struct intel_gvt_irq *irq = &gvt->irq; local in function:regbase_to_irq_info
158 for_each_set_bit(i, irq
327 struct intel_gvt_irq *irq = &vgpu->gvt->irq; local in function:update_upstream_irq
379 init_irq_map(struct intel_gvt_irq * irq) argument
405 propagate_event(struct intel_gvt_irq * irq,enum intel_gvt_event_type event,struct intel_vgpu * vgpu) argument
428 handle_default_event_virt(struct intel_gvt_irq * irq,enum intel_gvt_event_type event,struct intel_vgpu * vgpu) argument
471 struct intel_gvt_irq *irq = &vgpu->gvt->irq; local in function:gen8_check_pending_irq
496 gen8_init_irq(struct intel_gvt_irq * irq) argument
627 struct intel_gvt_irq *irq = &gvt->irq; local in function:intel_vgpu_trigger_virtual_event
639 init_events(struct intel_gvt_irq * irq) argument
653 struct intel_gvt_irq *irq; local in function:vblank_timer_fn
675 struct intel_gvt_irq *irq = &gvt->irq; local in function:intel_gvt_clean_irq
694 struct intel_gvt_irq *irq = &gvt->irq; local in function:intel_gvt_init_irq
[all...]
/src/sys/arch/powerpc/pic/
H A Di8259_common.c65 i8259_enable_irq(struct pic_ops *pic, int irq, int type) argument
69 i8259->irqs |= 1 << irq;
79 i8259_disable_irq(struct pic_ops *pic, int irq) argument
82 uint32_t mask = 1 << irq;
90 i8259_ack_irq(struct pic_ops *pic, int irq) argument
92 if (irq < 8) {
93 isa_outb(IO_ICU1, 0xe0 | irq);
95 isa_outb(IO_ICU2, 0xe0 | (irq & 7));
103 int irq; local in function:i8259_get_irq
106 irq
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H A Dpic_openpic.c56 int irq; local in function:setup_openpic
97 for (irq = 0; irq < (pic->pic_numintrs - 1); irq++) {
99 openpic_write(OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK);
101 openpic_write(OPENPIC_IDEST(irq), 1 << 0);
116 for (irq = 0; irq < pic->pic_numintrs; irq++) {
121 irq
141 opic_establish_irq(struct pic_ops * pic,int irq,int type,int pri) argument
170 opic_enable_irq(struct pic_ops * pic,int irq,int type) argument
182 opic_disable_irq(struct pic_ops * pic,int irq) argument
[all...]
/src/sys/arch/arm/sa11x0/
H A Dsa11x0_irqhandler.c116 int i, irq, ipl; local in function:intr_calculatemasks
121 for (irq = 0; irq < ICU_LEN; irq++) {
123 for (q = irqhandlers[irq]; q; q = q->ih_next)
125 intrlevel[irq] = ipls;
131 for (irq = 0; irq < ICU_LEN; irq++)
132 if (intrlevel[irq]
155 sa11x0_intr_evcnt(sa11x0_chipset_tag_t ic,int irq) argument
163 sa11x0_intr_establish(sa11x0_chipset_tag_t ic,int irq,int type,int level,int (* ih_fun)(void *),void * ih_arg) argument
232 int irq = ih->ih_irq; local in function:sa11x0_intr_disestablish
266 int irq = (int)p; local in function:stray_irqhandler
281 int irq; local in function:dumpirqhandlers
[all...]
/src/sys/arch/evbppc/pmppc/
H A Dpic_cpc700.c81 cpc700_pic_enable_irq(struct pic_ops *pic, int irq, int type) argument
83 cpc700_enable_irq(irq);
87 cpc700_pic_disable_irq(struct pic_ops *pic, int irq) argument
89 cpc700_disable_irq(irq);
95 int irq; local in function:cpc700_get_irq
97 irq = cpc700_read_irq();
98 if (irq < 0)
100 return irq;
104 cpc700_ack_irq(struct pic_ops *pic, int irq) argument
106 cpc700_eoi(irq);
[all...]
/src/sys/arch/rs6000/rs6000/
H A Dpic_iocc.c87 int irq; local in function:iocc_get_irq
94 irq = 31 - __builtin_clz(rv);
95 if (irq >= 0 && irq < 16)
96 return irq;
102 iocc_enable_irq(struct pic_ops *pic, int irq, int type) argument
107 mask |= 1 << irq;
113 iocc_disable_irq(struct pic_ops *pic, int irq) argument
118 mask &= ~(1 << irq);
124 iocc_ack_irq(struct pic_ops *pic, int irq) argument
131 iocc_set_priority(int cpu,int pri,int irq) argument
[all...]
/src/sys/arch/arm/iomd/
H A Diomd_irqhandler.c83 /* Clear all the IRQ handlers and the irq block masks */
126 * int irq_claim(int irq, irqhandler_t *handler)
132 irq_claim(int irq, irqhandler_t *handler) argument
146 * IRQ_INSTRUCT indicates that we should get the irq number
147 * from the irq structure
149 if (irq == IRQ_INSTRUCT)
150 irq = handler->ih_num;
152 /* Make sure the irq number is valid */
153 if (irq < 0 || irq >
250 irq_release(int irq,irqhandler_t * handler) argument
344 intr_claim(int irq,int level,const char * name,int (* ih_func)(void *),void * ih_arg) argument
411 disable_irq(int irq) argument
431 enable_irq(int irq) argument
[all...]
/src/sys/arch/evbppc/nintendo/dev/
H A Dahb.c169 aprint_normal(" irq %d", aaa->aaa_irq);
176 hollywood_enable_irq(struct pic_ops *pic, int irq, int type) argument
178 pic_irqmask[0] |= __BIT(irq);
183 hollywood_disable_irq(struct pic_ops *pic, int irq) argument
185 pic_irqmask[0] &= ~__BIT(irq);
193 int irq; local in function:hollywood_get_irq
200 irq = ffs32(pend) - 1;
202 return irq;
206 hollywood_ack_irq(struct pic_ops *pic, int irq) argument
208 WR4(HW_PPCIRQFLAGS, __BIT(irq));
212 hollywood_establish_irq(struct pic_ops * pic,int irq,int type,int pri) argument
224 latte_enable_irq(struct pic_ops * pic,int irq,int type) argument
233 latte_disable_irq(struct pic_ops * pic,int irq) argument
245 int irq; local in function:latte_get_irq
264 latte_ack_irq(struct pic_ops * pic,int irq) argument
272 latte_establish_irq(struct pic_ops * pic,int irq,int type,int pri) argument
287 ahb_intr_init(int irq) argument
313 ahb_intr_establish(int irq,int ipl,int (* func)(void *),void * arg,const char * name) argument
[all...]
/src/sys/arch/arm/ixp12x0/
H A Dixp12x0_intr.c120 ixp12x0_enable_irq(int irq) argument
122 if (irq < SYS_NIRQ) {
123 intr_enabled |= (1U << irq);
124 switch (irq) {
133 panic("enable_irq:bad IRQ %d", irq);
136 pci_intr_enabled |= (1U << (irq - SYS_NIRQ));
137 IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ));
142 ixp12x0_disable_irq(int irq) argument
144 if (irq < SYS_NIRQ) {
145 intr_enabled ^= ~(1U << irq);
172 int irq, ipl; local in function:ixp12x0_intr_calculate_masks
331 ixp12x0_intr_establish(int irq,int ipl,int (* ih_func)(void *),void * arg) argument
385 int irq; local in function:ixp12x0_intr_dispatch
[all...]
/src/sys/arch/arm/xscale/
H A Dixp425_intr.c150 ixp425_enable_irq(int irq) argument
153 intr_enabled |= (1U << irq);
158 ixp425_disable_irq(int irq) argument
161 intr_enabled &= ~(1U << irq);
166 ixp425_irq2gpio_bit(int irq) argument
180 if (int2gpio[irq] == 0xff)
181 panic("ixp425_irq2gpio_bit: bad GPIO irq: %d\n", irq);
183 return (1U << int2gpio[irq]);
194 int irq, ip local in function:ixp425_intr_calculate_masks
333 ixp425_intr_establish(int irq,int ipl,int (* func)(void *),void * arg) argument
389 int oldirqstate, irq, ibit, hwpend; local in function:ixp425_intr_dispatch
[all...]
/src/sys/arch/powerpc/powerpc/
H A Dopenpic.c13 openpic_enable_irq(int irq, int type) argument
17 x = openpic_read(OPENPIC_SRC_VECTOR(irq));
23 openpic_write(OPENPIC_SRC_VECTOR(irq), x);
27 openpic_disable_irq(int irq) argument
31 x = openpic_read(OPENPIC_SRC_VECTOR(irq));
33 openpic_write(OPENPIC_SRC_VECTOR(irq), x);
/src/sys/arch/shark/isa/
H A Disa_irqhandler.c116 /* Clear all the IRQ handlers and the irq block masks */
141 * int irq_claim(int irq, irqhandler_t *handler)
147 irq_claim(int irq, irqhandler_t *handler, const char *group, const char *name) argument
159 * IRQ_INSTRUCT indicates that we should get the irq number
160 * from the irq structure
162 if (irq == IRQ_INSTRUCT)
163 irq = handler->ih_num;
165 /* Make sure the irq number is valid */
166 if (irq < 0 || irq >
209 irq_release(int irq,irqhandler_t * handler) argument
273 int irq, level; local in function:irq_calculatemasks
310 intr_claim(int irq,int level,int (* ih_func)(void *),void * ih_arg,const char * group,const char * name) argument
348 disable_irq(int irq) argument
368 enable_irq(int irq) argument
[all...]
/src/sys/arch/arm/ep93xx/
H A Dep93xx_intr.c87 ep93xx_enable_irq(int irq) argument
89 if (irq < VIC_NIRQ) {
90 vic1_intr_enabled |= (1U << irq);
91 VIC1REG(EP93XX_VIC_IntEnable) = (1U << irq);
93 vic2_intr_enabled |= (1U << (irq - VIC_NIRQ));
94 VIC2REG(EP93XX_VIC_IntEnable) = (1U << (irq - VIC_NIRQ));
99 ep93xx_disable_irq(int irq) argument
101 if (irq < VIC_NIRQ) {
102 vic1_intr_enabled &= ~(1U << irq);
103 VIC1REG(EP93XX_VIC_IntEnClear) = (1U << irq);
118 int irq, ipl; local in function:ep93xx_intr_calculate_masks
290 ep93xx_intr_establish(int irq,int ipl,int (* ih_func)(void *),void * arg) argument
341 int irq; local in function:ep93xx_intr_dispatch
[all...]
/src/sys/arch/i386/eisa/
H A Deisa_machdep.c131 eisa_intr_map(eisa_chipset_tag_t ec, u_int irq, argument
134 if (irq >= NUM_LEGACY_IRQS) {
135 aprint_error("eisa_intr_map: bad IRQ %d\n", irq);
139 if (irq == 2) {
141 irq = 9;
146 if (intr_find_mpmapping(mp_eisa_bus, irq, ihp) == 0 ||
147 intr_find_mpmapping(mp_isa_bus, irq, ihp) == 0) {
148 *ihp |= irq;
155 *ihp = irq;
163 int irq; local in function:eisa_intr_string
200 int pin, irq; local in function:eisa_intr_establish
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