| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| si_dpm.h | 103 u32 mpll_func_cntl_1; member in struct:si_clock_registers
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| ci_dpm.h | 141 u32 mpll_func_cntl_1; member in struct:ci_clock_registers
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| radeon_ci_dpm.c | 1897 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
2806 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; local in function:ci_calculate_mclk_params
2820 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2821 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2869 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
3087 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
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| radeon_si_dpm.c | 3587 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4391 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4507 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; local in function:si_populate_smc_acpi_state
4593 cpu_to_be32(mpll_func_cntl_1);
4890 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; local in function:si_populate_mclk_value
4904 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4905 mpll_func_cntl_1 |= CLKF(mpll_param.clkf)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_iceland_smumgr.c | 1064 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; local in function:iceland_calculate_mclk_params
1080 /* MPLL_FUNC_CNTL_1 setup*/
1081 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1082 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1083 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1084 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1085 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
[all...] |
| amdgpu_ci_smumgr.c | 1040 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; local in function:ci_calculate_mclk_params
1055 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1056 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1057 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1058 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1059 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1060 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode)
[all...] |
| amdgpu_tonga_smumgr.c | 807 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; local in function:tonga_calculate_mclk_params
826 /* MPLL_FUNC_CNTL_1 setup*/
827 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
828 MPLL_FUNC_CNTL_1, CLKF,
830 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
831 MPLL_FUNC_CNTL_1, CLKFRAC,
833 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| si_dpm.h | 919 u32 mpll_func_cntl_1; member in struct:si_clock_registers
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| amdgpu_si_dpm.c | 4048 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4857 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4971 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; local in function:si_populate_smc_acpi_state
5058 cpu_to_be32(mpll_func_cntl_1);
5354 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; local in function:si_populate_mclk_value
5368 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5369 mpll_func_cntl_1 |= CLKF(mpll_param.clkf)
[all...] |
