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    Searched refs:sc_atac (Results 1 - 25 of 80) sorted by relevancy

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  /src/sys/dev/pci/
viaide.c 432 sc->sc_wdcdev.sc_atac.atac_dev = self;
521 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
534 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
535 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
548 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
555 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
558 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
568 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5
    [all...]
artsata.c 113 sc->sc_wdcdev.sc_atac.atac_dev = self;
136 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
144 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
146 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
149 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
162 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
170 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
181 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
196 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
204 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev
    [all...]
svwsata.c 99 sc->sc_wdcdev.sc_atac.atac_dev = self;
131 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
138 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
139 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
141 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
143 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
144 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
147 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
148 sc->sc_wdcdev.sc_atac.atac_nchannels = 4;
149 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel
    [all...]
cmdide.c 121 sc->sc_wdcdev.sc_atac.atac_dev = self;
155 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
159 sc->sc_wdcdev.sc_atac.atac_claim_hw = cmd064x_claim_hw;
160 sc->sc_wdcdev.sc_atac.atac_free_hw = cmd064x_free_hw;
164 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
178 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
213 for(uint i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
238 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
250 sc->sc_wdcdev.sc_atac.atac_dev), i);
278 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev
    [all...]
schide.c 110 sc->sc_wdcdev.sc_atac.atac_dev = self;
127 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
131 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
134 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
137 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
138 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
140 sc->sc_wdcdev.sc_atac.atac_set_modes = sch_setup_channel;
141 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
142 sc->sc_wdcdev.sc_atac.atac_nchannels = 1
    [all...]
stpcide.c 80 sc->sc_wdcdev.sc_atac.atac_dev = self;
97 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
101 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
103 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
106 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
107 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
108 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
109 sc->sc_wdcdev.sc_atac.atac_set_modes = stpc_setup_channel;
110 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
111 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS
    [all...]
iteide.c 90 sc->sc_wdcdev.sc_atac.atac_dev = self;
111 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
117 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
122 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
125 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
128 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
129 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
130 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
132 sc->sc_wdcdev.sc_atac.atac_set_modes = ite_setup_channel;
133 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray
    [all...]
pdcsata.c 216 sc->sc_wdcdev.sc_atac.atac_dev = self;
238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
246 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
249 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
256 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
264 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
275 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
282 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
284 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
286 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA
    [all...]
cypide.c 83 sc->sc_wdcdev.sc_atac.atac_dev = self;
109 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
114 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
118 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
125 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
130 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
132 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
135 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
136 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
137 sc->sc_wdcdev.sc_atac.atac_set_modes = cy693_setup_channel
    [all...]
toshide.c 103 sc->sc_wdcdev.sc_atac.atac_dev = self;
124 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
130 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16;
131 sc->sc_wdcdev.sc_atac.atac_pio_cap = 5;
134 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
136 sc->sc_wdcdev.sc_atac.atac_dma_cap = 3;
137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
140 sc->sc_wdcdev.sc_atac.atac_set_modes = piccolo_setup_channel;
142 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
143 sc->sc_wdcdev.sc_atac.atac_nchannels = 1
    [all...]
rccide.c 106 sc->sc_wdcdev.sc_atac.atac_dev = self;
123 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
127 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
130 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
133 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
134 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
141 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
143 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
148 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5
    [all...]
siside.c 103 sc->sc_wdcdev.sc_atac.atac_dev = self;
234 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
247 sc->sc_wdcdev.sc_atac.atac_udma_cap =
252 sc->sc_wdcdev.sc_atac.atac_udma_cap =
256 sc->sc_wdcdev.sc_atac.atac_udma_cap =
262 sc->sc_wdcdev.sc_atac.atac_udma_cap =
269 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
272 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
278 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
283 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32
    [all...]
pciide_common.c 183 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags);
187 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
236 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
248 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
273 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
279 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
300 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
309 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
319 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
351 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev
    [all...]
geodeide.c 96 sc->sc_wdcdev.sc_atac.atac_dev = self;
111 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
116 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA;
124 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
125 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
126 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
133 sc->sc_wdcdev.sc_atac.atac_udma_cap = 1;
135 sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel;
136 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
137 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS
    [all...]
aceride.c 90 sc->sc_wdcdev.sc_atac.atac_dev = self;
123 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
127 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
129 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
131 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
133 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
135 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
144 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev
    [all...]
hptide.c 100 sc->sc_wdcdev.sc_atac.atac_dev = self;
118 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
172 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
176 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
178 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
181 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
182 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
184 sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel;
185 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
188 sc->sc_wdcdev.sc_atac.atac_nchannels = 1
    [all...]
ixpide.c 88 sc->sc_wdcdev.sc_atac.atac_dev = self;
107 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
112 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
114 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
118 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
119 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
120 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
121 sc->sc_wdcdev.sc_atac.atac_set_modes = ixp_setup_channel;
122 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
123 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS
    [all...]
nside.c 84 sc->sc_wdcdev.sc_atac.atac_dev = self;
100 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
105 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
108 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
122 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
123 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
124 sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel;
125 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
126 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
142 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++)
    [all...]
optiide.c 96 sc->sc_wdcdev.sc_atac.atac_dev = self;
114 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
133 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16;
134 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
136 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
138 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
140 sc->sc_wdcdev.sc_atac.atac_set_modes = opti_setup_channel;
142 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
143 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
153 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels
    [all...]
  /src/sys/arch/arm/gemini/
obio_wdc.c 109 sc->sc_wdcdev.sc_atac.atac_dev = self;
133 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
135 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
137 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
138 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
141 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
151 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NOIRQ;
  /src/sys/arch/evbarm/iq31244/
wdc_obio.c 80 sc->sc_wdcdev.sc_atac.atac_dev = self;
104 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
106 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
108 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
109 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
112 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
128 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NOIRQ;
  /src/sys/dev/podulebus/
hcide.c 87 sc->sc_wdc.sc_atac.atac_dev = self;
90 sc->sc_wdc.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_NOIRQ;
91 sc->sc_wdc.sc_atac.atac_pio_cap = 0; /* XXX correct? */
92 sc->sc_wdc.sc_atac.atac_nchannels = HCIDE_NCHANNELS;
93 sc->sc_wdc.sc_atac.atac_channels = sc->sc_chp;
100 ch->ch_atac = &sc->sc_wdc.sc_atac;
  /src/sys/arch/evbarm/tsarm/
wdc_ts.c 77 sc->sc_wdcdev.sc_atac.atac_dev = self;
102 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
104 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
106 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
107 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
110 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
  /src/sys/arch/prep/pnpbus/
wdc_pnpbus.c 104 sc->sc_wdcdev.sc_atac.atac_dev = self;
130 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
131 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
133 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32;
135 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
137 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_chanlist;
138 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
141 sc->sc_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
  /src/sys/dev/isa/
wdc_isa.c 167 sc->sc_wdcdev.sc_atac.atac_dev = self;
197 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
206 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
208 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32;
210 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATA_NOSTREAM;
212 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATAPI_NOSTREAM;
214 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
216 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
217 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
220 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
    [all...]

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