cpu.h revision 1.106.12.2
1 /* $NetBSD: cpu.h,v 1.106.12.2 2014/08/20 00:03:12 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #if defined(_KERNEL_OPT) 49 #include "opt_cputype.h" 50 #include "opt_lockdebug.h" 51 #include "opt_multiprocessor.h" 52 #endif 53 54 #ifndef _LOCORE 55 #include <sys/cpu_data.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 59 typedef struct cpu_watchpoint { 60 register_t cw_addr; 61 register_t cw_mask; 62 uint32_t cw_asid; 63 uint32_t cw_mode; 64 } cpu_watchpoint_t; 65 /* (abstract) mode bits */ 66 #define CPUWATCH_WRITE __BIT(0) 67 #define CPUWATCH_READ __BIT(1) 68 #define CPUWATCH_EXEC __BIT(2) 69 #define CPUWATCH_MASK __BIT(3) 70 #define CPUWATCH_ASID __BIT(4) 71 #define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE) 72 73 #define CPUWATCH_MAX 8 /* max possible number of watchpoints */ 74 75 u_int cpuwatch_discover(void); 76 void cpuwatch_free(cpu_watchpoint_t *); 77 cpu_watchpoint_t *cpuwatch_alloc(void); 78 void cpuwatch_set_all(void); 79 void cpuwatch_clr_all(void); 80 void cpuwatch_set(cpu_watchpoint_t *); 81 void cpuwatch_clr(cpu_watchpoint_t *); 82 83 struct cpu_info { 84 struct cpu_data ci_data; /* MI per-cpu data */ 85 struct cpu_info *ci_next; /* Next CPU in list */ 86 struct cpu_softc *ci_softc; /* chip-dependent hook */ 87 device_t ci_dev; /* owning device */ 88 cpuid_t ci_cpuid; /* Machine-level identifier */ 89 u_long ci_cctr_freq; /* cycle counter frequency */ 90 u_long ci_cpu_freq; /* CPU frequency */ 91 u_long ci_cycles_per_hz; /* CPU freq / hz */ 92 u_long ci_divisor_delay; /* for delay/DELAY */ 93 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 94 struct lwp *ci_curlwp; /* currently running lwp */ 95 volatile int ci_want_resched; /* user preemption pending */ 96 int ci_mtx_count; /* negative count of held mutexes */ 97 int ci_mtx_oldspl; /* saved SPL value */ 98 int ci_idepth; /* hardware interrupt depth */ 99 int ci_cpl; /* current [interrupt] priority level */ 100 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 101 struct evcnt ci_ev_count_compare; /* hard clock intr counter */ 102 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */ 103 struct lwp *ci_softlwps[SOFTINT_COUNT]; 104 volatile u_int ci_softints; 105 struct evcnt ci_ev_fpu_loads; /* fpu load counter */ 106 struct evcnt ci_ev_fpu_saves; /* fpu save counter */ 107 struct evcnt ci_ev_dsp_loads; /* dsp load counter */ 108 struct evcnt ci_ev_dsp_saves; /* dsp save counter */ 109 struct evcnt ci_ev_tlbmisses; 110 111 /* 112 * Per-cpu pmap information 113 */ 114 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 115 u_int ci_pmap_asid_cur; /* current ASID */ 116 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 117 union segtab *ci_pmap_seg0tab; 118 #ifdef _LP64 119 union segtab *ci_pmap_segtab; 120 #else 121 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 122 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 123 #endif 124 125 u_int ci_cpuwatch_count; /* number of watchpoints on this CPU */ 126 cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX]; 127 128 #ifdef MULTIPROCESSOR 129 volatile u_long ci_flags; 130 volatile uint64_t ci_request_ipis; 131 /* bitmask of IPIs requested */ 132 /* use on chips where hw cannot pass tag */ 133 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 134 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 135 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 136 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 137 struct evcnt ci_evcnt_synci_activate_rqst; 138 struct evcnt ci_evcnt_synci_onproc_rqst; 139 struct evcnt ci_evcnt_synci_deferred_rqst; 140 struct evcnt ci_evcnt_synci_ipi_rqst; 141 142 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 143 #define CPUF_PRESENT 0x02 /* CPU is present */ 144 #define CPUF_RUNNING 0x04 /* CPU is running */ 145 #define CPUF_PAUSED 0x08 /* CPU is paused */ 146 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 147 #endif 148 149 }; 150 151 #define CPU_INFO_ITERATOR int __unused 152 #define CPU_INFO_FOREACH(cii, ci) \ 153 ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 154 155 #endif /* !_LOCORE */ 156 #endif /* _KERNEL */ 157 158 /* 159 * CTL_MACHDEP definitions. 160 */ 161 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 162 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 163 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 164 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 165 #define CPU_LMMI 5 /* Loongson multimedia instructions */ 166 167 /* 168 * Platform can override, but note this breaks userland compatibility 169 * with other mips platforms. 170 */ 171 #ifndef CPU_MAXID 172 #define CPU_MAXID 5 /* number of valid machdep ids */ 173 #endif 174 175 #ifdef _KERNEL 176 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 177 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 178 #define MIPS1 1 179 #define MIPS3 1 180 #define MIPS4 1 181 #define MIPS32 1 182 #define MIPS32R2 1 183 #define MIPS64 1 184 #define MIPS64R2 1 185 #endif 186 187 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 188 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64RR2 must be specified 189 #endif 190 191 /* Shortcut for MIPS3 or above defined */ 192 #if defined(MIPS3) || defined(MIPS4) \ 193 || defined(MIPS32) || defined(MIPS32R2) \ 194 || defined(MIPS64) || defined(MIPS64R2) 195 196 #define MIPS3_PLUS 1 197 #define __HAVE_CPU_COUNTER 198 #else 199 #undef MIPS3_PLUS 200 #endif 201 202 /* 203 * Macros to find the CPU architecture we're on at run-time, 204 * or if possible, at compile-time. 205 */ 206 207 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 208 #define CPU_ARCH_MIPS1 (1 << 0) 209 #define CPU_ARCH_MIPS2 (1 << 1) 210 #define CPU_ARCH_MIPS3 (1 << 2) 211 #define CPU_ARCH_MIPS4 (1 << 3) 212 #define CPU_ARCH_MIPS5 (1 << 4) 213 #define CPU_ARCH_MIPS32 (1 << 5) 214 #define CPU_ARCH_MIPS64 (1 << 6) 215 #define CPU_ARCH_MIPS32R2 (1 << 7) 216 #define CPU_ARCH_MIPS64R2 (1 << 8) 217 218 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 219 #define MIPS_CURLWP $24 220 #define MIPS_CURLWP_QUOTED "$24" 221 #define MIPS_CURLWP_LABEL _L_T8 222 #define MIPS_CURLWP_REG _R_T8 223 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 224 225 #ifndef _LOCORE 226 227 extern struct cpu_info cpu_info_store; 228 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 229 230 #define curlwp mips_curlwp 231 #define curcpu() (curlwp->l_cpu) 232 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 233 #ifdef MULTIPROCESSOR 234 #define cpu_number() (curcpu()->ci_index) 235 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 236 #else 237 #define cpu_number() (0) 238 #define CPU_IS_PRIMARY(ci) (true) 239 #endif 240 241 /* XXX simonb 242 * Should the following be in a cpu_info type structure? 243 * And how many of these are per-cpu vs. per-system? (Ie, 244 * we can assume that all cpus have the same mmu-type, but 245 * maybe not that all cpus run at the same clock speed. 246 * Some SGI's apparently support R12k and R14k in the same 247 * box.) 248 */ 249 struct mips_options { 250 const struct pridtab *mips_cpu; 251 252 u_int mips_cpu_arch; 253 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 254 u_int mips_cpu_flags; 255 u_int mips_num_tlb_entries; 256 mips_prid_t mips_cpu_id; 257 mips_prid_t mips_fpu_id; 258 bool mips_has_r4k_mmu; 259 bool mips_has_llsc; 260 u_int mips3_pg_shift; 261 u_int mips3_pg_cached; 262 u_int mips3_cca_devmem; 263 #ifdef MIPS3_PLUS 264 #ifdef _LP64 265 uint64_t mips3_xkphys_cached; 266 #endif 267 uint64_t mips3_tlb_vpn_mask; 268 uint64_t mips3_tlb_pfn_mask; 269 uint32_t mips3_tlb_pg_mask; 270 #endif 271 }; 272 extern struct mips_options mips_options; 273 274 #define CPU_MIPS_R4K_MMU 0x0001 275 #define CPU_MIPS_NO_LLSC 0x0002 276 #define CPU_MIPS_CAUSE_IV 0x0004 277 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 278 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 279 #define CPU_MIPS_CACHED_CCA_SHIFT 4 280 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 281 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 282 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 283 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 284 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 285 #define CPU_MIPS_NO_LLADDR 0x1000 286 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 287 #define CPU_MIPS_LOONGSON2 0x4000 288 #define MIPS_NOT_SUPP 0x8000 289 #define CPU_MIPS_HAVE_DSP 0x10000 290 291 #endif /* !_LOCORE */ 292 293 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 294 295 #if defined(MIPS1) 296 297 # define CPUISMIPS3 0 298 # define CPUIS64BITS 0 299 # define CPUISMIPS32 0 300 # define CPUISMIPS32R2 0 301 # define CPUISMIPS64 0 302 # define CPUISMIPS64R2 0 303 # define CPUISMIPSNN 0 304 # define MIPS_HAS_R4K_MMU 0 305 # define MIPS_HAS_CLOCK 0 306 # define MIPS_HAS_LLSC 0 307 # define MIPS_HAS_LLADDR 0 308 # define MIPS_HAS_DSP 0 309 # define MIPS_HAS_LMMI 0 310 311 #elif defined(MIPS3) || defined(MIPS4) 312 313 # define CPUISMIPS3 1 314 # define CPUIS64BITS 1 315 # define CPUISMIPS32 0 316 # define CPUISMIPS32R2 0 317 # define CPUISMIPS64 0 318 # define CPUISMIPS64R2 0 319 # define CPUISMIPSNN 0 320 # define MIPS_HAS_R4K_MMU 1 321 # define MIPS_HAS_CLOCK 1 322 # if defined(_LOCORE) 323 # if !defined(MIPS3_4100) 324 # define MIPS_HAS_LLSC 1 325 # else 326 # define MIPS_HAS_LLSC 0 327 # endif 328 # else /* _LOCORE */ 329 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 330 # endif /* _LOCORE */ 331 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 332 # define MIPS_HAS_DSP 0 333 # if defined(MIPS3_LOONGSON2) 334 # define MIPS_HAS_LMMI ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0) 335 # else 336 # define MIPS_HAS_LMMI 0 337 # endif 338 #elif defined(MIPS32) 339 340 # define CPUISMIPS3 1 341 # define CPUIS64BITS 0 342 # define CPUISMIPS32 1 343 # define CPUISMIPS32R2 0 344 # define CPUISMIPS64 0 345 # define CPUISMIPS64R2 0 346 # define CPUISMIPSNN 1 347 # define MIPS_HAS_R4K_MMU 1 348 # define MIPS_HAS_CLOCK 1 349 # define MIPS_HAS_LLSC 1 350 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 351 # define MIPS_HAS_DSP 0 352 # define MIPS_HAS_LMMI 0 353 354 #elif defined(MIPS32R2) 355 356 # define CPUISMIPS3 1 357 # define CPUIS64BITS 0 358 # define CPUISMIPS32 0 359 # define CPUISMIPS32R2 1 360 # define CPUISMIPS64 0 361 # define CPUISMIPS64R2 0 362 # define CPUISMIPSNN 1 363 # define MIPS_HAS_R4K_MMU 1 364 # define MIPS_HAS_CLOCK 1 365 # define MIPS_HAS_LLSC 1 366 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 367 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 368 # define MIPS_HAS_LMMI 0 369 370 #elif defined(MIPS64) 371 372 # define CPUISMIPS3 1 373 # define CPUIS64BITS 1 374 # define CPUISMIPS32 0 375 # define CPUISMIPS32R2 0 376 # define CPUISMIPS64 1 377 # define CPUISMIPS64R2 0 378 # define CPUISMIPSNN 1 379 # define MIPS_HAS_R4K_MMU 1 380 # define MIPS_HAS_CLOCK 1 381 # define MIPS_HAS_LLSC 1 382 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 383 # define MIPS_HAS_DSP 0 384 # define MIPS_HAS_LMMI 0 385 386 #elif defined(MIPS64R2) 387 388 # define CPUISMIPS3 1 389 # define CPUIS64BITS 1 390 # define CPUISMIPS32 0 391 # define CPUISMIPS32R2 0 392 # define CPUISMIPS64 0 393 # define CPUISMIPS64R2 1 394 # define CPUISMIPSNN 1 395 # define MIPS_HAS_R4K_MMU 1 396 # define MIPS_HAS_CLOCK 1 397 # define MIPS_HAS_LLSC 1 398 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 399 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 400 # define MIPS_HAS_LMMI 0 401 402 #endif 403 404 #else /* run-time test */ 405 406 #ifndef _LOCORE 407 408 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 409 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 410 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 411 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 412 413 /* This test is ... rather bogus */ 414 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 415 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 416 417 /* And these aren't much better while the previous test exists as is... */ 418 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 419 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 420 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 421 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 422 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 423 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 424 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 425 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 426 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 427 428 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 429 430 #else /* !_LOCORE */ 431 432 #define MIPS_HAS_LLSC 0 433 434 #endif /* !_LOCORE */ 435 436 #endif /* run-time test */ 437 438 #ifndef _LOCORE 439 440 /* 441 * definitions of cpu-dependent requirements 442 * referenced in generic code 443 */ 444 445 /* 446 * Send an inter-processor interupt to each other CPU (excludes curcpu()) 447 */ 448 void cpu_broadcast_ipi(int); 449 450 /* 451 * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu()) 452 */ 453 void cpu_multicast_ipi(__cpuset_t, int); 454 455 /* 456 * Send an inter-processor interupt to another CPU. 457 */ 458 int cpu_send_ipi(struct cpu_info *, int); 459 460 /* 461 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 462 */ 463 void cpu_intr(int, vaddr_t, uint32_t); 464 465 /* 466 * Arguments to hardclock and gatherstats encapsulate the previous 467 * machine state in an opaque clockframe. 468 */ 469 struct clockframe { 470 vaddr_t pc; /* program counter at time of interrupt */ 471 uint32_t sr; /* status register at time of interrupt */ 472 bool intr; /* interrupted a interrupt */ 473 }; 474 475 /* 476 * A port must provde CLKF_USERMODE() for use in machine-independent code. 477 * These differ on r4000 and r3000 systems; provide them in the 478 * port-dependent file that includes this one, using the macros below. 479 */ 480 481 /* mips1 versions */ 482 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 483 484 /* mips3 versions */ 485 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 486 487 #define CLKF_PC(framep) ((framep)->pc) 488 #define CLKF_INTR(framep) ((framep)->intr) 489 490 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 491 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 492 #endif 493 494 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 495 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 496 #endif 497 498 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 499 #define CLKF_USERMODE(framep) \ 500 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 501 #endif 502 503 /* 504 * Misc prototypes and variable declarations. 505 */ 506 #define LWP_PC(l) cpu_lwp_pc(l) 507 508 struct proc; 509 struct lwp; 510 struct pcb; 511 struct reg; 512 513 /* 514 * Preempt the current process if in interrupt from user mode, 515 * or after the current trap/syscall if in system mode. 516 */ 517 void cpu_need_resched(struct cpu_info *, int); 518 /* 519 * Notify the current lwp (l) that it has a signal pending, 520 * process as soon as possible. 521 */ 522 void cpu_signotify(struct lwp *); 523 524 /* 525 * Give a profiling tick to the current process when the user profiling 526 * buffer pages are invalid. On the MIPS, request an ast to send us 527 * through trap, marking the proc as needing a profiling tick. 528 */ 529 void cpu_need_proftick(struct lwp *); 530 void cpu_set_curpri(int); 531 532 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 533 534 struct cpu_info * 535 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 536 cpuid_t); 537 void cpu_attach_common(device_t, struct cpu_info *); 538 void cpu_startup_common(void); 539 #ifdef _LP64 540 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 541 #endif 542 543 #ifdef MULTIPROCESSOR 544 void cpu_hatch(struct cpu_info *ci); 545 void cpu_trampoline(void); 546 void cpu_boot_secondary_processors(void); 547 void cpu_halt(void); 548 void cpu_halt_others(void); 549 void cpu_pause(struct reg *); 550 void cpu_pause_others(void); 551 void cpu_resume(int); 552 void cpu_resume_others(void); 553 int cpu_is_paused(int); 554 void cpu_debug_dump(void); 555 556 extern volatile __cpuset_t cpus_running; 557 extern volatile __cpuset_t cpus_hatched; 558 extern volatile __cpuset_t cpus_paused; 559 extern volatile __cpuset_t cpus_resumed; 560 extern volatile __cpuset_t cpus_halted; 561 #endif 562 563 /* copy.S */ 564 int32_t kfetch_32(volatile uint32_t *, uint32_t); 565 int8_t ufetch_int8(void *); 566 int16_t ufetch_int16(void *); 567 int32_t ufetch_int32(void *); 568 uint8_t ufetch_uint8(void *); 569 uint16_t ufetch_uint16(void *); 570 uint32_t ufetch_uint32(void *); 571 int8_t ufetch_int8_intrsafe(void *); 572 int16_t ufetch_int16_intrsafe(void *); 573 int32_t ufetch_int32_intrsafe(void *); 574 uint8_t ufetch_uint8_intrsafe(void *); 575 uint16_t ufetch_uint16_intrsafe(void *); 576 uint32_t ufetch_uint32_intrsafe(void *); 577 #ifdef _LP64 578 int64_t ufetch_int64(void *); 579 uint64_t ufetch_uint64(void *); 580 int64_t ufetch_int64_intrsafe(void *); 581 uint64_t ufetch_uint64_intrsafe(void *); 582 #endif 583 char ufetch_char(void *); 584 short ufetch_short(void *); 585 int ufetch_int(void *); 586 long ufetch_long(void *); 587 char ufetch_char_intrsafe(void *); 588 short ufetch_short_intrsafe(void *); 589 int ufetch_int_intrsafe(void *); 590 long ufetch_long_intrsafe(void *); 591 592 u_char ufetch_uchar(void *); 593 u_short ufetch_ushort(void *); 594 u_int ufetch_uint(void *); 595 u_long ufetch_ulong(void *); 596 u_char ufetch_uchar_intrsafe(void *); 597 u_short ufetch_ushort_intrsafe(void *); 598 u_int ufetch_uint_intrsafe(void *); 599 u_long ufetch_ulong_intrsafe(void *); 600 void *ufetch_ptr(void *); 601 602 int ustore_int8(void *, int8_t); 603 int ustore_int16(void *, int16_t); 604 int ustore_int32(void *, int32_t); 605 int ustore_uint8(void *, uint8_t); 606 int ustore_uint16(void *, uint16_t); 607 int ustore_uint32(void *, uint32_t); 608 int ustore_int8_intrsafe(void *, int8_t); 609 int ustore_int16_intrsafe(void *, int16_t); 610 int ustore_int32_intrsafe(void *, int32_t); 611 int ustore_uint8_intrsafe(void *, uint8_t); 612 int ustore_uint16_intrsafe(void *, uint16_t); 613 int ustore_uint32_intrsafe(void *, uint32_t); 614 #ifdef _LP64 615 int ustore_int64(void *, int64_t); 616 int ustore_uint64(void *, uint64_t); 617 int ustore_int64_intrsafe(void *, int64_t); 618 int ustore_uint64_intrsafe(void *, uint64_t); 619 #endif 620 int ustore_char(void *, char); 621 int ustore_char_intrsafe(void *, char); 622 int ustore_short(void *, short); 623 int ustore_short_intrsafe(void *, short); 624 int ustore_int(void *, int); 625 int ustore_int_intrsafe(void *, int); 626 int ustore_long(void *, long); 627 int ustore_long_intrsafe(void *, long); 628 int ustore_uchar(void *, u_char); 629 int ustore_uchar_intrsafe(void *, u_char); 630 int ustore_ushort(void *, u_short); 631 int ustore_ushort_intrsafe(void *, u_short); 632 int ustore_uint(void *, u_int); 633 int ustore_uint_intrsafe(void *, u_int); 634 int ustore_ulong(void *, u_long); 635 int ustore_ulong_intrsafe(void *, u_long); 636 int ustore_ptr(void *, void *); 637 int ustore_ptr_intrsafe(void *, void *); 638 639 int ustore_uint32_isync(void *, uint32_t); 640 641 /* trap.c */ 642 void netintr(void); 643 int kdbpeek(vaddr_t); 644 645 /* mips_dsp.c */ 646 void dsp_init(void); 647 void dsp_discard(void); 648 void dsp_load(void); 649 void dsp_save(void); 650 bool dsp_used_p(void); 651 extern const pcu_ops_t mips_dsp_ops; 652 653 /* mips_fpu.c */ 654 void fpu_init(void); 655 void fpu_discard(void); 656 void fpu_load(void); 657 void fpu_save(void); 658 bool fpu_used_p(void); 659 extern const pcu_ops_t mips_fpu_ops; 660 661 /* mips_machdep.c */ 662 void dumpsys(void); 663 int savectx(struct pcb *); 664 void cpu_identify(device_t); 665 666 /* locore*.S */ 667 int badaddr(void *, size_t); 668 int badaddr64(uint64_t, size_t); 669 670 /* vm_machdep.c */ 671 void * cpu_uarea_alloc(bool); 672 bool cpu_uarea_free(void *); 673 void cpu_proc_fork(struct proc *, struct proc *); 674 vaddr_t cpu_lwp_pc(struct lwp *); 675 int ioaccess(vaddr_t, paddr_t, vsize_t); 676 int iounaccess(vaddr_t, vsize_t); 677 678 #endif /* ! _LOCORE */ 679 #endif /* _KERNEL */ 680 #endif /* _CPU_H_ */ 681
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