| History log of /src/sys/arch/mips/include/cpu.h |
| Revision | | Date | Author | Comments |
| 1.135 |
| 23-Jul-2023 |
skrll | USE __BIT() for CPUF_* flags. NFCI.
|
| 1.134 |
| 31-Jan-2023 |
andvar | fix few typos in comments.
|
| 1.133 |
| 14-Aug-2021 |
ryo | Improved the performance of kernel profiling on MULTIPROCESSOR, and possible to get profiling data for each CPU.
In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.
- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.
|
| 1.132 |
| 29-Mar-2021 |
simonb | Include #include <mips/frame.h> to get lwp_trapframe() definition.
Needed for dtrace.
|
| 1.131 |
| 17-Aug-2020 |
mrg | branches: 1.131.2; 1.131.4;
port crash(8) to mips. (most of the kernel side.)
- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
avoid conflicting with the ddb/crash one
- enable dumppcb
some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.
|
| 1.130 |
| 09-Aug-2020 |
skrll | Don't kcpuset_clone every pmap_tlb_shootdown_bystanders. Instead allocate
a kcpuset_t per cpu_info and use that.
|
| 1.129 |
| 26-Jul-2020 |
simonb | #define<tab>
Nuke trailing whitespace.
|
| 1.128 |
| 01-Dec-2019 |
ad | Fix false sharing problems with cpu_info. Identified with tprof(8).
This was a very nice win in my tests on a 48 CPU box.
- Reorganise cpu_data slightly according to usage.
- Put cpu_onproc into struct cpu_info alongside ci_curlwp (now is ci_onproc).
- On x86, put some items in their own cache lines according to usage, like
the IPI bitmask and ci_want_resched.
|
| 1.127 |
| 21-Nov-2019 |
ad | mi_userret(): take care of calling preempt(), set spc_curpriority directly,
and remove MD code that does the same.
|
| 1.126 |
| 16-Sep-2018 |
skrll | interrupt has two 'r's
fix another typo while I'm here (flsah)
|
| 1.125 |
| 22-Aug-2018 |
msaitoh | - Cleanup for dynamic sysctl:
- Remove unused *_NAMES macros for sysctl.
- Remove unused *_MAXID for sysctls.
- Move CTL_MACHDEP sysctl definitions for m68k into m68k/include/cpu.h and
use them on all m68k machines.
|
| 1.124 |
| 07-Mar-2018 |
maya | branches: 1.124.2;
Adjust ci on the second iteration.
Now a MULTIPROCESSOR+LOCKDEBUG ERLITE reaches userland again
|
| 1.123 |
| 22-Jan-2018 |
maya | branches: 1.123.2;
Don't attempt to dereference cpu_infos if ncpus == 0.
Instead use the already initialized cpu_info_store.
(Also, now we assume all ncpus have cpu_infos initialized. seems to work.)
fixes PR port-mips/52940: ERLITE multiprocessor hangs early
|
| 1.122 |
| 16-Dec-2017 |
mrg | CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.
this should fix the new assert in init_main.c.
|
| 1.121 |
| 31-Oct-2016 |
skrll | branches: 1.121.8;
Pre-allocate some kcpuset_ts so that we don't try and allocate in the
wrong context.
|
| 1.120 |
| 16-Jul-2016 |
macallan | move sysctl-related #defines out of #ifdef _KERNEL so userland can see them
now pixman builds again on loongson
|
| 1.119 |
| 11-Jul-2016 |
skrll | branches: 1.119.2;
Remove commented #include
|
| 1.118 |
| 11-Jul-2016 |
matt | Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
|
| 1.117 |
| 11-Jun-2015 |
matt | Define (but not use) separate kernel and user pagetables.
Move to the new names.
|
| 1.116 |
| 10-Jun-2015 |
matt | Transition from __cpuset_t to kcpuset_t *. This brings the local pmap one
step closer to uvm/pmap, its eventual replacement. Tested on ERLITE MP kernel.
|
| 1.115 |
| 07-Jun-2015 |
matt | assembly no longer include <machine/cpu.h>. Instead MIPS_CURLWP is gotten
from regdef.h and everything else from assym.h. <mips/mips_param.h> no
longer include <machine/cpu.h>
|
| 1.114 |
| 06-Jun-2015 |
matt | Reuse the ci_next to hold the nmi exception stack.
|
| 1.113 |
| 02-Jun-2015 |
matt | Fix CPU_INFO_FOREACH which had the MULTIPROCESSOR/!MULTIPROCESSOR definitions
reversed.
|
| 1.112 |
| 01-Jun-2015 |
matt | Rework cavium support in preparation for MULTIPROCESSOR support
|
| 1.111 |
| 28-May-2015 |
matt | Use the lwp_getcpu() inline for curcpu().
|
| 1.110 |
| 02-May-2015 |
matt | Don't define MIPS1/MIPS32/MIPS32R2 if ABI is N32 or N64.
|
| 1.109 |
| 10-Nov-2013 |
christos | branches: 1.109.6;
fix unused
|
| 1.108 |
| 10-Nov-2013 |
christos | use __unused instead of __USE and void cast to mark iterator variable unused
where needed (from phone)
|
| 1.107 |
| 28-Feb-2013 |
macallan | branches: 1.107.6;
add sysctl machdep.loongson-mmi to indicate wether Loongson Multimedia
Instructions are supported
mostly for pixman
|
| 1.106 |
| 22-Sep-2011 |
macallan | branches: 1.106.2; 1.106.12;
support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs
|
| 1.105 |
| 16-Aug-2011 |
matt | Add support for the MIPS DSP ASE (as a second PCU).
|
| 1.104 |
| 31-Jul-2011 |
matt | Add CPU_MIPS_LOONGSON2 flag (rather defining a CPU_ARCH_MIPS3_LOONGSON2).
This is much less intrusive and disruptive.
|
| 1.103 |
| 06-Jul-2011 |
matt | Add
uint32_t kfetch_32(volatile uint32_t *, uint32_t);
which fetches a 32-bit value from a provided addess or returns
an user supplied value on error.
|
| 1.102 |
| 02-May-2011 |
rmind | Extend PCU:
- Add pcu_ops_t::pcu_state_release() operation for PCU_RELEASE case.
- Add pcu_switchpoint() to perform release operation on context switch.
- Sprinkle const, misc. Also, sync MIPS with changes.
Per discussions with matt@.
|
| 1.101 |
| 14-Apr-2011 |
cliff | - MIPS CPU (COP0) watchpoint support moved from db_machdep.h to cpu.h
- CPU watchpoints are per-cpu; add ci_cpuwatch_count, ci_watchpoint_tab[]
to struct cpuinfo
|
| 1.100 |
| 06-Apr-2011 |
matt | Fix LKM/MODULAR case.
|
| 1.99 |
| 15-Mar-2011 |
matt | Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
|
| 1.98 |
| 20-Feb-2011 |
matt | Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
|
| 1.97 |
| 26-Jan-2011 |
pooka | Add support for the Extensible MIPS ("eMIPS") platform. The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.
eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing. eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.
NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman. Microsoft Corporation has
donated full copyright to The NetBSD Foundation.
Platform support for eMIPS is the first part of Microsoft's
contribution. The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.
|
| 1.96 |
| 22-Dec-2010 |
nisimura | branches: 1.96.2; 1.96.4;
PROC_PC() should have been changed to LWP_PC().
|
| 1.95 |
| 23-Jan-2010 |
mrg | branches: 1.95.4;
rename pridtab{}::cpu_name to cpu_displayname.
should fix a build error reported by he@.
|
| 1.94 |
| 14-Dec-2009 |
matt | Merge from matt-nb5-mips64
Merge mips-specific arch files.
|
| 1.93 |
| 27-Nov-2009 |
rmind | - Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.
|
| 1.92 |
| 21-Nov-2009 |
rmind | Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.
|
| 1.91 |
| 21-Oct-2009 |
rmind | Remove uarea swap-out functionality:
- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.
Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).
Discussed on <tech-kern>, reviewed by <ad>.
|
| 1.90 |
| 26-May-2008 |
tsutsui | branches: 1.90.16;
Remove all initialization of obsolete ci_divisor_recip in
mips struct cpu_info and related macroes.
The member was prepared for a hack in MD microtime(9) implementation
but it has been superseded by MI timecounter(9).
|
| 1.89 |
| 27-Feb-2008 |
xtraeme | branches: 1.89.2; 1.89.4; 1.89.6;
Remove CTL_MACHDEP_NAMES, it's not used anywhere.
Ok by martin@.
|
| 1.88 |
| 09-Jan-2008 |
wiz | branches: 1.88.2; 1.88.6;
Fix typo in macro name and comments.
|
| 1.87 |
| 04-Dec-2007 |
he | branches: 1.87.4;
Define the various MIPS* CPU macros also for _STANDALONE in addition
to for _LKM, so that we don't #error out in that case.
This fixes the build for sgimips boot programs, which wants to use
libkern, which now includes the atomic stuff, which for the mips ports
ends up including this file.
"simonb said OK"
|
| 1.86 |
| 03-Dec-2007 |
ad | branches: 1.86.2;
Interrupt handling changes, in discussion since February:
- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.
|
| 1.85 |
| 19-Oct-2007 |
ad | branches: 1.85.2;
Merge from vmlocking: add CPU_INFO_ITERATOR.
|
| 1.84 |
| 17-Oct-2007 |
garbled | Merge the ppcoea-renovation branch to HEAD.
This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.
TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.
NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
|
| 1.83 |
| 04-Aug-2007 |
ad | branches: 1.83.2; 1.83.6;
Add ci_cpuid where it's missing.
|
| 1.82 |
| 17-May-2007 |
yamt | branches: 1.82.2; 1.82.4; 1.82.8;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.
from doc/BRANCHES:
idle lwp, and some changes depending on it.
1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
|
| 1.81 |
| 21-Feb-2007 |
simonb | branches: 1.81.4; 1.81.6; 1.81.12;
Fix a tyop.
|
| 1.80 |
| 16-Feb-2007 |
oster | branches: 1.80.2;
Fix typo from newlock2 merge, allowing MIPS64 to build again.
|
| 1.79 |
| 16-Feb-2007 |
ad | Remove spllowersoftclock() and CLKF_BASEPRI(), and always dispatch callouts
via a soft interrupt. In the near future, softclock will be run from process
context.
|
| 1.78 |
| 09-Feb-2007 |
ad | Merge newlock2 to head.
|
| 1.77 |
| 23-Mar-2006 |
tsutsui | branches: 1.77.8;
include/cpu.h: make sure MIPS3_PLUS properly defined even if _LOCORE is defined
mips/fp.S: include <mips/cpu.h> for #ifdef MIPS3_PLUS
Closes PR port-mips/27298.
|
| 1.76 |
| 24-Dec-2005 |
perry | branches: 1.76.4; 1.76.6; 1.76.8; 1.76.10; 1.76.12;
bare asm -> __asm
|
| 1.75 |
| 11-Dec-2005 |
christos | merge ktrace-lwp.
|
| 1.74 |
| 05-Nov-2005 |
tsutsui | Make MIPS3_PG_SHIFT a variable and initialize it accordingly
in mips_vector_init() if options MIPS3_4100 is specified
so that kernels which have options MIPS3_4100 also work
on other MIPS3 CPUs.
XXX: now should we rename options MIPS3_4100 to options ENABLE_MIPS_R4100,
XXX: or just make MIPS3_PG_SHIFT always a variable?
|
| 1.73 |
| 22-Sep-2004 |
yamt | branches: 1.73.10; 1.73.12; 1.73.18;
move some per-cpu data definitions to MI place so that they can be modified
without touching all ports. discussed on tech-kern@.
|
| 1.72 |
| 04-Jan-2004 |
jdolecek | Rearrange process exit path to avoid need to free resources from different
process context ('reaper').
From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
as FPU state), and is the last potentially blocking operation;
all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
for both 'process' and 'lwp' exit
uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.
MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.
g/c now unneeded routines and variables, including the reaper kernel thread
|
| 1.71 |
| 07-Aug-2003 |
agc | Move UCB-licensed code from 4-clause to 3-clause licence.
Patches provided by Joel Baker in PR 22364, verified by myself.
|
| 1.70 |
| 17-Jan-2003 |
thorpej | branches: 1.70.2;
Merge the nathanw_sa branch.
|
| 1.69 |
| 17-Dec-2002 |
simonb | Add support for caches where the data cache is fully coherent, and
either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.
|
| 1.68 |
| 24-Nov-2002 |
simonb | Move the curpcb and segbase extern decls to cpu.h to better group together
what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
|
| 1.67 |
| 05-Aug-2002 |
shin | ++CPU_MAXID for CPU_LLSC.
|
| 1.66 |
| 04-Aug-2002 |
gmcgarry | Add sysctl variable to represent native CPU support for LL/SC instructions.
|
| 1.65 |
| 23-Jun-2002 |
manu | Typo
|
| 1.64 |
| 04-Jun-2002 |
simonb | 3 ports are now using the reciprocal count divisor code now, move it
to <mips/cpu.h>, and add MIPS_SET_CI_RECIPRICAL and MIPS_COUNT_TO_MHZ
macros to use it.
|
| 1.63 |
| 01-Jun-2002 |
simonb | Add two new cpu capability flags: CPU_MIPS_USE_WAIT for CPUs that use a
"wait" instruction based cpu_idle(), and CPU_MIPS_NO_WAIT for specific
CPUs that don't use this (applicable to mips32/64 mainly).
|
| 1.62 |
| 05-Apr-2002 |
simonb | branches: 1.62.2;
Add a "CPU_MIPS_DOUBLE_COUNT" flag for CPUs where the cp0 count register
ticks over at half the CPU clock speed, and set this flag for the known
CPUs with this behaviour. Better names for this flag gratefully accepted!
Also adjust comment about known R4000/R4400 revisions.
|
| 1.61 |
| 03-Apr-2002 |
simonb | Add prototype for badaddr64().
|
| 1.60 |
| 19-Mar-2002 |
simonb | Define all CPU types if _LKM is defined; fixes problems building LKM's
as noted by FUKAUMI Naoki on port-mips.
|
| 1.59 |
| 06-Mar-2002 |
simonb | Add a field for the reciprocal of the divisor delay for use by microtime.
|
| 1.58 |
| 05-Mar-2002 |
simonb | Add support for MIPS32 and MIPS64 architectures:
- Clean up (somewhat) mips1 vs mips3+ configuration.
XXX: this is still quite messy.
- Add cpu frequency info to struct cpu_info.
- ANSIfy.
|
| 1.57 |
| 14-Nov-2001 |
thorpej | branches: 1.57.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
|
| 1.56 |
| 16-Oct-2001 |
uch | branches: 1.56.2;
R5900 support.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
|
| 1.55 |
| 04-Sep-2001 |
simonb | Oops, <sys/sched.h> isn't asm safe, move inside an "#ifndef LOCORE" block.
|
| 1.54 |
| 04-Sep-2001 |
simonb | May as well include <mips/cpuregs.h> in <mips/cpu.h> once rather than
in every MIPS port's <machine/cpu.h>.
|
| 1.53 |
| 04-Sep-2001 |
simonb | Centralise struct cpu_info declaration and related info to <mips/cpu.h>.
|
| 1.52 |
| 14-Jun-2001 |
thorpej | branches: 1.52.2;
Don't need to prototype child_return() here, it's in <sys/proc.h>.
|
| 1.51 |
| 11-Jun-2001 |
wiz | Fix various misspellings of compatible/compatibility.
|
| 1.50 |
| 14-Jan-2001 |
thorpej | branches: 1.50.2;
Make the astpending flag per-process.
|
| 1.49 |
| 14-Jan-2001 |
thorpej | - Make ast() loop around astpending; it's possible for a new
AST to be posted when delivering signals, or after a process
is preempted.
- Move all signal posting to ast(). userret() is now a one-liner.
|
| 1.48 |
| 11-Jan-2001 |
thorpej | Mmm, dependency problems. Add a cast to make PROC_PC() actually
work.
|
| 1.47 |
| 11-Jan-2001 |
thorpej | Modeled after mycroft's changes to the Alpha port, add PROC_PC() to
get profiling out of userret(), and move the preemption check to ast().
|
| 1.46 |
| 05-Oct-2000 |
cgd | always have to declare cpu_arch and the related constants (since setting
it isn't conditionalized). (d'oh!)
|
| 1.45 |
| 05-Oct-2000 |
cgd | tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).
|
| 1.44 |
| 25-Aug-2000 |
thorpej | Make need_resched() take a "struct cpu_info *" argument. This
causes gives a primitive form of processor affinity. Its use in
roundrobin() still needs some work.
|
| 1.43 |
| 13-Jul-2000 |
jeffs | Add comment that overriding the sysctl defines in machine/cpu.h
breaks userland binary compatiabiltiy between mips ports. Move
check down so common values are always defined here.
|
| 1.42 |
| 11-Jul-2000 |
jeffs | Only define machdep sysctls if CPU_MAXID is not defined by machine/cpu.h.
This lets mips ports have additional machdep sysctl. Define CPUISMIPS3
for MIPS1+MIPS2 as cpu_arch >= 3 to support mips4. Add cpu_intr()
prototype so this is defined in one place.
|
| 1.41 |
| 30-May-2000 |
nisimura | branches: 1.41.2;
savefpregs() and loadfpregs() are defined in mips_machdep.c
|
| 1.40 |
| 26-May-2000 |
thorpej | branches: 1.40.2;
First sweep at scheduler state cleanup. Collect MI scheduler
state into global and per-CPU scheduler state:
- Global state: sched_qs (run queues), sched_whichqs (bitmap
of non-empty run queues), sched_slpque (sleep queues).
NOTE: These may collectively move into a struct schedstate
at some point in the future.
- Per-CPU state, struct schedstate_percpu: spc_runtime
(time process on this CPU started running), spc_flags
(replaces struct proc's p_schedflags), and
spc_curpriority (usrpri of processes on this CPU).
- Every platform must now supply a struct cpu_info and
a curcpu() macro. Simplify existing cpu_info declarations
where appropriate.
- All references to per-CPU scheduler state now made through
curcpu(). NOTE: this will likely be adjusted in the future
after further changes to struct proc are made.
Tested on i386 and Alpha. Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.
|
| 1.39 |
| 15-Apr-2000 |
soda | remove following symbols which became unnecessary in recent cpu_intr() change:
mips_hardware_intr
MIPS3_INTERNAL_TIMER_INTERRUPT
mips3_intr_cycle_count
mips3_timer_delta
|
| 1.38 |
| 11-Apr-2000 |
nisimura | Introduce cpu_intr() whose body is now provided by target ports in
their own ways. Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.
|
| 1.37 |
| 28-Mar-2000 |
simonb | Move fpcurproc declaration to <mips/cpu.h>.
|
| 1.36 |
| 24-Mar-2000 |
soren | Revert previous.
|
| 1.35 |
| 24-Mar-2000 |
soren | Move sysctl definitions from arch/mips to arch/foo.
|
| 1.34 |
| 07-Mar-2000 |
soren | Garbage collect MIPS_SR_INT_ENAB/MIPS_SR_INT_ENA_CUR definitions.
|
| 1.33 |
| 09-Jan-2000 |
simonb | Use the badaddr() prototype in mips/include/cpu.h by including
<machine/cpu.h> in mips/include/mips_param.h. Remove duplicate
badaddr() prototypes from some pmax header files.
|
| 1.32 |
| 10-Aug-1999 |
thorpej | branches: 1.32.2;
Define cpu_number() as discussed on tech-smp.
|
| 1.31 |
| 20-May-1999 |
lukem | * convert to using MI allocsys(). most ports were using an MD allocsys(),
although a couple still used the old pre-4.4-lite (?) mechanism.
* use format_bytes() to format the various printf()s that print out memory sizes
|
| 1.30 |
| 18-May-1999 |
nisimura | - Move MachSetPID(1) call to pmap_bootstrap() adajacent to kernel pmap
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S
|
| 1.29 |
| 23-Mar-1999 |
simonb | branches: 1.29.4;
Add CPU_BOOTED_KERNEL to CTL_MACHDEP definition.
|
| 1.28 |
| 14-Jan-1999 |
castor | * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.
* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.
* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.
* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
|
| 1.27 |
| 11-Nov-1998 |
thorpej | Changes to support fork_kthread():
- cpu_set_kpc() now takes void *arg third argument, passed to the
entry point.
- cpu_fork() allows parent to be non-curproc iff parent is proc0.
When forking non-curproc, assume its state has already been saved.
- Adjust various pieces of machine-dependent code to account of all of this.
|
| 1.26 |
| 28-Oct-1998 |
jonathan | Add `struct proc;' to keep egcs warnings happy in userland.
XXX why are kernel prototypes visible here at all?
|
| 1.25 |
| 11-Sep-1998 |
jonathan | branches: 1.25.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.
Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.
Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.
* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
|
| 1.24 |
| 25-Feb-1998 |
thorpej | Prototype allocsys(), mips_init_msgbuf(), and mips_init_proc0().
|
| 1.23 |
| 19-Feb-1998 |
thorpej | Prototype dumpsys() and savectx().
|
| 1.22 |
| 22-Jun-1997 |
jonathan | * Change Sprite MACH_xxx prefix to MIPS_xxx.
* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
|
| 1.21 |
| 21-Jun-1997 |
jonathan | More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.
* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S
* Garbage-collect MachHitFlushDCache()
* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
|
| 1.20 |
| 16-Jun-1997 |
jonathan | Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.
NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.
mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.
mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.
mips/include/mips1_pte.h:
mips1 TLB bit definitions.
mips/include/mips3_pte.h:
mips3 TLB bit definitions.
mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.
mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.
mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.
mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)
mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.
mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().
pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
|
| 1.19 |
| 16-Jun-1997 |
jonathan | Garbage-collect redundant declarations:
mips/include/locore.h:
Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
remove cpu_prid definition.
pmax/pmax/machdep.c:
remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
remove local protoypes of HitFlushDCache() functions.
|
| 1.18 |
| 16-Jun-1997 |
jonathan | Yet more merging:
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.
* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
|
| 1.17 |
| 16-Jun-1997 |
jonathan | Garbage-collect #include <machine/machConst.h>.
|
| 1.16 |
| 15-Jun-1997 |
mhitch | From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline().
|
| 1.15 |
| 23-Mar-1996 |
jonathan | fix case typo: CLKF_BASEPRI_R4k to _R4K
|
| 1.14 |
| 23-Mar-1996 |
jonathan | Factor out r3000 versus r4000 differences (CLKF_USERMODE() and CLKF_BASEPRI()),
provide r3k and r4k versions of each, and move to sys/arch/mips/include.
Note in comments where each mips-based port should provide
definitions in its own cpu.h after including this file.
|
| 1.13 |
| 19-Mar-1996 |
jonathan | Add additional mips CPU and FPU ids from Pica port:
IDT r3081 family, r4600, MIPS-IV architecture, others.
|
| 1.12 |
| 28-Jun-1995 |
cgd | remove unused cpu_exec() definitions. moved "broken swap" markers, for
ports that still need it, to types.h.
|
| 1.11 |
| 05-May-1995 |
cgd | define BROKEN_SWAP and/or cpu_swapout as appropriate.
|
| 1.10 |
| 22-Apr-1995 |
christos | - added sunos_machdep.c for sun3, atari, amiga and mac68k.
- changed machdep.c and trap.c to use struct emul.
- remove ep_setup references.
- added struct emul to all emulations.
|
| 1.9 |
| 28-Mar-1995 |
jtc | KERNEL -> _KERNEL
|
| 1.8 |
| 26-Oct-1994 |
cgd | new RCS ID format.
|
| 1.7 |
| 02-Jun-1994 |
glass | fix a few integration bugs, add vmfault debugging, more ultrix stuff
|
| 1.6 |
| 27-May-1994 |
glass | bsd 4.4-lite pmax port as ported to NetBSD
|
| 1.5 |
| 27-May-1994 |
glass | upgrade to bsd 4.4-lite code base. only mod is rcsids
|
| 1.4 |
| 15-Jan-1994 |
deraadt | intrframe -> clockframe
|
| 1.3 |
| 14-Jan-1994 |
deraadt | some pmax updating (Terry Friedrichsen is helping on this now).
|
| 1.2 |
| 15-Oct-1993 |
deraadt | update from rick, tarfile of Oct 11 10:46
|
| 1.1 |
| 12-Oct-1993 |
deraadt | branches: 1.1.1;
Initial revision
|
| 1.1.1.1 |
| 12-Oct-1993 |
deraadt | pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
|
| 1.25.2.4 |
| 16-Nov-1998 |
nisimura | - Step forward to MIPS64 support. Incorporate partially Caster Fu's
patches. Still some work is missing to satisfy his QED 5230 port.
- More symbolic definitions in genassym.cf which improve possible 64bit-ness
of locore_mips{1,3}.S.
- Fix mips3 L1 cache line size detection logic in cpuarch.h as pointed by
Caster.
- Fix a bug in proc_trampoline() code in locore_mips3.S as pointed by Caster.
- Replace vm_offset_t with vaddr_t/paddr_t entirely. Note that
NetBSD/newsmips has purged vm_offset_t too.
- Synchronize various files according to recent changes made in main trunk.
|
| 1.25.2.3 |
| 14-Nov-1998 |
drochner | fix egcs warnings
kdbpeek() prototype cleanup, ala PR port-mips/5252
|
| 1.25.2.2 |
| 30-Oct-1998 |
nisimura | - Make pm.c monochrome-aware and compilable with UVM.
- Make trap.c compilable with UVM.
- Place #ifdef _KERNEL guard in cpu.h
- Make asm.h more MIPS standard-alike while retaining current definitions.
|
| 1.25.2.1 |
| 15-Oct-1998 |
nisimura | - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
|
| 1.29.4.1 |
| 21-Jun-1999 |
thorpej | Sync w/ -current.
|
| 1.32.2.2 |
| 18-Jan-2001 |
bouyer | Sync with head (for UBC+NFS fixes, mostly).
|
| 1.32.2.1 |
| 20-Nov-2000 |
bouyer | Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
|
| 1.40.2.1 |
| 22-Jun-2000 |
minoura | Sync w/ netbsd-1-5-base.
|
| 1.41.2.1 |
| 19-Jul-2000 |
jeffs | Pull up cpu_intr() prototype + platform dependent machdeps.
(approved by thorepj).
|
| 1.50.2.1 |
| 21-Jun-2001 |
nathanw | Catch up to -current.
|
| 1.52.2.5 |
| 06-Sep-2002 |
jdolecek | sync kqueue branch with HEAD
|
| 1.52.2.4 |
| 23-Jun-2002 |
jdolecek | catch up with -current on kqueue branch
|
| 1.52.2.3 |
| 16-Mar-2002 |
jdolecek | Catch up with -current.
|
| 1.52.2.2 |
| 10-Jan-2002 |
thorpej | Sync kqueue branch with -current.
|
| 1.52.2.1 |
| 13-Sep-2001 |
thorpej | Update the kqueue branch to HEAD.
|
| 1.56.2.1 |
| 11-Nov-2001 |
shin | delete obsolete variables.
mips_L2CacheSize
mips_L2CacheIsSnooping
mips_L2CacheMixed
|
| 1.57.2.13 |
| 19-Dec-2002 |
thorpej | Sync with HEAD.
|
| 1.57.2.12 |
| 11-Dec-2002 |
thorpej | Sync with HEAD.
|
| 1.57.2.11 |
| 13-Aug-2002 |
nathanw | Catch up to -current.
|
| 1.57.2.10 |
| 01-Aug-2002 |
nathanw | Catch up to -current.
|
| 1.57.2.9 |
| 02-Jul-2002 |
nathanw | Whitespace.
|
| 1.57.2.8 |
| 24-Jun-2002 |
nathanw | Curproc->curlwp renaming.
Change uses of "curproc->l_proc" back to "curproc", which is more like the
original use. Bare uses of "curproc" are now "curlwp".
"curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL)
so that it is always safe to reference curproc (*de*referencing curproc
is another story, but that's always been true).
|
| 1.57.2.7 |
| 20-Jun-2002 |
nathanw | Catch up to -current.
|
| 1.57.2.6 |
| 17-Apr-2002 |
nathanw | Catch up to -current.
|
| 1.57.2.5 |
| 01-Apr-2002 |
nathanw | Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
|
| 1.57.2.4 |
| 08-Jan-2002 |
nathanw | Catch up to -current.
|
| 1.57.2.3 |
| 08-Dec-2001 |
thorpej | Add a cpu_proc_fork(), called from uvm_proc_fork(), which takes care
of machine-dependent handling a fork() time (this is different from
forking the actual context in an LWP world). #define it away on
platforms which do not need it.
Problem noted by Gregory McGarry.
|
| 1.57.2.2 |
| 17-Nov-2001 |
wdk | Inital support for Scheduler Activation on MIPS architectures.
Compiles for sgimips. Needs more work in locore.S in order to reach
single user and beyond.
|
| 1.57.2.1 |
| 14-Nov-2001 |
wdk | file cpu.h was added on branch nathanw_sa on 2001-11-17 23:43:41 +0000
|
| 1.62.2.3 |
| 31-Aug-2002 |
gehenna | catch up with -current.
|
| 1.62.2.2 |
| 16-Jul-2002 |
gehenna | catch up with -current.
|
| 1.62.2.1 |
| 14-Jul-2002 |
gehenna | catch up with -current.
|
| 1.70.2.5 |
| 10-Nov-2005 |
skrll | Sync with HEAD. Here we go again...
|
| 1.70.2.4 |
| 24-Sep-2004 |
skrll | Sync with HEAD.
|
| 1.70.2.3 |
| 21-Sep-2004 |
skrll | Fix the sync with head I botched.
|
| 1.70.2.2 |
| 18-Sep-2004 |
skrll | Sync with HEAD.
|
| 1.70.2.1 |
| 03-Aug-2004 |
skrll | Sync with HEAD
|
| 1.73.18.1 |
| 19-Apr-2006 |
tron | Pull up following revision(s) (requested by tsutsui in ticket #1259):
sys/arch/mips/mips/fp.S: revision 1.30
sys/arch/mips/include/cpu.h: revision 1.77
include/cpu.h: make sure MIPS3_PLUS properly defined even if _LOCORE is defined
mips/fp.S: include <mips/cpu.h> for #ifdef MIPS3_PLUS
Closes PR port-mips/27298.
|
| 1.73.12.7 |
| 17-Mar-2008 |
yamt | sync with head.
|
| 1.73.12.6 |
| 21-Jan-2008 |
yamt | sync with head
|
| 1.73.12.5 |
| 07-Dec-2007 |
yamt | sync with head
|
| 1.73.12.4 |
| 27-Oct-2007 |
yamt | sync with head.
|
| 1.73.12.3 |
| 03-Sep-2007 |
yamt | sync with head.
|
| 1.73.12.2 |
| 26-Feb-2007 |
yamt | sync with head.
|
| 1.73.12.1 |
| 21-Jun-2006 |
yamt | sync with head.
|
| 1.73.10.1 |
| 19-Apr-2006 |
tron | Pull up following revision(s) (requested by tsutsui in ticket #1259):
sys/arch/mips/mips/fp.S: revision 1.30
sys/arch/mips/include/cpu.h: revision 1.77
include/cpu.h: make sure MIPS3_PLUS properly defined even if _LOCORE is defined
mips/fp.S: include <mips/cpu.h> for #ifdef MIPS3_PLUS
Closes PR port-mips/27298.
|
| 1.76.12.1 |
| 28-Mar-2006 |
tron | Merge 2006-03-28 NetBSD-current into the "peter-altq" branch.
|
| 1.76.10.1 |
| 19-Apr-2006 |
elad | sync with head - hopefully this will work
|
| 1.76.8.1 |
| 01-Apr-2006 |
yamt | sync with head.
|
| 1.76.6.1 |
| 22-Apr-2006 |
simonb | Sync with head.
|
| 1.76.4.1 |
| 09-Sep-2006 |
rpaulo | sync with head
|
| 1.77.8.2 |
| 11-Jan-2007 |
ad | Checkpoint work in progress.
|
| 1.77.8.1 |
| 29-Dec-2006 |
ad | Checkpoint work in progress.
|
| 1.80.2.3 |
| 18-Apr-2007 |
ad | - Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.
|
| 1.80.2.2 |
| 21-Mar-2007 |
ad | Initial changes for MIPS. Not yet working under gxemul.
|
| 1.80.2.1 |
| 27-Feb-2007 |
yamt | - sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
|
| 1.81.12.2 |
| 03-Oct-2007 |
garbled | Sync with HEAD
|
| 1.81.12.1 |
| 22-May-2007 |
matt | Update to HEAD.
|
| 1.81.6.1 |
| 11-Jul-2007 |
mjf | Sync with head.
|
| 1.81.4.3 |
| 03-Dec-2007 |
ad | Sync with HEAD.
|
| 1.81.4.2 |
| 15-Jul-2007 |
ad | Get pmax working.
|
| 1.81.4.1 |
| 27-May-2007 |
ad | Sync with head.
|
| 1.82.8.3 |
| 09-Dec-2007 |
jmcneill | Sync with HEAD.
|
| 1.82.8.2 |
| 26-Oct-2007 |
joerg | Sync with HEAD.
Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.
|
| 1.82.8.1 |
| 04-Aug-2007 |
jmcneill | Sync with HEAD.
|
| 1.82.4.1 |
| 15-Aug-2007 |
skrll | Sync with HEAD.
|
| 1.82.2.2 |
| 07-Aug-2007 |
matt | Sync with HEAD.
|
| 1.82.2.1 |
| 18-Jul-2007 |
matt | Make sure to copy p_md in cpu_proc_fork. Generate an error if MULTIPROCESSOR
is defined.
|
| 1.83.6.1 |
| 25-Oct-2007 |
bouyer | Sync with HEAD.
|
| 1.83.2.3 |
| 23-Mar-2008 |
matt | sync with HEAD
|
| 1.83.2.2 |
| 09-Jan-2008 |
matt | sync with HEAD
|
| 1.83.2.1 |
| 06-Nov-2007 |
matt | sync with HEAD
|
| 1.85.2.2 |
| 18-Feb-2008 |
mjf | Sync with HEAD.
|
| 1.85.2.1 |
| 08-Dec-2007 |
mjf | Sync with HEAD.
|
| 1.86.2.1 |
| 08-Dec-2007 |
ad | Sync with head.
|
| 1.87.4.1 |
| 10-Jan-2008 |
bouyer | Sync with HEAD
|
| 1.88.6.2 |
| 02-Jun-2008 |
mjf | Sync with HEAD.
|
| 1.88.6.1 |
| 03-Apr-2008 |
mjf | Sync with HEAD.
|
| 1.88.2.1 |
| 24-Mar-2008 |
keiichi | sync with head.
|
| 1.89.6.1 |
| 23-Jun-2008 |
wrstuden | Sync w/ -current. 34 merge conflicts to follow.
|
| 1.89.4.2 |
| 11-Mar-2010 |
yamt | sync with head
|
| 1.89.4.1 |
| 04-May-2009 |
yamt | sync with head.
|
| 1.89.2.1 |
| 04-Jun-2008 |
yamt | sync with head
|
| 1.90.16.46 |
| 04-Aug-2012 |
matt | Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does). XXX fix mips1
|
| 1.90.16.45 |
| 09-Jul-2012 |
matt | Use a spinlock to protect the segtab queues. Use union pmap_segmap and
pmap_segmap_t to track -HEAD. Use KERNEL_PID for the same reason.
|
| 1.90.16.44 |
| 27-Feb-2012 |
matt | Count all traps types.
|
| 1.90.16.43 |
| 13-Feb-2012 |
matt | Add mm_md_direct_mapped_virt (inverse of mm_md_direct_mapped_phys). Add a
third argument, vsize_t *, which, if not NULL, returns the amount of virtual
space left in that direct mapped segment.
Get rid most of the individual direct_mapped assert and use the above
routines instead.
Improve kernel core dump code.
|
| 1.90.16.42 |
| 13-Feb-2012 |
matt | Fix emulation to not panic when it encounters something it doesn't like.
(so running crashme won't crash the system).
Centralize the trapsignal processing so we can print out the trap info if
so desired.
Add a machdep.printfataltraps sysctl knob.
|
| 1.90.16.41 |
| 28-Jan-2012 |
matt | Add mm_md_direct_mapped_phys from current.
|
| 1.90.16.40 |
| 19-Jan-2012 |
matt | When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.
The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.
Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
|
| 1.90.16.39 |
| 23-Dec-2011 |
matt | Make CPUISMIPS3 deal with MIPS32R2 and MIPS64R2
Add mips_num_tlb_asids.
Allow a caller to cpu_identify to supply a cpuname (or NULL).
|
| 1.90.16.38 |
| 03-Dec-2011 |
matt | Rework things a bit for the XLR/XLS/XLP TLB. Before dealing with the TLB when
MP on the XL?, disable interrupts and take out a lock to prevent concurrent
updates to the TLB. In the TLB miss and invalid exception handlers, if the
lock is already owned by another CPU, simply return from the exception and
let it continue or restart as appropriate. This prevents concurrent TLB
exceptions in multiple threads from possibly updating the TLB multiple times
for a single address.
|
| 1.90.16.37 |
| 26-May-2011 |
matt | Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP). This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand. If in the miss handlers, the TLB is already
locked let trap deal with the exeception.
|
| 1.90.16.36 |
| 29-Apr-2011 |
matt | Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
|
| 1.90.16.35 |
| 08-Feb-2011 |
cliff | - fix cpu_number() define for non- MULTIPROCESSOR case
|
| 1.90.16.34 |
| 08-Feb-2011 |
cliff | - re-define cpu_number() to now mean ci_index instead of ci_cpuid
- re-define CPU_IS_PRIMARY() to use CPUF_PRIMARY instead of ci_cpuid
|
| 1.90.16.33 |
| 05-Feb-2011 |
cliff | - include cpuset.h, we're using CPUSET_* macros now for cpus_running, cpus_paused, etc.
those data are now type mips_cpuset_t.
- move opt_* includes up above sys/* includes
- add declarations for IPI broadcast, multicast functions
- add declarations for cpu halt, pause, resume, etc functions useful for ddb
|
| 1.90.16.32 |
| 01-Sep-2010 |
matt | Fill cpu_data cpu_{node,core,smt}_id for RMI.
|
| 1.90.16.31 |
| 18-Aug-2010 |
matt | *** empty log message ***
|
| 1.90.16.30 |
| 16-Aug-2010 |
matt | Support user VAs > 4GB (but less than 1TB for now) using a 3 level page table.
Add debug code to help find redundant faults (PMAP_FAULTINFO).
|
| 1.90.16.29 |
| 09-Jun-2010 |
matt | Add support for setting/clearing PK_32 on _LP64 kernels. Make cpu_proc_fork
a real function and add it to vm_machdep.c and let it copy PK_32 on fork.
Properly clear/set PK_32 depending on ABI in setregs. Lack of PX_32 use
tracked down by Cliff Neighbors. [Ya! ps now works!]
|
| 1.90.16.28 |
| 21-Mar-2010 |
cliff | - add ci_next_cp0_clk_intr, ci_count_compare_evcnt, ci_count_compare_missed_evcnt
to struct cpu_info, for per-CPU count/compare clock programming
- add ci_request_ipis to struct cpu_info to allow passing IPI tags
on systems where hardware does not provide such feature; use atomic ops for this.
- declaration of mips_vector_init was moved from here to mips/include/locore.h
|
| 1.90.16.27 |
| 11-Mar-2010 |
matt | Add MP-aware icache support.
|
| 1.90.16.26 |
| 11-Mar-2010 |
matt | Add ci_softc member to cpu_info.
|
| 1.90.16.25 |
| 01-Mar-2010 |
matt | Add secondary processor spinup support (cpu_trampoline is in locore_mips3.S).
Nuke lse_boot_secondary_processors (not needed).
Move cpu_info_store to cpu_subr.C
|
| 1.90.16.24 |
| 28-Feb-2010 |
matt | Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE. Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.
|
| 1.90.16.23 |
| 27-Feb-2010 |
matt | Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.
|
| 1.90.16.22 |
| 25-Feb-2010 |
matt | Remove ci_curpm since it isn't used.
|
| 1.90.16.21 |
| 23-Feb-2010 |
matt | Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine
|
| 1.90.16.20 |
| 16-Feb-2010 |
matt | Add __HAVE_PREEMPTION support for NetBSD/mips. Kill IPL_PREEMPT since it
isn't needed.
|
| 1.90.16.19 |
| 15-Feb-2010 |
matt | Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]
Nested interrupts now work. Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted. spl is handled through the
mips_splsw table. Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE). A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.
Interrupt delivery is completely different. Clock interrupts may interrupt
device interrupts. ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code). cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:
void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
int ipl;
uint32_t pending;
while (ppl < (ipl = splintr(&pending))) {
splx(ipl); /* enable interrupts */
<handle pending interrupts>
(void)splhigh(); /* disable interrupts */
}
}
mipsX_subr.S has been reworked. All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.
The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.
A bunch of debugging code was left conditionalized by PARANOIA. If this
code detects a bug, it will enter an infinite loop. It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.
|
| 1.90.16.18 |
| 05-Feb-2010 |
matt | Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address. This avoids
TLB machinations when swtching to/from the softint thread. This can only
be done for lwp which won't exit.
|
| 1.90.16.17 |
| 01-Feb-2010 |
matt | Merge frame into trapframe. While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it. This is
a step to fast softints and kernel preemption.
trapframe now includes a struct reg instead of a separate array of registers.
|
| 1.90.16.16 |
| 30-Jan-2010 |
matt | Change MIPS_CURLWP from s7 to t8. In a MALTA64 kernel, s6 is used 9155 times
which means the compiler could really use s7 is was free to do so. The least
used temporary was t8 (288 times). Once the kernel was switched to use t8 for
MIPS_CURLWP, s7 was used 7524 times.
Additionally a MALTA32 kernel shrunk by 6205 instructions (24820 bytes) or
about 1% of its text size.
[For some reason, pre-change t1 was never used and post change t2 was never
used. Not sure why.]
|
| 1.90.16.15 |
| 26-Jan-2010 |
matt | Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
|
| 1.90.16.14 |
| 20-Jan-2010 |
matt | Adjust things to the new world order.
|
| 1.90.16.13 |
| 20-Jan-2010 |
matt | Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
|
| 1.90.16.12 |
| 15-Jan-2010 |
matt | Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.
|
| 1.90.16.11 |
| 14-Jan-2010 |
matt | More fixes for the CFATTAL_DECL_NEW changes and rmixl cpucore/cpu changes.
|
| 1.90.16.10 |
| 13-Jan-2010 |
cliff | - cpu_identify() now gets device_t arg
- add CIDFL's for RMI L2, cores, threads attributes
|
| 1.90.16.9 |
| 30-Dec-2009 |
matt | Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.
|
| 1.90.16.8 |
| 23-Nov-2009 |
cliff | fix types in struct clockframe and args to cpu_intr
to be corect for 32 or 64 bit kernel
|
| 1.90.16.7 |
| 15-Nov-2009 |
matt | Fix typo.
|
| 1.90.16.6 |
| 14-Nov-2009 |
matt | switch from fu*/su* to ufetch_*/ustore_*.
|
| 1.90.16.5 |
| 13-Nov-2009 |
cliff | - struct pridtab definition is moved here from mips_machdep.c
- 'mycpu' is now global (was static); uh, a name change might be nice?
- new bit for cpu_flags 'CPU_MIPS_HAVE_MxCR' denotes
mfcr, mtcr instructions are available on this CPU
- new field 'cpu_cp0flags' in pridtab tracks whether (some) CP0 regs exist
- define bits in cpu_cp0flags, including a "USE" bit that,
if clear means cpu_cp0flags can be ignored. common CP0 regs do not
need to be represented here, only newer optional ones are.
- new field 'cpu_cidflags' in pridtab allows defining company-specific flags
- some RMI company specific flags are defined to track chip family
|
| 1.90.16.4 |
| 15-Sep-2009 |
matt | Define MIPS_HAS_LLADDR everywhere it should be.
|
| 1.90.16.3 |
| 15-Sep-2009 |
matt | Add a CPU_MIPS_NO_LLADDR flag / MIPS_HAS_LLADDR macro. And use to determine
whether to printf lladdr COP0 register
|
| 1.90.16.2 |
| 08-Sep-2009 |
matt | Add and optimize MIPS_PHYS_TO_XKPHYS_{UN,}CACHED(pa).
Treat like mips3_pg_cached: add mips3_xkphys_cached which contains the
starting address of the cached XKPHYS region. It also respects SPECIAL_CCA.
|
| 1.90.16.1 |
| 21-Aug-2009 |
matt | Make cpu_proc_fork copy the abi from process to process.
|
| 1.95.4.3 |
| 31-May-2011 |
rmind | sync with head
|
| 1.95.4.2 |
| 21-Apr-2011 |
rmind | sync with head
|
| 1.95.4.1 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.96.4.2 |
| 05-Mar-2011 |
bouyer | Sync with HEAD
|
| 1.96.4.1 |
| 08-Feb-2011 |
bouyer | Sync with HEAD
|
| 1.96.2.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.106.12.3 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.106.12.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.106.12.1 |
| 23-Jun-2013 |
tls | resync from head
|
| 1.106.2.1 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.107.6.1 |
| 18-May-2014 |
rmind | sync with head
|
| 1.109.6.4 |
| 05-Dec-2016 |
skrll | Sync with HEAD
|
| 1.109.6.3 |
| 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.109.6.2 |
| 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.109.6.1 |
| 06-Jun-2015 |
skrll | Sync with HEAD
|
| 1.119.2.2 |
| 04-Nov-2016 |
pgoyette | Sync with HEAD
|
| 1.119.2.1 |
| 26-Jul-2016 |
pgoyette | Sync with HEAD
|
| 1.121.8.1 |
| 26-Feb-2018 |
snj | Pull up following revision(s) (requested by skrll in ticket #566):
sys/arch/arm/include/cpu.h: 1.94
sys/arch/mips/include/cpu.h: 1.122
sys/arch/powerpc/include/cpu.h: 1.103
sys/sys/cpu.h: 1.42
CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.
this should fix the new assert in init_main.c.
--
apply the same change for powerpc as mrg did for arm and mips:
CPU_INFO_FOREACH() must always iterate at least the boot cpu.
document this in sys/cpu.h and fix the arm and mips versions
to check ncpu is non zero before using it as an iterator max.
this should fix the new assert in init_main.c.
|
| 1.123.2.3 |
| 30-Sep-2018 |
pgoyette | Ssync with HEAD
|
| 1.123.2.2 |
| 06-Sep-2018 |
pgoyette | Sync with HEAD
Resolve a couple of conflicts (result of the uimin/uimax changes)
|
| 1.123.2.1 |
| 15-Mar-2018 |
pgoyette | Synch with HEAD
|
| 1.124.2.2 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.124.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.131.4.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.131.2.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
