cpu.h revision 1.110
1 /* $NetBSD: cpu.h,v 1.110 2015/05/02 17:39:31 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #if defined(_KERNEL_OPT) 49 #include "opt_cputype.h" 50 #include "opt_lockdebug.h" 51 #include "opt_multiprocessor.h" 52 #endif 53 54 #ifndef _LOCORE 55 #include <sys/cpu_data.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 59 typedef struct cpu_watchpoint { 60 register_t cw_addr; 61 register_t cw_mask; 62 uint32_t cw_asid; 63 uint32_t cw_mode; 64 } cpu_watchpoint_t; 65 /* (abstract) mode bits */ 66 #define CPUWATCH_WRITE __BIT(0) 67 #define CPUWATCH_READ __BIT(1) 68 #define CPUWATCH_EXEC __BIT(2) 69 #define CPUWATCH_MASK __BIT(3) 70 #define CPUWATCH_ASID __BIT(4) 71 #define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE) 72 73 #define CPUWATCH_MAX 8 /* max possible number of watchpoints */ 74 75 u_int cpuwatch_discover(void); 76 void cpuwatch_free(cpu_watchpoint_t *); 77 cpu_watchpoint_t *cpuwatch_alloc(void); 78 void cpuwatch_set_all(void); 79 void cpuwatch_clr_all(void); 80 void cpuwatch_set(cpu_watchpoint_t *); 81 void cpuwatch_clr(cpu_watchpoint_t *); 82 83 struct cpu_info { 84 struct cpu_data ci_data; /* MI per-cpu data */ 85 struct cpu_info *ci_next; /* Next CPU in list */ 86 struct cpu_softc *ci_softc; /* chip-dependent hook */ 87 device_t ci_dev; /* owning device */ 88 cpuid_t ci_cpuid; /* Machine-level identifier */ 89 u_long ci_cctr_freq; /* cycle counter frequency */ 90 u_long ci_cpu_freq; /* CPU frequency */ 91 u_long ci_cycles_per_hz; /* CPU freq / hz */ 92 u_long ci_divisor_delay; /* for delay/DELAY */ 93 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 94 struct lwp *ci_curlwp; /* currently running lwp */ 95 volatile int ci_want_resched; /* user preemption pending */ 96 int ci_mtx_count; /* negative count of held mutexes */ 97 int ci_mtx_oldspl; /* saved SPL value */ 98 int ci_idepth; /* hardware interrupt depth */ 99 int ci_cpl; /* current [interrupt] priority level */ 100 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 101 struct evcnt ci_ev_count_compare; /* hard clock intr counter */ 102 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */ 103 struct lwp *ci_softlwps[SOFTINT_COUNT]; 104 volatile u_int ci_softints; 105 struct evcnt ci_ev_fpu_loads; /* fpu load counter */ 106 struct evcnt ci_ev_fpu_saves; /* fpu save counter */ 107 struct evcnt ci_ev_dsp_loads; /* dsp load counter */ 108 struct evcnt ci_ev_dsp_saves; /* dsp save counter */ 109 struct evcnt ci_ev_tlbmisses; 110 111 /* 112 * Per-cpu pmap information 113 */ 114 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 115 u_int ci_pmap_asid_cur; /* current ASID */ 116 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 117 union segtab *ci_pmap_seg0tab; 118 #ifdef _LP64 119 union segtab *ci_pmap_segtab; 120 #else 121 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 122 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 123 #endif 124 125 u_int ci_cpuwatch_count; /* number of watchpoints on this CPU */ 126 cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX]; 127 128 #ifdef MULTIPROCESSOR 129 volatile u_long ci_flags; 130 volatile uint64_t ci_request_ipis; 131 /* bitmask of IPIs requested */ 132 /* use on chips where hw cannot pass tag */ 133 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 134 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 135 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 136 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 137 struct evcnt ci_evcnt_synci_activate_rqst; 138 struct evcnt ci_evcnt_synci_onproc_rqst; 139 struct evcnt ci_evcnt_synci_deferred_rqst; 140 struct evcnt ci_evcnt_synci_ipi_rqst; 141 142 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 143 #define CPUF_PRESENT 0x02 /* CPU is present */ 144 #define CPUF_RUNNING 0x04 /* CPU is running */ 145 #define CPUF_PAUSED 0x08 /* CPU is paused */ 146 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 147 #endif 148 149 }; 150 151 #define CPU_INFO_ITERATOR int __unused 152 #define CPU_INFO_FOREACH(cii, ci) \ 153 ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 154 155 #endif /* !_LOCORE */ 156 #endif /* _KERNEL */ 157 158 /* 159 * CTL_MACHDEP definitions. 160 */ 161 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 162 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 163 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 164 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 165 #define CPU_LMMI 5 /* Loongson multimedia instructions */ 166 167 /* 168 * Platform can override, but note this breaks userland compatibility 169 * with other mips platforms. 170 */ 171 #ifndef CPU_MAXID 172 #define CPU_MAXID 5 /* number of valid machdep ids */ 173 #endif 174 175 #ifdef _KERNEL 176 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 177 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 178 #if !defined(__mips_n32) && !defined(__mips_n64) 179 #define MIPS1 1 180 #endif 181 #define MIPS3 1 182 #define MIPS4 1 183 #if !defined(__mips_n32) && !defined(__mips_n64) 184 #define MIPS32 1 185 #define MIPS32R2 1 186 #endif 187 #define MIPS64 1 188 #define MIPS64R2 1 189 #endif 190 191 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 192 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified 193 #endif 194 195 /* Shortcut for MIPS3 or above defined */ 196 #if defined(MIPS3) || defined(MIPS4) \ 197 || defined(MIPS32) || defined(MIPS32R2) \ 198 || defined(MIPS64) || defined(MIPS64R2) 199 200 #define MIPS3_PLUS 1 201 #define __HAVE_CPU_COUNTER 202 #else 203 #undef MIPS3_PLUS 204 #endif 205 206 /* 207 * Macros to find the CPU architecture we're on at run-time, 208 * or if possible, at compile-time. 209 */ 210 211 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 212 #define CPU_ARCH_MIPS1 (1 << 0) 213 #define CPU_ARCH_MIPS2 (1 << 1) 214 #define CPU_ARCH_MIPS3 (1 << 2) 215 #define CPU_ARCH_MIPS4 (1 << 3) 216 #define CPU_ARCH_MIPS5 (1 << 4) 217 #define CPU_ARCH_MIPS32 (1 << 5) 218 #define CPU_ARCH_MIPS64 (1 << 6) 219 #define CPU_ARCH_MIPS32R2 (1 << 7) 220 #define CPU_ARCH_MIPS64R2 (1 << 8) 221 222 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 223 #define MIPS_CURLWP $24 224 #define MIPS_CURLWP_QUOTED "$24" 225 #define MIPS_CURLWP_LABEL _L_T8 226 #define MIPS_CURLWP_REG _R_T8 227 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 228 229 #ifndef _LOCORE 230 231 extern struct cpu_info cpu_info_store; 232 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 233 234 #define curlwp mips_curlwp 235 #define curcpu() (curlwp->l_cpu) 236 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 237 #ifdef MULTIPROCESSOR 238 #define cpu_number() (curcpu()->ci_index) 239 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 240 #else 241 #define cpu_number() (0) 242 #define CPU_IS_PRIMARY(ci) (true) 243 #endif 244 245 /* XXX simonb 246 * Should the following be in a cpu_info type structure? 247 * And how many of these are per-cpu vs. per-system? (Ie, 248 * we can assume that all cpus have the same mmu-type, but 249 * maybe not that all cpus run at the same clock speed. 250 * Some SGI's apparently support R12k and R14k in the same 251 * box.) 252 */ 253 struct mips_options { 254 const struct pridtab *mips_cpu; 255 256 u_int mips_cpu_arch; 257 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 258 u_int mips_cpu_flags; 259 u_int mips_num_tlb_entries; 260 mips_prid_t mips_cpu_id; 261 mips_prid_t mips_fpu_id; 262 bool mips_has_r4k_mmu; 263 bool mips_has_llsc; 264 u_int mips3_pg_shift; 265 u_int mips3_pg_cached; 266 u_int mips3_cca_devmem; 267 #ifdef MIPS3_PLUS 268 #ifdef _LP64 269 uint64_t mips3_xkphys_cached; 270 #endif 271 uint64_t mips3_tlb_vpn_mask; 272 uint64_t mips3_tlb_pfn_mask; 273 uint32_t mips3_tlb_pg_mask; 274 #endif 275 }; 276 extern struct mips_options mips_options; 277 278 #define CPU_MIPS_R4K_MMU 0x0001 279 #define CPU_MIPS_NO_LLSC 0x0002 280 #define CPU_MIPS_CAUSE_IV 0x0004 281 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 282 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 283 #define CPU_MIPS_CACHED_CCA_SHIFT 4 284 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 285 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 286 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 287 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 288 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 289 #define CPU_MIPS_NO_LLADDR 0x1000 290 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 291 #define CPU_MIPS_LOONGSON2 0x4000 292 #define MIPS_NOT_SUPP 0x8000 293 #define CPU_MIPS_HAVE_DSP 0x10000 294 295 #endif /* !_LOCORE */ 296 297 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 298 299 #if defined(MIPS1) 300 301 # define CPUISMIPS3 0 302 # define CPUIS64BITS 0 303 # define CPUISMIPS32 0 304 # define CPUISMIPS32R2 0 305 # define CPUISMIPS64 0 306 # define CPUISMIPS64R2 0 307 # define CPUISMIPSNN 0 308 # define MIPS_HAS_R4K_MMU 0 309 # define MIPS_HAS_CLOCK 0 310 # define MIPS_HAS_LLSC 0 311 # define MIPS_HAS_LLADDR 0 312 # define MIPS_HAS_DSP 0 313 # define MIPS_HAS_LMMI 0 314 315 #elif defined(MIPS3) || defined(MIPS4) 316 317 # define CPUISMIPS3 1 318 # define CPUIS64BITS 1 319 # define CPUISMIPS32 0 320 # define CPUISMIPS32R2 0 321 # define CPUISMIPS64 0 322 # define CPUISMIPS64R2 0 323 # define CPUISMIPSNN 0 324 # define MIPS_HAS_R4K_MMU 1 325 # define MIPS_HAS_CLOCK 1 326 # if defined(_LOCORE) 327 # if !defined(MIPS3_4100) 328 # define MIPS_HAS_LLSC 1 329 # else 330 # define MIPS_HAS_LLSC 0 331 # endif 332 # else /* _LOCORE */ 333 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 334 # endif /* _LOCORE */ 335 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 336 # define MIPS_HAS_DSP 0 337 # if defined(MIPS3_LOONGSON2) 338 # define MIPS_HAS_LMMI ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0) 339 # else 340 # define MIPS_HAS_LMMI 0 341 # endif 342 #elif defined(MIPS32) 343 344 # define CPUISMIPS3 1 345 # define CPUIS64BITS 0 346 # define CPUISMIPS32 1 347 # define CPUISMIPS32R2 0 348 # define CPUISMIPS64 0 349 # define CPUISMIPS64R2 0 350 # define CPUISMIPSNN 1 351 # define MIPS_HAS_R4K_MMU 1 352 # define MIPS_HAS_CLOCK 1 353 # define MIPS_HAS_LLSC 1 354 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 355 # define MIPS_HAS_DSP 0 356 # define MIPS_HAS_LMMI 0 357 358 #elif defined(MIPS32R2) 359 360 # define CPUISMIPS3 1 361 # define CPUIS64BITS 0 362 # define CPUISMIPS32 0 363 # define CPUISMIPS32R2 1 364 # define CPUISMIPS64 0 365 # define CPUISMIPS64R2 0 366 # define CPUISMIPSNN 1 367 # define MIPS_HAS_R4K_MMU 1 368 # define MIPS_HAS_CLOCK 1 369 # define MIPS_HAS_LLSC 1 370 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 371 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 372 # define MIPS_HAS_LMMI 0 373 374 #elif defined(MIPS64) 375 376 # define CPUISMIPS3 1 377 # define CPUIS64BITS 1 378 # define CPUISMIPS32 0 379 # define CPUISMIPS32R2 0 380 # define CPUISMIPS64 1 381 # define CPUISMIPS64R2 0 382 # define CPUISMIPSNN 1 383 # define MIPS_HAS_R4K_MMU 1 384 # define MIPS_HAS_CLOCK 1 385 # define MIPS_HAS_LLSC 1 386 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 387 # define MIPS_HAS_DSP 0 388 # define MIPS_HAS_LMMI 0 389 390 #elif defined(MIPS64R2) 391 392 # define CPUISMIPS3 1 393 # define CPUIS64BITS 1 394 # define CPUISMIPS32 0 395 # define CPUISMIPS32R2 0 396 # define CPUISMIPS64 0 397 # define CPUISMIPS64R2 1 398 # define CPUISMIPSNN 1 399 # define MIPS_HAS_R4K_MMU 1 400 # define MIPS_HAS_CLOCK 1 401 # define MIPS_HAS_LLSC 1 402 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 403 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 404 # define MIPS_HAS_LMMI 0 405 406 #endif 407 408 #else /* run-time test */ 409 410 #ifndef _LOCORE 411 412 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 413 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 414 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 415 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 416 417 /* This test is ... rather bogus */ 418 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 419 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 420 421 /* And these aren't much better while the previous test exists as is... */ 422 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 423 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 424 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 425 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 426 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 427 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 428 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 429 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 430 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 431 432 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 433 434 #else /* !_LOCORE */ 435 436 #define MIPS_HAS_LLSC 0 437 438 #endif /* !_LOCORE */ 439 440 #endif /* run-time test */ 441 442 #ifndef _LOCORE 443 444 /* 445 * definitions of cpu-dependent requirements 446 * referenced in generic code 447 */ 448 449 /* 450 * Send an inter-processor interupt to each other CPU (excludes curcpu()) 451 */ 452 void cpu_broadcast_ipi(int); 453 454 /* 455 * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu()) 456 */ 457 void cpu_multicast_ipi(__cpuset_t, int); 458 459 /* 460 * Send an inter-processor interupt to another CPU. 461 */ 462 int cpu_send_ipi(struct cpu_info *, int); 463 464 /* 465 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 466 */ 467 void cpu_intr(int, vaddr_t, uint32_t); 468 469 /* 470 * Arguments to hardclock and gatherstats encapsulate the previous 471 * machine state in an opaque clockframe. 472 */ 473 struct clockframe { 474 vaddr_t pc; /* program counter at time of interrupt */ 475 uint32_t sr; /* status register at time of interrupt */ 476 bool intr; /* interrupted a interrupt */ 477 }; 478 479 /* 480 * A port must provde CLKF_USERMODE() for use in machine-independent code. 481 * These differ on r4000 and r3000 systems; provide them in the 482 * port-dependent file that includes this one, using the macros below. 483 */ 484 485 /* mips1 versions */ 486 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 487 488 /* mips3 versions */ 489 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 490 491 #define CLKF_PC(framep) ((framep)->pc) 492 #define CLKF_INTR(framep) ((framep)->intr) 493 494 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 495 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 496 #endif 497 498 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 499 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 500 #endif 501 502 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 503 #define CLKF_USERMODE(framep) \ 504 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 505 #endif 506 507 /* 508 * Misc prototypes and variable declarations. 509 */ 510 #define LWP_PC(l) cpu_lwp_pc(l) 511 512 struct proc; 513 struct lwp; 514 struct pcb; 515 struct reg; 516 517 /* 518 * Preempt the current process if in interrupt from user mode, 519 * or after the current trap/syscall if in system mode. 520 */ 521 void cpu_need_resched(struct cpu_info *, int); 522 /* 523 * Notify the current lwp (l) that it has a signal pending, 524 * process as soon as possible. 525 */ 526 void cpu_signotify(struct lwp *); 527 528 /* 529 * Give a profiling tick to the current process when the user profiling 530 * buffer pages are invalid. On the MIPS, request an ast to send us 531 * through trap, marking the proc as needing a profiling tick. 532 */ 533 void cpu_need_proftick(struct lwp *); 534 void cpu_set_curpri(int); 535 536 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 537 538 struct cpu_info * 539 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 540 cpuid_t); 541 void cpu_attach_common(device_t, struct cpu_info *); 542 void cpu_startup_common(void); 543 #ifdef _LP64 544 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 545 #endif 546 547 #ifdef MULTIPROCESSOR 548 void cpu_hatch(struct cpu_info *ci); 549 void cpu_trampoline(void); 550 void cpu_boot_secondary_processors(void); 551 void cpu_halt(void); 552 void cpu_halt_others(void); 553 void cpu_pause(struct reg *); 554 void cpu_pause_others(void); 555 void cpu_resume(int); 556 void cpu_resume_others(void); 557 int cpu_is_paused(int); 558 void cpu_debug_dump(void); 559 560 extern volatile __cpuset_t cpus_running; 561 extern volatile __cpuset_t cpus_hatched; 562 extern volatile __cpuset_t cpus_paused; 563 extern volatile __cpuset_t cpus_resumed; 564 extern volatile __cpuset_t cpus_halted; 565 #endif 566 567 /* copy.S */ 568 int32_t kfetch_32(volatile uint32_t *, uint32_t); 569 int8_t ufetch_int8(void *); 570 int16_t ufetch_int16(void *); 571 int32_t ufetch_int32(void *); 572 uint8_t ufetch_uint8(void *); 573 uint16_t ufetch_uint16(void *); 574 uint32_t ufetch_uint32(void *); 575 int8_t ufetch_int8_intrsafe(void *); 576 int16_t ufetch_int16_intrsafe(void *); 577 int32_t ufetch_int32_intrsafe(void *); 578 uint8_t ufetch_uint8_intrsafe(void *); 579 uint16_t ufetch_uint16_intrsafe(void *); 580 uint32_t ufetch_uint32_intrsafe(void *); 581 #ifdef _LP64 582 int64_t ufetch_int64(void *); 583 uint64_t ufetch_uint64(void *); 584 int64_t ufetch_int64_intrsafe(void *); 585 uint64_t ufetch_uint64_intrsafe(void *); 586 #endif 587 char ufetch_char(void *); 588 short ufetch_short(void *); 589 int ufetch_int(void *); 590 long ufetch_long(void *); 591 char ufetch_char_intrsafe(void *); 592 short ufetch_short_intrsafe(void *); 593 int ufetch_int_intrsafe(void *); 594 long ufetch_long_intrsafe(void *); 595 596 u_char ufetch_uchar(void *); 597 u_short ufetch_ushort(void *); 598 u_int ufetch_uint(void *); 599 u_long ufetch_ulong(void *); 600 u_char ufetch_uchar_intrsafe(void *); 601 u_short ufetch_ushort_intrsafe(void *); 602 u_int ufetch_uint_intrsafe(void *); 603 u_long ufetch_ulong_intrsafe(void *); 604 void *ufetch_ptr(void *); 605 606 int ustore_int8(void *, int8_t); 607 int ustore_int16(void *, int16_t); 608 int ustore_int32(void *, int32_t); 609 int ustore_uint8(void *, uint8_t); 610 int ustore_uint16(void *, uint16_t); 611 int ustore_uint32(void *, uint32_t); 612 int ustore_int8_intrsafe(void *, int8_t); 613 int ustore_int16_intrsafe(void *, int16_t); 614 int ustore_int32_intrsafe(void *, int32_t); 615 int ustore_uint8_intrsafe(void *, uint8_t); 616 int ustore_uint16_intrsafe(void *, uint16_t); 617 int ustore_uint32_intrsafe(void *, uint32_t); 618 #ifdef _LP64 619 int ustore_int64(void *, int64_t); 620 int ustore_uint64(void *, uint64_t); 621 int ustore_int64_intrsafe(void *, int64_t); 622 int ustore_uint64_intrsafe(void *, uint64_t); 623 #endif 624 int ustore_char(void *, char); 625 int ustore_char_intrsafe(void *, char); 626 int ustore_short(void *, short); 627 int ustore_short_intrsafe(void *, short); 628 int ustore_int(void *, int); 629 int ustore_int_intrsafe(void *, int); 630 int ustore_long(void *, long); 631 int ustore_long_intrsafe(void *, long); 632 int ustore_uchar(void *, u_char); 633 int ustore_uchar_intrsafe(void *, u_char); 634 int ustore_ushort(void *, u_short); 635 int ustore_ushort_intrsafe(void *, u_short); 636 int ustore_uint(void *, u_int); 637 int ustore_uint_intrsafe(void *, u_int); 638 int ustore_ulong(void *, u_long); 639 int ustore_ulong_intrsafe(void *, u_long); 640 int ustore_ptr(void *, void *); 641 int ustore_ptr_intrsafe(void *, void *); 642 643 int ustore_uint32_isync(void *, uint32_t); 644 645 /* trap.c */ 646 void netintr(void); 647 int kdbpeek(vaddr_t); 648 649 /* mips_dsp.c */ 650 void dsp_init(void); 651 void dsp_discard(void); 652 void dsp_load(void); 653 void dsp_save(void); 654 bool dsp_used_p(void); 655 extern const pcu_ops_t mips_dsp_ops; 656 657 /* mips_fpu.c */ 658 void fpu_init(void); 659 void fpu_discard(void); 660 void fpu_load(void); 661 void fpu_save(void); 662 bool fpu_used_p(void); 663 extern const pcu_ops_t mips_fpu_ops; 664 665 /* mips_machdep.c */ 666 void dumpsys(void); 667 int savectx(struct pcb *); 668 void cpu_identify(device_t); 669 670 /* locore*.S */ 671 int badaddr(void *, size_t); 672 int badaddr64(uint64_t, size_t); 673 674 /* vm_machdep.c */ 675 void * cpu_uarea_alloc(bool); 676 bool cpu_uarea_free(void *); 677 void cpu_proc_fork(struct proc *, struct proc *); 678 vaddr_t cpu_lwp_pc(struct lwp *); 679 int ioaccess(vaddr_t, paddr_t, vsize_t); 680 int iounaccess(vaddr_t, vsize_t); 681 682 #endif /* ! _LOCORE */ 683 #endif /* _KERNEL */ 684 #endif /* _CPU_H_ */ 685
Indexes created Mon Sep 29 13:09:55 GMT 2025