cpu.h revision 1.112
1 /* $NetBSD: cpu.h,v 1.112 2015/06/01 22:55:12 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #if defined(_KERNEL_OPT) 49 #include "opt_cputype.h" 50 #include "opt_lockdebug.h" 51 #include "opt_multiprocessor.h" 52 #endif 53 54 #ifndef _LOCORE 55 #include <sys/cpu_data.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 59 typedef struct cpu_watchpoint { 60 register_t cw_addr; 61 register_t cw_mask; 62 uint32_t cw_asid; 63 uint32_t cw_mode; 64 } cpu_watchpoint_t; 65 /* (abstract) mode bits */ 66 #define CPUWATCH_WRITE __BIT(0) 67 #define CPUWATCH_READ __BIT(1) 68 #define CPUWATCH_EXEC __BIT(2) 69 #define CPUWATCH_MASK __BIT(3) 70 #define CPUWATCH_ASID __BIT(4) 71 #define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE) 72 73 #define CPUWATCH_MAX 8 /* max possible number of watchpoints */ 74 75 u_int cpuwatch_discover(void); 76 void cpuwatch_free(cpu_watchpoint_t *); 77 cpu_watchpoint_t *cpuwatch_alloc(void); 78 void cpuwatch_set_all(void); 79 void cpuwatch_clr_all(void); 80 void cpuwatch_set(cpu_watchpoint_t *); 81 void cpuwatch_clr(cpu_watchpoint_t *); 82 83 struct cpu_info { 84 struct cpu_data ci_data; /* MI per-cpu data */ 85 void *ci_xnext; /* unused */ 86 struct cpu_softc *ci_softc; /* chip-dependent hook */ 87 device_t ci_dev; /* owning device */ 88 cpuid_t ci_cpuid; /* Machine-level identifier */ 89 u_long ci_cctr_freq; /* cycle counter frequency */ 90 u_long ci_cpu_freq; /* CPU frequency */ 91 u_long ci_cycles_per_hz; /* CPU freq / hz */ 92 u_long ci_divisor_delay; /* for delay/DELAY */ 93 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 94 struct lwp *ci_curlwp; /* currently running lwp */ 95 volatile int ci_want_resched; /* user preemption pending */ 96 int ci_mtx_count; /* negative count of held mutexes */ 97 int ci_mtx_oldspl; /* saved SPL value */ 98 int ci_idepth; /* hardware interrupt depth */ 99 int ci_cpl; /* current [interrupt] priority level */ 100 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 101 struct evcnt ci_ev_count_compare; /* hard clock intr counter */ 102 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */ 103 struct lwp *ci_softlwps[SOFTINT_COUNT]; 104 volatile u_int ci_softints; 105 struct evcnt ci_ev_fpu_loads; /* fpu load counter */ 106 struct evcnt ci_ev_fpu_saves; /* fpu save counter */ 107 struct evcnt ci_ev_dsp_loads; /* dsp load counter */ 108 struct evcnt ci_ev_dsp_saves; /* dsp save counter */ 109 struct evcnt ci_ev_tlbmisses; 110 111 /* 112 * Per-cpu pmap information 113 */ 114 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 115 u_int ci_pmap_asid_cur; /* current ASID */ 116 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 117 union segtab *ci_pmap_seg0tab; 118 #ifdef _LP64 119 union segtab *ci_pmap_segtab; 120 #else 121 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 122 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 123 #endif 124 125 u_int ci_cpuwatch_count; /* number of watchpoints on this CPU */ 126 cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX]; 127 128 #ifdef MULTIPROCESSOR 129 volatile u_long ci_flags; 130 volatile uint64_t ci_request_ipis; 131 /* bitmask of IPIs requested */ 132 /* use on chips where hw cannot pass tag */ 133 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 134 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 135 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 136 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 137 struct evcnt ci_evcnt_synci_activate_rqst; 138 struct evcnt ci_evcnt_synci_onproc_rqst; 139 struct evcnt ci_evcnt_synci_deferred_rqst; 140 struct evcnt ci_evcnt_synci_ipi_rqst; 141 142 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 143 #define CPUF_PRESENT 0x02 /* CPU is present */ 144 #define CPUF_RUNNING 0x04 /* CPU is running */ 145 #define CPUF_PAUSED 0x08 /* CPU is paused */ 146 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 147 #endif 148 149 }; 150 151 #ifdef MULTIPROCESSOR 152 #define CPU_INFO_ITERATOR int __unused 153 #define CPU_INFO_FOREACH(cii, ci) \ 154 ci = &cpu_info_store; ci != NULL; ci = NULL 155 #else 156 #define CPU_INFO_ITERATOR int 157 #define CPU_INFO_FOREACH(cii, ci) \ 158 cii = 0; cii < MAXCPUS && (ci = cpu_infos[cii]) != NULL; cii++ 159 #endif 160 161 #endif /* !_LOCORE */ 162 #endif /* _KERNEL */ 163 164 /* 165 * CTL_MACHDEP definitions. 166 */ 167 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 168 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 169 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 170 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 171 #define CPU_LMMI 5 /* Loongson multimedia instructions */ 172 173 /* 174 * Platform can override, but note this breaks userland compatibility 175 * with other mips platforms. 176 */ 177 #ifndef CPU_MAXID 178 #define CPU_MAXID 5 /* number of valid machdep ids */ 179 #endif 180 181 #ifdef _KERNEL 182 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 183 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 184 #if !defined(__mips_n32) && !defined(__mips_n64) 185 #define MIPS1 1 186 #endif 187 #define MIPS3 1 188 #define MIPS4 1 189 #if !defined(__mips_n32) && !defined(__mips_n64) 190 #define MIPS32 1 191 #define MIPS32R2 1 192 #endif 193 #define MIPS64 1 194 #define MIPS64R2 1 195 #endif 196 197 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 198 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified 199 #endif 200 201 /* Shortcut for MIPS3 or above defined */ 202 #if defined(MIPS3) || defined(MIPS4) \ 203 || defined(MIPS32) || defined(MIPS32R2) \ 204 || defined(MIPS64) || defined(MIPS64R2) 205 206 #define MIPS3_PLUS 1 207 #define __HAVE_CPU_COUNTER 208 #else 209 #undef MIPS3_PLUS 210 #endif 211 212 /* 213 * Macros to find the CPU architecture we're on at run-time, 214 * or if possible, at compile-time. 215 */ 216 217 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 218 #define CPU_ARCH_MIPS1 (1 << 0) 219 #define CPU_ARCH_MIPS2 (1 << 1) 220 #define CPU_ARCH_MIPS3 (1 << 2) 221 #define CPU_ARCH_MIPS4 (1 << 3) 222 #define CPU_ARCH_MIPS5 (1 << 4) 223 #define CPU_ARCH_MIPS32 (1 << 5) 224 #define CPU_ARCH_MIPS64 (1 << 6) 225 #define CPU_ARCH_MIPS32R2 (1 << 7) 226 #define CPU_ARCH_MIPS64R2 (1 << 8) 227 228 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 229 #define MIPS_CURLWP $24 230 #define MIPS_CURLWP_QUOTED "$24" 231 #define MIPS_CURLWP_LABEL _L_T8 232 #define MIPS_CURLWP_REG _R_T8 233 #define TF_MIPS_CURLWP(x) TF_REG_T8(x) 234 235 #ifndef _LOCORE 236 237 extern struct cpu_info cpu_info_store; 238 #ifdef MULTIPROCESSOR 239 extern struct cpu_info *cpuid_infos[]; 240 #endif 241 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 242 243 #define curlwp mips_curlwp 244 #define curcpu() lwp_getcpu(curlwp) 245 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 246 #ifdef MULTIPROCESSOR 247 #define cpu_number() (curcpu()->ci_index) 248 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 249 #else 250 #define cpu_number() (0) 251 #define CPU_IS_PRIMARY(ci) (true) 252 #endif 253 254 /* XXX simonb 255 * Should the following be in a cpu_info type structure? 256 * And how many of these are per-cpu vs. per-system? (Ie, 257 * we can assume that all cpus have the same mmu-type, but 258 * maybe not that all cpus run at the same clock speed. 259 * Some SGI's apparently support R12k and R14k in the same 260 * box.) 261 */ 262 struct mips_options { 263 const struct pridtab *mips_cpu; 264 265 u_int mips_cpu_arch; 266 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 267 u_int mips_cpu_flags; 268 u_int mips_num_tlb_entries; 269 mips_prid_t mips_cpu_id; 270 mips_prid_t mips_fpu_id; 271 bool mips_has_r4k_mmu; 272 bool mips_has_llsc; 273 u_int mips3_pg_shift; 274 u_int mips3_pg_cached; 275 u_int mips3_cca_devmem; 276 #ifdef MIPS3_PLUS 277 #ifdef _LP64 278 uint64_t mips3_xkphys_cached; 279 #endif 280 uint64_t mips3_tlb_vpn_mask; 281 uint64_t mips3_tlb_pfn_mask; 282 uint32_t mips3_tlb_pg_mask; 283 #endif 284 }; 285 extern struct mips_options mips_options; 286 287 #define CPU_MIPS_R4K_MMU 0x0001 288 #define CPU_MIPS_NO_LLSC 0x0002 289 #define CPU_MIPS_CAUSE_IV 0x0004 290 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 291 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 292 #define CPU_MIPS_CACHED_CCA_SHIFT 4 293 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 294 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 295 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 296 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 297 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 298 #define CPU_MIPS_NO_LLADDR 0x1000 299 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 300 #define CPU_MIPS_LOONGSON2 0x4000 301 #define MIPS_NOT_SUPP 0x8000 302 #define CPU_MIPS_HAVE_DSP 0x10000 303 304 #endif /* !_LOCORE */ 305 306 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 307 308 #if defined(MIPS1) 309 310 # define CPUISMIPS3 0 311 # define CPUIS64BITS 0 312 # define CPUISMIPS32 0 313 # define CPUISMIPS32R2 0 314 # define CPUISMIPS64 0 315 # define CPUISMIPS64R2 0 316 # define CPUISMIPSNN 0 317 # define MIPS_HAS_R4K_MMU 0 318 # define MIPS_HAS_CLOCK 0 319 # define MIPS_HAS_LLSC 0 320 # define MIPS_HAS_LLADDR 0 321 # define MIPS_HAS_DSP 0 322 # define MIPS_HAS_LMMI 0 323 324 #elif defined(MIPS3) || defined(MIPS4) 325 326 # define CPUISMIPS3 1 327 # define CPUIS64BITS 1 328 # define CPUISMIPS32 0 329 # define CPUISMIPS32R2 0 330 # define CPUISMIPS64 0 331 # define CPUISMIPS64R2 0 332 # define CPUISMIPSNN 0 333 # define MIPS_HAS_R4K_MMU 1 334 # define MIPS_HAS_CLOCK 1 335 # if defined(_LOCORE) 336 # if !defined(MIPS3_4100) 337 # define MIPS_HAS_LLSC 1 338 # else 339 # define MIPS_HAS_LLSC 0 340 # endif 341 # else /* _LOCORE */ 342 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 343 # endif /* _LOCORE */ 344 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 345 # define MIPS_HAS_DSP 0 346 # if defined(MIPS3_LOONGSON2) 347 # define MIPS_HAS_LMMI ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0) 348 # else 349 # define MIPS_HAS_LMMI 0 350 # endif 351 #elif defined(MIPS32) 352 353 # define CPUISMIPS3 1 354 # define CPUIS64BITS 0 355 # define CPUISMIPS32 1 356 # define CPUISMIPS32R2 0 357 # define CPUISMIPS64 0 358 # define CPUISMIPS64R2 0 359 # define CPUISMIPSNN 1 360 # define MIPS_HAS_R4K_MMU 1 361 # define MIPS_HAS_CLOCK 1 362 # define MIPS_HAS_LLSC 1 363 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 364 # define MIPS_HAS_DSP 0 365 # define MIPS_HAS_LMMI 0 366 367 #elif defined(MIPS32R2) 368 369 # define CPUISMIPS3 1 370 # define CPUIS64BITS 0 371 # define CPUISMIPS32 0 372 # define CPUISMIPS32R2 1 373 # define CPUISMIPS64 0 374 # define CPUISMIPS64R2 0 375 # define CPUISMIPSNN 1 376 # define MIPS_HAS_R4K_MMU 1 377 # define MIPS_HAS_CLOCK 1 378 # define MIPS_HAS_LLSC 1 379 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 380 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 381 # define MIPS_HAS_LMMI 0 382 383 #elif defined(MIPS64) 384 385 # define CPUISMIPS3 1 386 # define CPUIS64BITS 1 387 # define CPUISMIPS32 0 388 # define CPUISMIPS32R2 0 389 # define CPUISMIPS64 1 390 # define CPUISMIPS64R2 0 391 # define CPUISMIPSNN 1 392 # define MIPS_HAS_R4K_MMU 1 393 # define MIPS_HAS_CLOCK 1 394 # define MIPS_HAS_LLSC 1 395 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 396 # define MIPS_HAS_DSP 0 397 # define MIPS_HAS_LMMI 0 398 399 #elif defined(MIPS64R2) 400 401 # define CPUISMIPS3 1 402 # define CPUIS64BITS 1 403 # define CPUISMIPS32 0 404 # define CPUISMIPS32R2 0 405 # define CPUISMIPS64 0 406 # define CPUISMIPS64R2 1 407 # define CPUISMIPSNN 1 408 # define MIPS_HAS_R4K_MMU 1 409 # define MIPS_HAS_CLOCK 1 410 # define MIPS_HAS_LLSC 1 411 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 412 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 413 # define MIPS_HAS_LMMI 0 414 415 #endif 416 417 #else /* run-time test */ 418 419 #ifndef _LOCORE 420 421 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 422 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 423 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 424 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 425 426 /* This test is ... rather bogus */ 427 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 428 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 429 430 /* And these aren't much better while the previous test exists as is... */ 431 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 432 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 433 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 434 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 435 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 436 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 437 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 438 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 439 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 440 441 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 442 443 #else /* !_LOCORE */ 444 445 #define MIPS_HAS_LLSC 0 446 447 #endif /* !_LOCORE */ 448 449 #endif /* run-time test */ 450 451 #ifndef _LOCORE 452 453 /* 454 * definitions of cpu-dependent requirements 455 * referenced in generic code 456 */ 457 458 /* 459 * Send an inter-processor interupt to each other CPU (excludes curcpu()) 460 */ 461 void cpu_broadcast_ipi(int); 462 463 /* 464 * Send an inter-processor interupt to CPUs in cpuset (excludes curcpu()) 465 */ 466 void cpu_multicast_ipi(__cpuset_t, int); 467 468 /* 469 * Send an inter-processor interupt to another CPU. 470 */ 471 int cpu_send_ipi(struct cpu_info *, int); 472 473 /* 474 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 475 */ 476 void cpu_intr(int, vaddr_t, uint32_t); 477 478 /* 479 * Arguments to hardclock and gatherstats encapsulate the previous 480 * machine state in an opaque clockframe. 481 */ 482 struct clockframe { 483 vaddr_t pc; /* program counter at time of interrupt */ 484 uint32_t sr; /* status register at time of interrupt */ 485 bool intr; /* interrupted a interrupt */ 486 }; 487 488 /* 489 * A port must provde CLKF_USERMODE() for use in machine-independent code. 490 * These differ on r4000 and r3000 systems; provide them in the 491 * port-dependent file that includes this one, using the macros below. 492 */ 493 494 /* mips1 versions */ 495 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 496 497 /* mips3 versions */ 498 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 499 500 #define CLKF_PC(framep) ((framep)->pc) 501 #define CLKF_INTR(framep) ((framep)->intr) 502 503 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 504 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 505 #endif 506 507 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 508 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 509 #endif 510 511 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 512 #define CLKF_USERMODE(framep) \ 513 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 514 #endif 515 516 /* 517 * Misc prototypes and variable declarations. 518 */ 519 #define LWP_PC(l) cpu_lwp_pc(l) 520 521 struct proc; 522 struct lwp; 523 struct pcb; 524 struct reg; 525 526 /* 527 * Preempt the current process if in interrupt from user mode, 528 * or after the current trap/syscall if in system mode. 529 */ 530 void cpu_need_resched(struct cpu_info *, int); 531 /* 532 * Notify the current lwp (l) that it has a signal pending, 533 * process as soon as possible. 534 */ 535 void cpu_signotify(struct lwp *); 536 537 /* 538 * Give a profiling tick to the current process when the user profiling 539 * buffer pages are invalid. On the MIPS, request an ast to send us 540 * through trap, marking the proc as needing a profiling tick. 541 */ 542 void cpu_need_proftick(struct lwp *); 543 void cpu_set_curpri(int); 544 545 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 546 547 struct cpu_info * 548 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 549 cpuid_t); 550 void cpu_attach_common(device_t, struct cpu_info *); 551 void cpu_startup_common(void); 552 #ifdef _LP64 553 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 554 #endif 555 556 #ifdef MULTIPROCESSOR 557 void cpu_hatch(struct cpu_info *ci); 558 void cpu_trampoline(void); 559 void cpu_boot_secondary_processors(void); 560 void cpu_halt(void); 561 void cpu_halt_others(void); 562 void cpu_pause(struct reg *); 563 void cpu_pause_others(void); 564 void cpu_resume(int); 565 void cpu_resume_others(void); 566 int cpu_is_paused(int); 567 void cpu_debug_dump(void); 568 569 extern volatile __cpuset_t cpus_running; 570 extern volatile __cpuset_t cpus_hatched; 571 extern volatile __cpuset_t cpus_paused; 572 extern volatile __cpuset_t cpus_resumed; 573 extern volatile __cpuset_t cpus_halted; 574 #endif 575 576 /* copy.S */ 577 int32_t kfetch_32(volatile uint32_t *, uint32_t); 578 int8_t ufetch_int8(void *); 579 int16_t ufetch_int16(void *); 580 int32_t ufetch_int32(void *); 581 uint8_t ufetch_uint8(void *); 582 uint16_t ufetch_uint16(void *); 583 uint32_t ufetch_uint32(void *); 584 int8_t ufetch_int8_intrsafe(void *); 585 int16_t ufetch_int16_intrsafe(void *); 586 int32_t ufetch_int32_intrsafe(void *); 587 uint8_t ufetch_uint8_intrsafe(void *); 588 uint16_t ufetch_uint16_intrsafe(void *); 589 uint32_t ufetch_uint32_intrsafe(void *); 590 #ifdef _LP64 591 int64_t ufetch_int64(void *); 592 uint64_t ufetch_uint64(void *); 593 int64_t ufetch_int64_intrsafe(void *); 594 uint64_t ufetch_uint64_intrsafe(void *); 595 #endif 596 char ufetch_char(void *); 597 short ufetch_short(void *); 598 int ufetch_int(void *); 599 long ufetch_long(void *); 600 char ufetch_char_intrsafe(void *); 601 short ufetch_short_intrsafe(void *); 602 int ufetch_int_intrsafe(void *); 603 long ufetch_long_intrsafe(void *); 604 605 u_char ufetch_uchar(void *); 606 u_short ufetch_ushort(void *); 607 u_int ufetch_uint(void *); 608 u_long ufetch_ulong(void *); 609 u_char ufetch_uchar_intrsafe(void *); 610 u_short ufetch_ushort_intrsafe(void *); 611 u_int ufetch_uint_intrsafe(void *); 612 u_long ufetch_ulong_intrsafe(void *); 613 void *ufetch_ptr(void *); 614 615 int ustore_int8(void *, int8_t); 616 int ustore_int16(void *, int16_t); 617 int ustore_int32(void *, int32_t); 618 int ustore_uint8(void *, uint8_t); 619 int ustore_uint16(void *, uint16_t); 620 int ustore_uint32(void *, uint32_t); 621 int ustore_int8_intrsafe(void *, int8_t); 622 int ustore_int16_intrsafe(void *, int16_t); 623 int ustore_int32_intrsafe(void *, int32_t); 624 int ustore_uint8_intrsafe(void *, uint8_t); 625 int ustore_uint16_intrsafe(void *, uint16_t); 626 int ustore_uint32_intrsafe(void *, uint32_t); 627 #ifdef _LP64 628 int ustore_int64(void *, int64_t); 629 int ustore_uint64(void *, uint64_t); 630 int ustore_int64_intrsafe(void *, int64_t); 631 int ustore_uint64_intrsafe(void *, uint64_t); 632 #endif 633 int ustore_char(void *, char); 634 int ustore_char_intrsafe(void *, char); 635 int ustore_short(void *, short); 636 int ustore_short_intrsafe(void *, short); 637 int ustore_int(void *, int); 638 int ustore_int_intrsafe(void *, int); 639 int ustore_long(void *, long); 640 int ustore_long_intrsafe(void *, long); 641 int ustore_uchar(void *, u_char); 642 int ustore_uchar_intrsafe(void *, u_char); 643 int ustore_ushort(void *, u_short); 644 int ustore_ushort_intrsafe(void *, u_short); 645 int ustore_uint(void *, u_int); 646 int ustore_uint_intrsafe(void *, u_int); 647 int ustore_ulong(void *, u_long); 648 int ustore_ulong_intrsafe(void *, u_long); 649 int ustore_ptr(void *, void *); 650 int ustore_ptr_intrsafe(void *, void *); 651 652 int ustore_uint32_isync(void *, uint32_t); 653 654 /* trap.c */ 655 void netintr(void); 656 int kdbpeek(vaddr_t); 657 658 /* mips_dsp.c */ 659 void dsp_init(void); 660 void dsp_discard(void); 661 void dsp_load(void); 662 void dsp_save(void); 663 bool dsp_used_p(void); 664 extern const pcu_ops_t mips_dsp_ops; 665 666 /* mips_fpu.c */ 667 void fpu_init(void); 668 void fpu_discard(void); 669 void fpu_load(void); 670 void fpu_save(void); 671 bool fpu_used_p(void); 672 extern const pcu_ops_t mips_fpu_ops; 673 674 /* mips_machdep.c */ 675 void dumpsys(void); 676 int savectx(struct pcb *); 677 void cpu_identify(device_t); 678 679 /* locore*.S */ 680 int badaddr(void *, size_t); 681 int badaddr64(uint64_t, size_t); 682 683 /* vm_machdep.c */ 684 void * cpu_uarea_alloc(bool); 685 bool cpu_uarea_free(void *); 686 void cpu_proc_fork(struct proc *, struct proc *); 687 vaddr_t cpu_lwp_pc(struct lwp *); 688 int ioaccess(vaddr_t, paddr_t, vsize_t); 689 int iounaccess(vaddr_t, vsize_t); 690 691 #endif /* ! _LOCORE */ 692 #endif /* _KERNEL */ 693 #endif /* _CPU_H_ */ 694
Indexes created Sun Sep 21 20:09:37 GMT 2025