cpu.h revision 1.120 1 /* $NetBSD: cpu.h,v 1.120 2016/07/16 01:59:05 macallan Exp $ */
2
3 /*-
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94
35 */
36
37 #ifndef _CPU_H_
38 #define _CPU_H_
39
40 /*
41 * Exported definitions unique to NetBSD/mips cpu support.
42 */
43
44 #ifdef _LOCORE
45 #error Use assym.h to get definitions from <mips/cpu.h>
46 #endif
47
48 #ifdef _KERNEL
49
50 #if defined(_KERNEL_OPT)
51 #include "opt_cputype.h"
52 #include "opt_lockdebug.h"
53 #include "opt_multiprocessor.h"
54 #endif
55
56 #include <sys/cpu_data.h>
57 #include <sys/device_if.h>
58 #include <sys/evcnt.h>
59 #include <sys/kcpuset.h>
60
61 typedef struct cpu_watchpoint {
62 register_t cw_addr;
63 register_t cw_mask;
64 uint32_t cw_asid;
65 uint32_t cw_mode;
66 } cpu_watchpoint_t;
67
68 /* (abstract) mode bits */
69 #define CPUWATCH_WRITE __BIT(0)
70 #define CPUWATCH_READ __BIT(1)
71 #define CPUWATCH_EXEC __BIT(2)
72 #define CPUWATCH_MASK __BIT(3)
73 #define CPUWATCH_ASID __BIT(4)
74 #define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE)
75
76 #define CPUWATCH_MAX 8 /* max possible number of watchpoints */
77
78 u_int cpuwatch_discover(void);
79 void cpuwatch_free(cpu_watchpoint_t *);
80 cpu_watchpoint_t *cpuwatch_alloc(void);
81 void cpuwatch_set_all(void);
82 void cpuwatch_clr_all(void);
83 void cpuwatch_set(cpu_watchpoint_t *);
84 void cpuwatch_clr(cpu_watchpoint_t *);
85
86 struct cpu_info {
87 struct cpu_data ci_data; /* MI per-cpu data */
88 void *ci_nmi_stack; /* NMI exception stack */
89 struct cpu_softc *ci_softc; /* chip-dependent hook */
90 device_t ci_dev; /* owning device */
91 cpuid_t ci_cpuid; /* Machine-level identifier */
92 u_long ci_cctr_freq; /* cycle counter frequency */
93 u_long ci_cpu_freq; /* CPU frequency */
94 u_long ci_cycles_per_hz; /* CPU freq / hz */
95 u_long ci_divisor_delay; /* for delay/DELAY */
96 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */
97 struct lwp *ci_curlwp; /* currently running lwp */
98 volatile int ci_want_resched; /* user preemption pending */
99 int ci_mtx_count; /* negative count of held mutexes */
100 int ci_mtx_oldspl; /* saved SPL value */
101 int ci_idepth; /* hardware interrupt depth */
102 int ci_cpl; /* current [interrupt] priority level */
103 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */
104 struct evcnt ci_ev_count_compare; /* hard clock intr counter */
105 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */
106 struct lwp *ci_softlwps[SOFTINT_COUNT];
107 volatile u_int ci_softints;
108 struct evcnt ci_ev_fpu_loads; /* fpu load counter */
109 struct evcnt ci_ev_fpu_saves; /* fpu save counter */
110 struct evcnt ci_ev_dsp_loads; /* dsp load counter */
111 struct evcnt ci_ev_dsp_saves; /* dsp save counter */
112 struct evcnt ci_ev_tlbmisses;
113
114 /*
115 * Per-cpu pmap information
116 */
117 int ci_tlb_slot; /* reserved tlb entry for cpu_info */
118 u_int ci_pmap_asid_cur; /* current ASID */
119 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */
120 union pmap_segtab *ci_pmap_segtabs[2];
121 #define ci_pmap_user_segtab ci_pmap_segtabs[0]
122 #define ci_pmap_kern_segtab ci_pmap_segtabs[1]
123 #ifdef _LP64
124 union pmap_segtab *ci_pmap_seg0tabs[2];
125 #define ci_pmap_user_seg0tab ci_pmap_seg0tabs[0]
126 #define ci_pmap_kern_seg0tab ci_pmap_seg0tabs[1]
127 #endif
128 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */
129 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */
130
131 u_int ci_cpuwatch_count; /* number of watchpoints on this CPU */
132 cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX];
133
134 #ifdef MULTIPROCESSOR
135 volatile u_long ci_flags;
136 volatile uint64_t ci_request_ipis;
137 /* bitmask of IPIs requested */
138 /* use on chips where hw cannot pass tag */
139 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */
140 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */
141 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */
142 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/
143 struct evcnt ci_evcnt_synci_activate_rqst;
144 struct evcnt ci_evcnt_synci_onproc_rqst;
145 struct evcnt ci_evcnt_synci_deferred_rqst;
146 struct evcnt ci_evcnt_synci_ipi_rqst;
147
148 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */
149 #define CPUF_PRESENT 0x02 /* CPU is present */
150 #define CPUF_RUNNING 0x04 /* CPU is running */
151 #define CPUF_PAUSED 0x08 /* CPU is paused */
152 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */
153 #endif
154
155 };
156
157 #ifdef MULTIPROCESSOR
158 #define CPU_INFO_ITERATOR int
159 #define CPU_INFO_FOREACH(cii, ci) \
160 cii = 0, ci = cpu_infos[0]; cii < ncpu && (ci = cpu_infos[cii]) != NULL; cii++
161 #else
162 #define CPU_INFO_ITERATOR int __unused
163 #define CPU_INFO_FOREACH(cii, ci) \
164 ci = &cpu_info_store; ci != NULL; ci = NULL
165 #endif
166
167 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
168 // MIPS_CURLWP moved to <mips/regdef.h>
169 #define MIPS_CURLWP_QUOTED "$24"
170 #define MIPS_CURLWP_LABEL _L_T8
171 #define MIPS_CURLWP_REG _R_T8
172
173 extern struct cpu_info cpu_info_store;
174 #ifdef MULTIPROCESSOR
175 extern struct cpu_info *cpuid_infos[];
176 #endif
177 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED);
178
179 #define curlwp mips_curlwp
180 #define curcpu() lwp_getcpu(curlwp)
181 #define curpcb ((struct pcb *)lwp_getpcb(curlwp))
182 #ifdef MULTIPROCESSOR
183 #define cpu_number() (curcpu()->ci_index)
184 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY)
185 #else
186 #define cpu_number() (0)
187 #define CPU_IS_PRIMARY(ci) (true)
188 #endif
189
190 /*
191 * definitions of cpu-dependent requirements
192 * referenced in generic code
193 */
194
195 /*
196 * Send an inter-processor interupt to each other CPU (excludes curcpu())
197 */
198 void cpu_broadcast_ipi(int);
199
200 /*
201 * Send an inter-processor interupt to CPUs in kcpuset (excludes curcpu())
202 */
203 void cpu_multicast_ipi(const kcpuset_t *, int);
204
205 /*
206 * Send an inter-processor interupt to another CPU.
207 */
208 int cpu_send_ipi(struct cpu_info *, int);
209
210 /*
211 * cpu_intr(ppl, pc, status); (most state needed by clockframe)
212 */
213 void cpu_intr(int, vaddr_t, uint32_t);
214
215 /*
216 * Arguments to hardclock and gatherstats encapsulate the previous
217 * machine state in an opaque clockframe.
218 */
219 struct clockframe {
220 vaddr_t pc; /* program counter at time of interrupt */
221 uint32_t sr; /* status register at time of interrupt */
222 bool intr; /* interrupted a interrupt */
223 };
224
225 /*
226 * A port must provde CLKF_USERMODE() for use in machine-independent code.
227 * These differ on r4000 and r3000 systems; provide them in the
228 * port-dependent file that includes this one, using the macros below.
229 */
230 uint32_t cpu_clkf_usermode_mask(void);
231
232 #define CLKF_USERMODE(framep) ((framep)->sr & cpu_clkf_usermode_mask())
233 #define CLKF_PC(framep) ((framep)->pc + 0)
234 #define CLKF_INTR(framep) ((framep)->intr + 0)
235
236 /*
237 * Misc prototypes and variable declarations.
238 */
239 #define LWP_PC(l) cpu_lwp_pc(l)
240
241 struct proc;
242 struct lwp;
243 struct pcb;
244 struct reg;
245
246 /*
247 * Preempt the current process if in interrupt from user mode,
248 * or after the current trap/syscall if in system mode.
249 */
250 void cpu_need_resched(struct cpu_info *, int);
251 /*
252 * Notify the current lwp (l) that it has a signal pending,
253 * process as soon as possible.
254 */
255 void cpu_signotify(struct lwp *);
256
257 /*
258 * Give a profiling tick to the current process when the user profiling
259 * buffer pages are invalid. On the MIPS, request an ast to send us
260 * through trap, marking the proc as needing a profiling tick.
261 */
262 void cpu_need_proftick(struct lwp *);
263 void cpu_set_curpri(int);
264
265 /* VM related hooks */
266 void cpu_boot_secondary_processors(void);
267 void * cpu_uarea_alloc(bool);
268 bool cpu_uarea_free(void *);
269 void cpu_proc_fork(struct proc *, struct proc *);
270 vaddr_t cpu_lwp_pc(struct lwp *);
271 #ifdef _LP64
272 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t);
273 #endif
274
275 #endif /* _KERNEL */
276
277 /*
278 * CTL_MACHDEP definitions.
279 */
280 #define CPU_CONSDEV 1 /* dev_t: console terminal device */
281 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */
282 #define CPU_ROOT_DEVICE 3 /* string: root device name */
283 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */
284 #define CPU_LMMI 5 /* Loongson multimedia instructions */
285
286 /*
287 * Platform can override, but note this breaks userland compatibility
288 * with other mips platforms.
289 */
290 #ifndef CPU_MAXID
291 #define CPU_MAXID 5 /* number of valid machdep ids */
292 #endif
293
294 #endif /* _CPU_H_ */
295