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cpu.h revision 1.13 
      1 /*	$NetBSD: cpu.h,v 1.13 1996/03/19 02:42:28 jonathan Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1992, 1993
      5  *	The Regents of the University of California.  All rights reserved.
      6  *
      7  * This code is derived from software contributed to Berkeley by
      8  * Ralph Campbell and Rick Macklem.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the University of
     21  *	California, Berkeley and its contributors.
     22  * 4. Neither the name of the University nor the names of its contributors
     23  *    may be used to endorse or promote products derived from this software
     24  *    without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36  * SUCH DAMAGE.
     37  *
     38  *	@(#)cpu.h	8.4 (Berkeley) 1/4/94
     39  */
     40 
     41 #ifndef _CPU_H_
     42 #define _CPU_H_
     43 
     44 #include <machine/machConst.h>
     45 
     46 /*
     47  * Exported definitions unique to NetBSD/mips cpu support.
     48  */
     49 
     50 /*
     51  * definitions of cpu-dependent requirements
     52  * referenced in generic code
     53  */
     54 #define	cpu_wait(p)			/* nothing */
     55 #define cpu_set_init_frame(p, fp)	/* nothing */
     56 #define	cpu_swapout(p)			panic("cpu_swapout: can't get here");
     57 
     58 /*
     59  * Arguments to hardclock and gatherstats encapsulate the previous
     60  * machine state in an opaque clockframe.
     61  */
     62 struct clockframe {
     63 	int	pc;	/* program counter at time of interrupt */
     64 	int	sr;	/* status register at time of interrupt */
     65 };
     66 
     67 #define	CLKF_USERMODE(framep)	((framep)->sr & MACH_SR_KU_PREV)
     68 #define	CLKF_BASEPRI(framep)	\
     69 	((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) == 0)
     70 #define	CLKF_PC(framep)		((framep)->pc)
     71 #define	CLKF_INTR(framep)	(0)
     72 
     73 /*
     74  * Preempt the current process if in interrupt from user mode,
     75  * or after the current trap/syscall if in system mode.
     76  */
     77 #define	need_resched()	{ want_resched = 1; aston(); }
     78 
     79 /*
     80  * Give a profiling tick to the current process when the user profiling
     81  * buffer pages are invalid.  On the MIPS, request an ast to send us
     82  * through trap, marking the proc as needing a profiling tick.
     83  */
     84 #define	need_proftick(p)	{ (p)->p_flag |= P_OWEUPC; aston(); }
     85 
     86 /*
     87  * Notify the current process (p) that it has a signal pending,
     88  * process as soon as possible.
     89  */
     90 #define	signotify(p)	aston()
     91 
     92 #define aston()		(astpending = 1)
     93 
     94 int	astpending;	/* need to trap before returning to user mode */
     95 int	want_resched;	/* resched() was called */
     96 
     97 /*
     98  * CPU identification, from PRID register.
     99  */
    100 union cpuprid {
    101 	int	cpuprid;
    102 	struct {
    103 #if BYTE_ORDER == BIG_ENDIAN
    104 		u_int	pad1:16;	/* reserved */
    105 		u_int	cp_imp:8;	/* implementation identifier */
    106 		u_int	cp_majrev:4;	/* major revision identifier */
    107 		u_int	cp_minrev:4;	/* minor revision identifier */
    108 #else
    109 		u_int	cp_minrev:4;	/* minor revision identifier */
    110 		u_int	cp_majrev:4;	/* major revision identifier */
    111 		u_int	cp_imp:8;	/* implementation identifier */
    112 		u_int	pad1:16;	/* reserved */
    113 #endif
    114 	} cpu;
    115 };
    116 
    117 /*
    118  * CTL_MACHDEP definitions.
    119  */
    120 #define	CPU_CONSDEV		1	/* dev_t: console terminal device */
    121 #define	CPU_MAXID		2	/* number of valid machdep ids */
    122 
    123 #define CTL_MACHDEP_NAMES { \
    124 	{ 0, 0 }, \
    125 	{ "console_device", CTLTYPE_STRUCT }, \
    126 }
    127 
    128 
    129 /*
    130  * MIPS CPU types (cp_imp).
    131  */
    132 #define	MIPS_R2000	0x01	/* MIPS R2000 CPU		ISA I   */
    133 #define	MIPS_R3000	0x02	/* MIPS R3000 CPU		ISA I   */
    134 #define	MIPS_R6000	0x03	/* MIPS R6000 CPU		ISA II	*/
    135 #define	MIPS_R4000	0x04	/* MIPS R4000/4400 CPU		ISA III	*/
    136 #define MIPS_R3LSI	0x05	/* LSI Logic R3000 derivate	ISA I	*/
    137 #define	MIPS_R6000A	0x06	/* MIPS R6000A CPU		ISA II	*/
    138 #define	MIPS_R3IDT	0x07	/* IDT R3000 derivate		ISA I	*/
    139 #define	MIPS_R10000	0x09	/* MIPS R10000/T5 CPU		ISA IV  */
    140 #define	MIPS_R4200	0x0a	/* MIPS R4200 CPU (ICE)		ISA III */
    141 #define MIPS_UNKC1	0x0b	/* unnanounced product cpu	ISA III */
    142 #define MIPS_UNKC2	0x0c	/* unnanounced product cpu	ISA III */
    143 #define	MIPS_R8000	0x10	/* MIPS R8000 Blackbird/TFP	ISA IV  */
    144 #define	MIPS_R4600	0x20	/* QED R4600 Orion		ISA III */
    145 #define	MIPS_R3SONY	0x21	/* Sony R3000 based CPU		ISA I   */
    146 #define	MIPS_R3TOSH	0x22	/* Toshiba R3000 based CPU	ISA I	*/
    147 #define	MIPS_R3NKK	0x23	/* NKK R3000 based CPU		ISA I   */
    148 
    149 
    150 /*
    151  * MIPS FPU types
    152  */
    153 #define	MIPS_SOFT	0x00	/* Software emulation		ISA I   */
    154 #define	MIPS_R2360	0x01	/* MIPS R2360 FPC		ISA I   */
    155 #define	MIPS_R2010	0x02	/* MIPS R2010 FPC		ISA I   */
    156 #define	MIPS_R3010	0x03	/* MIPS R3010 FPC		ISA I   */
    157 #define	MIPS_R6010	0x04	/* MIPS R6010 FPC		ISA II  */
    158 #define	MIPS_R4010	0x05	/* MIPS R4000/R4400 FPC		ISA II  */
    159 #define MIPS_R31LSI	0x06	/* LSI Logic derivate		ISA I	*/
    160 #define	MIPS_R10010	0x09	/* MIPS R10000/T5 FPU		ISA IV  */
    161 #define	MIPS_R4210	0x0a	/* MIPS R4200 FPC (ICE)		ISA III */
    162 #define MIPS_UNKF1	0x0b	/* unnanounced product cpu	ISA III */
    163 #define	MIPS_R8000	0x10	/* MIPS R8000 Blackbird/TFP	ISA IV  */
    164 #define	MIPS_R4600	0x20	/* QED R4600 Orion		ISA III */
    165 #define	MIPS_R3SONY	0x21	/* Sony R3000 based FPU		ISA I   */
    166 #define	MIPS_R3TOSH	0x22	/* Toshiba R3000 based FPU	ISA I	*/
    167 #define	MIPS_R3NKK	0x23	/* NKK R3000 based FPU		ISA I   */
    168 
    169 
    170 #ifdef _KERNEL
    171 union	cpuprid cpu;
    172 union	cpuprid fpu;
    173 u_int	machDataCacheSize;
    174 u_int	machInstCacheSize;
    175 extern	struct intr_tab intr_tab[];
    176 #endif
    177 
    178 /*
    179  * Enable realtime clock (always enabled).
    180  */
    181 #define	enablertclock()
    182 
    183 #endif /* _CPU_H_ */
    184