cpu.h revision 1.18
1 /* $NetBSD: cpu.h,v 1.18 1997/06/16 06:17:26 jonathan Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 /* 45 * Exported definitions unique to NetBSD/mips cpu support. 46 */ 47 48 /* 49 * definitions of cpu-dependent requirements 50 * referenced in generic code 51 */ 52 #define cpu_wait(p) /* nothing */ 53 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 54 55 /* 56 * Arguments to hardclock and gatherstats encapsulate the previous 57 * machine state in an opaque clockframe. 58 */ 59 struct clockframe { 60 int pc; /* program counter at time of interrupt */ 61 int sr; /* status register at time of interrupt */ 62 }; 63 64 /* 65 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 66 * in machine-independent code. These differ on r4000 and r3000 systems; 67 * provide them in the port-dependent file that includes this one, using 68 * the macros below. 69 */ 70 71 /* r3000 versions */ 72 #define CLKF_USERMODE_R3K(framep) ((framep)->sr & MACH_SR_KU_PREV) 73 #define CLKF_BASEPRI_R3K(framep) \ 74 ((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) == 0) 75 76 /* r4000 versions */ 77 #define CLKF_USERMODE_R4K(framep) ((framep)->sr & MACH_SR_KSU_USER) 78 #define CLKF_BASEPRI_R4K(framep) \ 79 ((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENAB)) == 0) 80 81 #define CLKF_PC(framep) ((framep)->pc) 82 #define CLKF_INTR(framep) (0) 83 84 #ifdef MIPS3 85 #define CLKF_USERMODE(framep) CLKF_USERMODE_R4K(framep) 86 #define CLKF_BASEPRI(framep) CLKF_BASEPRI_R4K(framep) 87 #else 88 #define CLKF_USERMODE(framep) CLKF_USERMODE_R3K(framep) 89 #define CLKF_BASEPRI(framep) CLKF_BASEPRI_R3K(framep) 90 #endif 91 92 93 /* 94 * Preempt the current process if in interrupt from user mode, 95 * or after the current trap/syscall if in system mode. 96 */ 97 #define need_resched() { want_resched = 1; aston(); } 98 99 /* 100 * Give a profiling tick to the current process when the user profiling 101 * buffer pages are invalid. On the MIPS, request an ast to send us 102 * through trap, marking the proc as needing a profiling tick. 103 */ 104 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 105 106 /* 107 * Notify the current process (p) that it has a signal pending, 108 * process as soon as possible. 109 */ 110 #define signotify(p) aston() 111 112 #define aston() (astpending = 1) 113 114 int astpending; /* need to trap before returning to user mode */ 115 int want_resched; /* resched() was called */ 116 117 /* 118 * CPU identification, from PRID register. 119 */ 120 union cpuprid { 121 int cpuprid; 122 struct { 123 #if BYTE_ORDER == BIG_ENDIAN 124 u_int pad1:16; /* reserved */ 125 u_int cp_imp:8; /* implementation identifier */ 126 u_int cp_majrev:4; /* major revision identifier */ 127 u_int cp_minrev:4; /* minor revision identifier */ 128 #else 129 u_int cp_minrev:4; /* minor revision identifier */ 130 u_int cp_majrev:4; /* major revision identifier */ 131 u_int cp_imp:8; /* implementation identifier */ 132 u_int pad1:16; /* reserved */ 133 #endif 134 } cpu; 135 }; 136 137 /* 138 * CTL_MACHDEP definitions. 139 */ 140 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 141 #define CPU_MAXID 2 /* number of valid machdep ids */ 142 143 #define CTL_MACHDEP_NAMES { \ 144 { 0, 0 }, \ 145 { "console_device", CTLTYPE_STRUCT }, \ 146 } 147 148 149 /* 150 * MIPS CPU types (cp_imp). 151 */ 152 #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 153 #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 154 #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 155 #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 156 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 157 #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 158 #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 159 #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 160 #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 161 #define MIPS_UNKC1 0x0b /* unnanounced product cpu ISA III */ 162 #define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */ 163 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 164 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 165 #define MIPS_R3SONY 0x21 /* Sony R3000 based CPU ISA I */ 166 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 167 #define MIPS_R3NKK 0x23 /* NKK R3000 based CPU ISA I */ 168 169 170 /* 171 * MIPS FPU types 172 */ 173 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 174 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 175 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 176 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 177 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 178 #define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 179 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 180 #define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 181 #define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 182 #define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 183 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 184 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 185 #define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 186 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 187 #define MIPS_R3NKK 0x23 /* NKK R3000 based FPU ISA I */ 188 189 /* 190 * XXX port-dependent code should define cpu_id and fpu_id variables 191 * and machine-dependent cache descriptor variables. 192 */ 193 194 /* 195 * Enable realtime clock (always enabled). 196 */ 197 #define enablertclock() 198 199 #endif /* _CPU_H_ */ 200
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