cpu.h revision 1.27
1 /* $NetBSD: cpu.h,v 1.27 1998/11/11 06:41:27 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 /* 45 * Exported definitions unique to NetBSD/mips cpu support. 46 */ 47 48 /* 49 * Macros to find the CPU architecture we're on at run-time, 50 * or if possible, at compile-time. 51 */ 52 53 #if (MIPS1 + MIPS3) == 1 54 #ifdef MIPS1 55 # define CPUISMIPS3 0 56 #endif /* mips1 */ 57 58 #ifdef MIPS3 59 # define CPUISMIPS3 1 60 #endif /* mips1 */ 61 62 #else /* run-time test */ 63 extern int cpu_arch; 64 #define CPUISMIPS3 (cpu_arch == 3) 65 #endif /* run-time test */ 66 67 /* 68 * definitions of cpu-dependent requirements 69 * referenced in generic code 70 */ 71 #define cpu_wait(p) /* nothing */ 72 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 73 74 /* 75 * Arguments to hardclock and gatherstats encapsulate the previous 76 * machine state in an opaque clockframe. 77 */ 78 struct clockframe { 79 int pc; /* program counter at time of interrupt */ 80 int sr; /* status register at time of interrupt */ 81 }; 82 83 /* 84 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 85 * in machine-independent code. These differ on r4000 and r3000 systems; 86 * provide them in the port-dependent file that includes this one, using 87 * the macros below. 88 */ 89 90 /* mips1 versions */ 91 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 92 #define MIPS1_CLKF_BASEPRI(framep) \ 93 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 94 95 /* mips3 versions */ 96 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 97 #define MIPS3_CLKF_BASEPRI(framep) \ 98 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENAB)) == 0) 99 100 #define CLKF_PC(framep) ((framep)->pc) 101 #define CLKF_INTR(framep) (0) 102 103 #if defined(MIPS3) && !defined(MIPS1) 104 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 105 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 106 #endif 107 108 #if !defined(MIPS3) && defined(MIPS1) 109 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 110 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 111 #endif 112 113 114 #if defined(MIPS3) && defined(MIPS1) 115 #define CLKF_USERMODE(framep) \ 116 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 117 #define CLKF_BASEPRI(framep) \ 118 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 119 #endif 120 121 122 123 /* 124 * Preempt the current process if in interrupt from user mode, 125 * or after the current trap/syscall if in system mode. 126 */ 127 #define need_resched() { want_resched = 1; aston(); } 128 129 /* 130 * Give a profiling tick to the current process when the user profiling 131 * buffer pages are invalid. On the MIPS, request an ast to send us 132 * through trap, marking the proc as needing a profiling tick. 133 */ 134 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 135 136 /* 137 * Notify the current process (p) that it has a signal pending, 138 * process as soon as possible. 139 */ 140 #define signotify(p) aston() 141 142 #define aston() (astpending = 1) 143 144 extern int astpending; /* need to trap before returning to user mode */ 145 extern int want_resched; /* resched() was called */ 146 #ifdef MIPS3 147 extern u_int mips_L2CacheSize; 148 extern int mips_L2CacheIsSnooping; /* L2 cache snoops uncached writes ? */ 149 extern int mips_L2CacheMixed; 150 151 #ifdef MIPS3_INTERNAL_TIMER_INTERRUPT 152 extern u_int32_t mips3_intr_cycle_count; 153 extern u_int32_t mips3_timer_delta; 154 #endif 155 #endif 156 157 /* 158 * CTL_MACHDEP definitions. 159 */ 160 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 161 #define CPU_MAXID 2 /* number of valid machdep ids */ 162 163 #define CTL_MACHDEP_NAMES { \ 164 { 0, 0 }, \ 165 { "console_device", CTLTYPE_STRUCT }, \ 166 } 167 168 /* 169 * Misc prototypes. 170 */ 171 172 struct user; 173 struct proc; 174 175 caddr_t allocsys __P((caddr_t)); 176 void dumpsys __P((void)); 177 int savectx __P((struct user *)); 178 void mips_init_msgbuf __P((void)); 179 void mips_init_proc0 __P((caddr_t)); 180 181 /* locore.S */ 182 extern void savefpregs __P((struct proc *)); 183 184 /* mips_machdep.c */ 185 extern void cpu_identify __P((void)); 186 extern void mips_vector_init __P((void)); 187 188 /* trap.c */ 189 extern void child_return __P((void *)); 190 191 /* 192 * MIPS CPU types (cp_imp). 193 */ 194 #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 195 #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 196 #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 197 #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 198 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 199 #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 200 #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 201 #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 202 #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 203 #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 204 #define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */ 205 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 206 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 207 /* ID conflict */ 208 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 209 #define MIPS_R3SONY MIPS_R4700 /* Sony R3000 CPU ISA I CLASH */ 210 211 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 212 /* ID conflict */ 213 #define MIPS_R5000 0x23 /* MIPS R5000 based CPU ISA IV */ 214 #define MIPS_R3NKK MIPS_R5000 /* NKK R3000 based CPU ISA I CLASH */ 215 216 #define MIPS_RM5230 0x28 /* QED RM5230 based CPU ISA IV */ 217 218 219 /* 220 * MIPS FPU types 221 */ 222 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 223 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 224 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 225 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 226 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 227 #define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 228 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 229 #define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 230 #define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 231 #define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 232 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 233 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 234 #define MIPS_R3SONY MIPS_R4700 /* Sony R3000 based FPU ISA I */ 235 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 236 /* ID conflict */ 237 #define MIPS_R3NKK MIPS_R5000 /* NKK R3000 based CPU ISA I CLASH */ 238 239 #define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 240 #define MIPS_RM5230 0x28 /* QED RM5230 based FPU ISA IV */ 241 242 243 /* 244 * Enable realtime clock (always enabled). 245 */ 246 #define enablertclock() 247 248 #endif /* _CPU_H_ */ 249
Indexes created Sun Sep 21 19:09:51 GMT 2025