cpu.h revision 1.57.2.10
1 /* $NetBSD: cpu.h,v 1.57.2.10 2002/08/01 02:42:30 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifndef _LOCORE 51 #include <sys/sched.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_lockdebug.h" 55 #endif 56 57 struct cpu_info { 58 struct schedstate_percpu ci_schedstate; /* scheduler state */ 59 u_long ci_cpu_freq; /* CPU frequency */ 60 u_long ci_cycles_per_hz; /* CPU freq / hz */ 61 u_long ci_divisor_delay; /* for delay/DELAY */ 62 u_long ci_divisor_recip; /* scaled reciprocal of previous; 63 see below */ 64 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 65 u_long ci_spin_locks; /* # of spin locks held */ 66 u_long ci_simple_locks; /* # of simple locks held */ 67 #endif 68 }; 69 /* 70 * To implement a more accurate microtime using the CP0 COUNT register 71 * we need to divide that register by the number of cycles per MHz. 72 * But... 73 * 74 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 75 * and MULTU are only 12 clocks on the same CPU. 76 * 77 * The strategy we use is to calculate the reciprical of cycles per MHz, 78 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 79 * HI register and have the results of the division. 80 */ 81 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 82 do { \ 83 KASSERT((cpu)->ci_divisor_delay != 0); \ 84 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 85 } while (0) 86 87 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 88 asm volatile("multu %1,%2 ; mfhi %0" \ 89 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 90 #endif /* !defined(_LOCORE) */ 91 92 /* 93 * CTL_MACHDEP definitions. 94 */ 95 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 96 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 97 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 98 99 /* 100 * Platform can override, but note this breaks userland compatibility 101 * with other mips platforms. 102 */ 103 #ifndef CPU_MAXID 104 #define CPU_MAXID 4 /* number of valid machdep ids */ 105 106 #define CTL_MACHDEP_NAMES { \ 107 { 0, 0 }, \ 108 { "console_device", CTLTYPE_STRUCT }, \ 109 { "booted_kernel", CTLTYPE_STRING }, \ 110 { "root_device", CTLTYPE_STRING }, \ 111 } 112 #endif 113 114 #ifdef _KERNEL 115 #ifndef _LOCORE 116 extern struct cpu_info cpu_info_store; 117 118 #define curcpu() (&cpu_info_store) 119 #define cpu_number() (0) 120 #define cpu_proc_fork(p1, p2) 121 #endif /* !_LOCORE */ 122 123 /* 124 * Macros to find the CPU architecture we're on at run-time, 125 * or if possible, at compile-time. 126 */ 127 128 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 129 #define CPU_ARCH_MIPS1 (1 << 0) 130 #define CPU_ARCH_MIPS2 (1 << 1) 131 #define CPU_ARCH_MIPS3 (1 << 2) 132 #define CPU_ARCH_MIPS4 (1 << 3) 133 #define CPU_ARCH_MIPS5 (1 << 4) 134 #define CPU_ARCH_MIPS32 (1 << 5) 135 #define CPU_ARCH_MIPS64 (1 << 6) 136 137 #ifndef _LOCORE 138 /* XXX simonb 139 * Should the following be in a cpu_info type structure? 140 * And how many of these are per-cpu vs. per-system? (Ie, 141 * we can assume that all cpus have the same mmu-type, but 142 * maybe not that all cpus run at the same clock speed. 143 * Some SGI's apparently support R12k and R14k in the same 144 * box.) 145 */ 146 extern int cpu_arch; 147 extern int mips_cpu_flags; 148 extern int mips_has_r4k_mmu; 149 extern int mips_has_llsc; 150 extern int mips3_pg_cached; 151 152 #define CPU_MIPS_R4K_MMU 0x0001 153 #define CPU_MIPS_NO_LLSC 0x0002 154 #define CPU_MIPS_CAUSE_IV 0x0004 155 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 156 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 157 #define CPU_MIPS_CACHED_CCA_SHIFT 4 158 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 159 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 160 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 161 #define MIPS_NOT_SUPP 0x8000 162 163 #ifdef _LKM 164 /* Assume all CPU architectures are valid for LKM's */ 165 #define MIPS1 1 166 #define MIPS3 1 167 #define MIPS4 1 168 #define MIPS32 1 169 #define MIPS64 1 170 #endif 171 172 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 173 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 174 #endif 175 176 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 177 #ifdef MIPS1 178 # define CPUISMIPS3 0 179 # define CPUIS64BITS 0 180 # define CPUISMIPS32 0 181 # define CPUISMIPS64 0 182 # define CPUISMIPSNN 0 183 # define MIPS_HAS_R4K_MMU 0 184 # define MIPS_HAS_CLOCK 0 185 # define MIPS_HAS_LLSC 0 186 #endif /* MIPS1 */ 187 188 #if defined(MIPS3) || defined(MIPS4) 189 # define CPUISMIPS3 1 190 # define CPUIS64BITS 1 191 # define CPUISMIPS32 0 192 # define CPUISMIPS64 0 193 # define CPUISMIPSNN 0 194 # define MIPS_HAS_R4K_MMU 1 195 # define MIPS_HAS_CLOCK 1 196 # define MIPS_HAS_LLSC (mips_has_llsc) 197 #endif /* MIPS3 || MIPS4 */ 198 199 #ifdef MIPS32 200 # define CPUISMIPS3 1 201 # define CPUIS64BITS 0 202 # define CPUISMIPS32 1 203 # define CPUISMIPS64 0 204 # define CPUISMIPSNN 1 205 # define MIPS_HAS_R4K_MMU 1 206 # define MIPS_HAS_CLOCK 1 207 # define MIPS_HAS_LLSC 1 208 #endif /* MIPS32 */ 209 210 #ifdef MIPS64 211 # define CPUISMIPS3 1 212 # define CPUIS64BITS 1 213 # define CPUISMIPS32 0 214 # define CPUISMIPS64 1 215 # define CPUISMIPSNN 1 216 # define MIPS_HAS_R4K_MMU 1 217 # define MIPS_HAS_CLOCK 1 218 # define MIPS_HAS_LLSC 1 219 #endif /* MIPS64 */ 220 221 #else /* run-time test */ 222 223 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 224 #define MIPS_HAS_LLSC (mips_has_llsc) 225 226 /* This test is ... rather bogus */ 227 #define CPUISMIPS3 ((cpu_arch & \ 228 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 229 230 /* And these aren't much better while the previous test exists as is... */ 231 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 232 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 233 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 234 #define CPUIS64BITS ((cpu_arch & \ 235 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 236 237 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 238 #endif /* run-time test */ 239 240 /* Shortcut for MIPS3 or above defined */ 241 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 242 #define MIPS3_PLUS 1 243 #else 244 #undef MIPS3_PLUS 245 #endif 246 247 248 /* 249 * definitions of cpu-dependent requirements 250 * referenced in generic code 251 */ 252 #define cpu_wait(p) /* nothing */ 253 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 254 255 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 256 257 /* 258 * Arguments to hardclock and gatherstats encapsulate the previous 259 * machine state in an opaque clockframe. 260 */ 261 struct clockframe { 262 int pc; /* program counter at time of interrupt */ 263 int sr; /* status register at time of interrupt */ 264 int ppl; /* previous priority level at time of interrupt */ 265 }; 266 267 /* 268 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 269 * in machine-independent code. These differ on r4000 and r3000 systems; 270 * provide them in the port-dependent file that includes this one, using 271 * the macros below. 272 */ 273 274 /* mips1 versions */ 275 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 276 #define MIPS1_CLKF_BASEPRI(framep) \ 277 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 278 279 /* mips3 versions */ 280 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 281 #define MIPS3_CLKF_BASEPRI(framep) \ 282 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 283 284 #ifdef IPL_ICU_MASK 285 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 286 #endif 287 288 #define CLKF_PC(framep) ((framep)->pc) 289 #define CLKF_INTR(framep) (0) 290 291 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 292 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 293 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 294 #endif 295 296 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 297 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 298 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 299 #endif 300 301 #ifdef IPL_ICU_MASK 302 #undef CLKF_BASEPRI 303 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 304 #endif 305 306 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 307 #define CLKF_USERMODE(framep) \ 308 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 309 #define CLKF_BASEPRI(framep) \ 310 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 311 #endif 312 313 /* 314 * This is used during profiling to integrate system time. It can safely 315 * assume that the process is resident. 316 */ 317 #define PROC_PC(p) \ 318 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 319 320 /* 321 * Preempt the current process if in interrupt from user mode, 322 * or after the current trap/syscall if in system mode. 323 */ 324 #define need_resched(ci) \ 325 do { \ 326 want_resched = 1; \ 327 if (curproc != NULL) \ 328 aston(curproc); \ 329 } while (/*CONSTCOND*/0) 330 331 /* 332 * Give a profiling tick to the current process when the user profiling 333 * buffer pages are invalid. On the MIPS, request an ast to send us 334 * through trap, marking the proc as needing a profiling tick. 335 */ 336 #define need_proftick(p) \ 337 do { \ 338 (p)->p_flag |= P_OWEUPC; \ 339 aston(p); \ 340 } while (/*CONSTCOND*/0) 341 342 /* 343 * Notify the current process (p) that it has a signal pending, 344 * process as soon as possible. 345 */ 346 #define signotify(p) aston(p) 347 348 #define aston(p) ((p)->p_md.md_astpending = 1) 349 350 extern int want_resched; /* resched() was called */ 351 352 /* 353 * Misc prototypes and variable declarations. 354 */ 355 struct proc; 356 struct user; 357 358 extern struct lwp *fpcurlwp; 359 360 /* trap.c */ 361 void netintr(void); 362 int kdbpeek(vaddr_t); 363 364 /* mips_machdep.c */ 365 void dumpsys(void); 366 int savectx(struct user *); 367 void mips_init_msgbuf(void); 368 void savefpregs(struct lwp *); 369 void loadfpregs(struct lwp *); 370 371 /* locore*.S */ 372 int badaddr(void *, size_t); 373 int badaddr64(uint64_t, size_t); 374 375 /* mips_machdep.c */ 376 void cpu_identify(void); 377 void mips_vector_init(void); 378 379 #endif /* ! _LOCORE */ 380 #endif /* _KERNEL */ 381 #endif /* _CPU_H_ */ 382
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