cpu.h revision 1.57.2.11
1 /* $NetBSD: cpu.h,v 1.57.2.11 2002/08/13 02:18:29 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifndef _LOCORE 51 #include <sys/sched.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_lockdebug.h" 55 #endif 56 57 struct cpu_info { 58 struct schedstate_percpu ci_schedstate; /* scheduler state */ 59 u_long ci_cpu_freq; /* CPU frequency */ 60 u_long ci_cycles_per_hz; /* CPU freq / hz */ 61 u_long ci_divisor_delay; /* for delay/DELAY */ 62 u_long ci_divisor_recip; /* scaled reciprocal of previous; 63 see below */ 64 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 65 u_long ci_spin_locks; /* # of spin locks held */ 66 u_long ci_simple_locks; /* # of simple locks held */ 67 #endif 68 }; 69 /* 70 * To implement a more accurate microtime using the CP0 COUNT register 71 * we need to divide that register by the number of cycles per MHz. 72 * But... 73 * 74 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 75 * and MULTU are only 12 clocks on the same CPU. 76 * 77 * The strategy we use is to calculate the reciprical of cycles per MHz, 78 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 79 * HI register and have the results of the division. 80 */ 81 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 82 do { \ 83 KASSERT((cpu)->ci_divisor_delay != 0); \ 84 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 85 } while (0) 86 87 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 88 asm volatile("multu %1,%2 ; mfhi %0" \ 89 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 90 #endif /* !defined(_LOCORE) */ 91 92 /* 93 * CTL_MACHDEP definitions. 94 */ 95 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 96 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 97 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 98 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 99 100 /* 101 * Platform can override, but note this breaks userland compatibility 102 * with other mips platforms. 103 */ 104 #ifndef CPU_MAXID 105 #define CPU_MAXID 5 /* number of valid machdep ids */ 106 107 #define CTL_MACHDEP_NAMES { \ 108 { 0, 0 }, \ 109 { "console_device", CTLTYPE_STRUCT }, \ 110 { "booted_kernel", CTLTYPE_STRING }, \ 111 { "root_device", CTLTYPE_STRING }, \ 112 { "llsc", CTLTYPE_INT }, \ 113 } 114 #endif 115 116 #ifdef _KERNEL 117 #ifndef _LOCORE 118 extern struct cpu_info cpu_info_store; 119 120 #define curcpu() (&cpu_info_store) 121 #define cpu_number() (0) 122 #define cpu_proc_fork(p1, p2) 123 #endif /* !_LOCORE */ 124 125 /* 126 * Macros to find the CPU architecture we're on at run-time, 127 * or if possible, at compile-time. 128 */ 129 130 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 131 #define CPU_ARCH_MIPS1 (1 << 0) 132 #define CPU_ARCH_MIPS2 (1 << 1) 133 #define CPU_ARCH_MIPS3 (1 << 2) 134 #define CPU_ARCH_MIPS4 (1 << 3) 135 #define CPU_ARCH_MIPS5 (1 << 4) 136 #define CPU_ARCH_MIPS32 (1 << 5) 137 #define CPU_ARCH_MIPS64 (1 << 6) 138 139 #ifndef _LOCORE 140 /* XXX simonb 141 * Should the following be in a cpu_info type structure? 142 * And how many of these are per-cpu vs. per-system? (Ie, 143 * we can assume that all cpus have the same mmu-type, but 144 * maybe not that all cpus run at the same clock speed. 145 * Some SGI's apparently support R12k and R14k in the same 146 * box.) 147 */ 148 extern int cpu_arch; 149 extern int mips_cpu_flags; 150 extern int mips_has_r4k_mmu; 151 extern int mips_has_llsc; 152 extern int mips3_pg_cached; 153 154 #define CPU_MIPS_R4K_MMU 0x0001 155 #define CPU_MIPS_NO_LLSC 0x0002 156 #define CPU_MIPS_CAUSE_IV 0x0004 157 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 158 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 159 #define CPU_MIPS_CACHED_CCA_SHIFT 4 160 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 161 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 162 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 163 #define MIPS_NOT_SUPP 0x8000 164 165 #ifdef _LKM 166 /* Assume all CPU architectures are valid for LKM's */ 167 #define MIPS1 1 168 #define MIPS3 1 169 #define MIPS4 1 170 #define MIPS32 1 171 #define MIPS64 1 172 #endif 173 174 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 175 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 176 #endif 177 178 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 179 #ifdef MIPS1 180 # define CPUISMIPS3 0 181 # define CPUIS64BITS 0 182 # define CPUISMIPS32 0 183 # define CPUISMIPS64 0 184 # define CPUISMIPSNN 0 185 # define MIPS_HAS_R4K_MMU 0 186 # define MIPS_HAS_CLOCK 0 187 # define MIPS_HAS_LLSC 0 188 #endif /* MIPS1 */ 189 190 #if defined(MIPS3) || defined(MIPS4) 191 # define CPUISMIPS3 1 192 # define CPUIS64BITS 1 193 # define CPUISMIPS32 0 194 # define CPUISMIPS64 0 195 # define CPUISMIPSNN 0 196 # define MIPS_HAS_R4K_MMU 1 197 # define MIPS_HAS_CLOCK 1 198 # define MIPS_HAS_LLSC (mips_has_llsc) 199 #endif /* MIPS3 || MIPS4 */ 200 201 #ifdef MIPS32 202 # define CPUISMIPS3 1 203 # define CPUIS64BITS 0 204 # define CPUISMIPS32 1 205 # define CPUISMIPS64 0 206 # define CPUISMIPSNN 1 207 # define MIPS_HAS_R4K_MMU 1 208 # define MIPS_HAS_CLOCK 1 209 # define MIPS_HAS_LLSC 1 210 #endif /* MIPS32 */ 211 212 #ifdef MIPS64 213 # define CPUISMIPS3 1 214 # define CPUIS64BITS 1 215 # define CPUISMIPS32 0 216 # define CPUISMIPS64 1 217 # define CPUISMIPSNN 1 218 # define MIPS_HAS_R4K_MMU 1 219 # define MIPS_HAS_CLOCK 1 220 # define MIPS_HAS_LLSC 1 221 #endif /* MIPS64 */ 222 223 #else /* run-time test */ 224 225 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 226 #define MIPS_HAS_LLSC (mips_has_llsc) 227 228 /* This test is ... rather bogus */ 229 #define CPUISMIPS3 ((cpu_arch & \ 230 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 231 232 /* And these aren't much better while the previous test exists as is... */ 233 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 234 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 235 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 236 #define CPUIS64BITS ((cpu_arch & \ 237 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 238 239 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 240 #endif /* run-time test */ 241 242 /* Shortcut for MIPS3 or above defined */ 243 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 244 #define MIPS3_PLUS 1 245 #else 246 #undef MIPS3_PLUS 247 #endif 248 249 250 /* 251 * definitions of cpu-dependent requirements 252 * referenced in generic code 253 */ 254 #define cpu_wait(p) /* nothing */ 255 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 256 257 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 258 259 /* 260 * Arguments to hardclock and gatherstats encapsulate the previous 261 * machine state in an opaque clockframe. 262 */ 263 struct clockframe { 264 int pc; /* program counter at time of interrupt */ 265 int sr; /* status register at time of interrupt */ 266 int ppl; /* previous priority level at time of interrupt */ 267 }; 268 269 /* 270 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 271 * in machine-independent code. These differ on r4000 and r3000 systems; 272 * provide them in the port-dependent file that includes this one, using 273 * the macros below. 274 */ 275 276 /* mips1 versions */ 277 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 278 #define MIPS1_CLKF_BASEPRI(framep) \ 279 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 280 281 /* mips3 versions */ 282 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 283 #define MIPS3_CLKF_BASEPRI(framep) \ 284 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 285 286 #ifdef IPL_ICU_MASK 287 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 288 #endif 289 290 #define CLKF_PC(framep) ((framep)->pc) 291 #define CLKF_INTR(framep) (0) 292 293 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 294 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 295 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 296 #endif 297 298 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 299 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 300 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 301 #endif 302 303 #ifdef IPL_ICU_MASK 304 #undef CLKF_BASEPRI 305 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 306 #endif 307 308 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 309 #define CLKF_USERMODE(framep) \ 310 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 311 #define CLKF_BASEPRI(framep) \ 312 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 313 #endif 314 315 /* 316 * This is used during profiling to integrate system time. It can safely 317 * assume that the process is resident. 318 */ 319 #define PROC_PC(p) \ 320 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 321 322 /* 323 * Preempt the current process if in interrupt from user mode, 324 * or after the current trap/syscall if in system mode. 325 */ 326 #define need_resched(ci) \ 327 do { \ 328 want_resched = 1; \ 329 if (curproc != NULL) \ 330 aston(curproc); \ 331 } while (/*CONSTCOND*/0) 332 333 /* 334 * Give a profiling tick to the current process when the user profiling 335 * buffer pages are invalid. On the MIPS, request an ast to send us 336 * through trap, marking the proc as needing a profiling tick. 337 */ 338 #define need_proftick(p) \ 339 do { \ 340 (p)->p_flag |= P_OWEUPC; \ 341 aston(p); \ 342 } while (/*CONSTCOND*/0) 343 344 /* 345 * Notify the current process (p) that it has a signal pending, 346 * process as soon as possible. 347 */ 348 #define signotify(p) aston(p) 349 350 #define aston(p) ((p)->p_md.md_astpending = 1) 351 352 extern int want_resched; /* resched() was called */ 353 354 /* 355 * Misc prototypes and variable declarations. 356 */ 357 struct proc; 358 struct user; 359 360 extern struct lwp *fpcurlwp; 361 362 /* trap.c */ 363 void netintr(void); 364 int kdbpeek(vaddr_t); 365 366 /* mips_machdep.c */ 367 void dumpsys(void); 368 int savectx(struct user *); 369 void mips_init_msgbuf(void); 370 void savefpregs(struct lwp *); 371 void loadfpregs(struct lwp *); 372 373 /* locore*.S */ 374 int badaddr(void *, size_t); 375 int badaddr64(uint64_t, size_t); 376 377 /* mips_machdep.c */ 378 void cpu_identify(void); 379 void mips_vector_init(void); 380 381 #endif /* ! _LOCORE */ 382 #endif /* _KERNEL */ 383 #endif /* _CPU_H_ */ 384
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