cpu.h revision 1.57.2.6
1 /* $NetBSD: cpu.h,v 1.57.2.6 2002/04/17 00:03:46 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifndef _LOCORE 51 #include <sys/sched.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_lockdebug.h" 55 #endif 56 57 struct cpu_info { 58 struct schedstate_percpu ci_schedstate; /* scheduler state */ 59 u_long ci_cpu_freq; /* CPU frequency */ 60 u_long ci_cycles_per_hz; /* CPU freq / hz */ 61 u_long ci_divisor_delay; /* for delay/DELAY */ 62 u_long ci_divisor_recip; /* scaled reciprocal of previous */ 63 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 64 u_long ci_spin_locks; /* # of spin locks held */ 65 u_long ci_simple_locks; /* # of simple locks held */ 66 #endif 67 }; 68 #endif /* !defined(_LOCORE) */ 69 70 /* 71 * CTL_MACHDEP definitions. 72 */ 73 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 74 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 75 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 76 77 /* 78 * Platform can override, but note this breaks userland compatibility 79 * with other mips platforms. 80 */ 81 #ifndef CPU_MAXID 82 #define CPU_MAXID 4 /* number of valid machdep ids */ 83 84 #define CTL_MACHDEP_NAMES { \ 85 { 0, 0 }, \ 86 { "console_device", CTLTYPE_STRUCT }, \ 87 { "booted_kernel", CTLTYPE_STRING }, \ 88 { "root_device", CTLTYPE_STRING }, \ 89 } 90 #endif 91 92 #ifdef _KERNEL 93 #ifndef _LOCORE 94 extern struct cpu_info cpu_info_store; 95 96 #define curcpu() (&cpu_info_store) 97 #define cpu_number() (0) 98 #define cpu_proc_fork(p1, p2) 99 #endif /* !_LOCORE */ 100 101 /* 102 * Macros to find the CPU architecture we're on at run-time, 103 * or if possible, at compile-time. 104 */ 105 106 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 107 #define CPU_ARCH_MIPS1 (1 << 0) 108 #define CPU_ARCH_MIPS2 (1 << 1) 109 #define CPU_ARCH_MIPS3 (1 << 2) 110 #define CPU_ARCH_MIPS4 (1 << 3) 111 #define CPU_ARCH_MIPS5 (1 << 4) 112 #define CPU_ARCH_MIPS32 (1 << 5) 113 #define CPU_ARCH_MIPS64 (1 << 6) 114 115 #ifndef _LOCORE 116 /* XXX simonb 117 * Should the following be in a cpu_info type structure? 118 * And how many of these are per-cpu vs. per-system? (Ie, 119 * we can assume that all cpus have the same mmu-type, but 120 * maybe not that all cpus run at the same clock speed. 121 * Some SGI's apparently support R12k and R14k in the same 122 * box.) 123 */ 124 extern int cpu_arch; 125 extern int mips_cpu_flags; 126 extern int mips_has_r4k_mmu; 127 extern int mips_has_llsc; 128 extern int mips3_pg_cached; 129 130 #define CPU_MIPS_R4K_MMU 0x0001 131 #define CPU_MIPS_NO_LLSC 0x0002 132 #define CPU_MIPS_CAUSE_IV 0x0004 133 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 134 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 135 #define CPU_MIPS_CACHED_CCA_SHIFT 4 136 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 137 #define MIPS_NOT_SUPP 0x8000 138 139 #ifdef _LKM 140 /* Assume all CPU architectures are valid for LKM's */ 141 #define MIPS1 1 142 #define MIPS3 1 143 #define MIPS4 1 144 #define MIPS32 1 145 #define MIPS64 1 146 #endif 147 148 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 149 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 150 #endif 151 152 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 153 #ifdef MIPS1 154 # define CPUISMIPS3 0 155 # define CPUIS64BITS 0 156 # define CPUISMIPS32 0 157 # define CPUISMIPS64 0 158 # define CPUISMIPSNN 0 159 # define MIPS_HAS_R4K_MMU 0 160 # define MIPS_HAS_CLOCK 0 161 # define MIPS_HAS_LLSC 0 162 #endif /* MIPS1 */ 163 164 #if defined(MIPS3) || defined(MIPS4) 165 # define CPUISMIPS3 1 166 # define CPUIS64BITS 1 167 # define CPUISMIPS32 0 168 # define CPUISMIPS64 0 169 # define CPUISMIPSNN 0 170 # define MIPS_HAS_R4K_MMU 1 171 # define MIPS_HAS_CLOCK 1 172 # define MIPS_HAS_LLSC (mips_has_llsc) 173 #endif /* MIPS3 || MIPS4 */ 174 175 #ifdef MIPS32 176 # define CPUISMIPS3 1 177 # define CPUIS64BITS 0 178 # define CPUISMIPS32 1 179 # define CPUISMIPS64 0 180 # define CPUISMIPSNN 1 181 # define MIPS_HAS_R4K_MMU 1 182 # define MIPS_HAS_CLOCK 1 183 # define MIPS_HAS_LLSC 1 184 #endif /* MIPS32 */ 185 186 #ifdef MIPS64 187 # define CPUISMIPS3 1 188 # define CPUIS64BITS 1 189 # define CPUISMIPS32 0 190 # define CPUISMIPS64 1 191 # define CPUISMIPSNN 1 192 # define MIPS_HAS_R4K_MMU 1 193 # define MIPS_HAS_CLOCK 1 194 # define MIPS_HAS_LLSC 1 195 #endif /* MIPS32 */ 196 197 #else /* run-time test */ 198 199 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 200 #define MIPS_HAS_LLSC (mips_has_llsc) 201 202 /* This test is ... rather bogus */ 203 #define CPUISMIPS3 ((cpu_arch & \ 204 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 205 206 /* And these aren't much better while the previous test exists as is... */ 207 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 208 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 209 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 210 #define CPUIS64BITS ((cpu_arch & \ 211 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 212 213 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 214 #endif /* run-time test */ 215 216 /* Shortcut for MIPS3 or above defined */ 217 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 218 #define MIPS3_PLUS 1 219 #else 220 #undef MIPS3_PLUS 221 #endif 222 223 224 /* 225 * definitions of cpu-dependent requirements 226 * referenced in generic code 227 */ 228 #define cpu_wait(p) /* nothing */ 229 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 230 231 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 232 233 /* 234 * Arguments to hardclock and gatherstats encapsulate the previous 235 * machine state in an opaque clockframe. 236 */ 237 struct clockframe { 238 int pc; /* program counter at time of interrupt */ 239 int sr; /* status register at time of interrupt */ 240 int ppl; /* previous priority level at time of interrupt */ 241 }; 242 243 /* 244 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 245 * in machine-independent code. These differ on r4000 and r3000 systems; 246 * provide them in the port-dependent file that includes this one, using 247 * the macros below. 248 */ 249 250 /* mips1 versions */ 251 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 252 #define MIPS1_CLKF_BASEPRI(framep) \ 253 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 254 255 /* mips3 versions */ 256 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 257 #define MIPS3_CLKF_BASEPRI(framep) \ 258 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 259 260 #ifdef IPL_ICU_MASK 261 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 262 #endif 263 264 #define CLKF_PC(framep) ((framep)->pc) 265 #define CLKF_INTR(framep) (0) 266 267 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 268 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 269 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 270 #endif 271 272 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 273 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 274 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 275 #endif 276 277 #ifdef IPL_ICU_MASK 278 #undef CLKF_BASEPRI 279 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 280 #endif 281 282 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 283 #define CLKF_USERMODE(framep) \ 284 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 285 #define CLKF_BASEPRI(framep) \ 286 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 287 #endif 288 289 /* 290 * This is used during profiling to integrate system time. It can safely 291 * assume that the process is resident. 292 */ 293 #define PROC_PC(p) \ 294 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 295 296 /* 297 * Preempt the current process if in interrupt from user mode, 298 * or after the current trap/syscall if in system mode. 299 */ 300 #define need_resched(ci) \ 301 do { \ 302 want_resched = 1; \ 303 if (curproc != NULL) \ 304 aston(curproc->l_proc); \ 305 } while (/*CONSTCOND*/0) 306 307 /* 308 * Give a profiling tick to the current process when the user profiling 309 * buffer pages are invalid. On the MIPS, request an ast to send us 310 * through trap, marking the proc as needing a profiling tick. 311 */ 312 #define need_proftick(p) \ 313 do { \ 314 (p)->p_flag |= P_OWEUPC; \ 315 aston(p); \ 316 } while (/*CONSTCOND*/0) 317 318 /* 319 * Notify the current process (p) that it has a signal pending, 320 * process as soon as possible. 321 */ 322 #define signotify(p) aston(p) 323 324 #define aston(p) ((p)->p_md.md_astpending = 1) 325 326 extern int want_resched; /* resched() was called */ 327 328 /* 329 * Misc prototypes and variable declarations. 330 */ 331 struct proc; 332 struct user; 333 334 extern struct lwp *fpcurproc; 335 336 /* trap.c */ 337 void netintr(void); 338 int kdbpeek(vaddr_t); 339 340 /* mips_machdep.c */ 341 void dumpsys(void); 342 int savectx(struct user *); 343 void mips_init_msgbuf(void); 344 void savefpregs(struct lwp *); 345 void loadfpregs(struct lwp *); 346 347 /* locore*.S */ 348 int badaddr(void *, size_t); 349 int badaddr64(uint64_t, size_t); 350 351 /* mips_machdep.c */ 352 void cpu_identify(void); 353 void mips_vector_init(void); 354 355 #endif /* ! _LOCORE */ 356 #endif /* _KERNEL */ 357 #endif /* _CPU_H_ */ 358
Indexes created Mon Oct 13 08:09:50 GMT 2025