cpu.h revision 1.62
1 /* $NetBSD: cpu.h,v 1.62 2002/04/05 01:22:16 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifndef _LOCORE 51 #include <sys/sched.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_lockdebug.h" 55 #endif 56 57 struct cpu_info { 58 struct schedstate_percpu ci_schedstate; /* scheduler state */ 59 u_long ci_cpu_freq; /* CPU frequency */ 60 u_long ci_cycles_per_hz; /* CPU freq / hz */ 61 u_long ci_divisor_delay; /* for delay/DELAY */ 62 u_long ci_divisor_recip; /* scaled reciprocal of previous */ 63 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 64 u_long ci_spin_locks; /* # of spin locks held */ 65 u_long ci_simple_locks; /* # of simple locks held */ 66 #endif 67 }; 68 #endif /* !defined(_LOCORE) */ 69 70 /* 71 * CTL_MACHDEP definitions. 72 */ 73 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 74 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 75 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 76 77 /* 78 * Platform can override, but note this breaks userland compatibility 79 * with other mips platforms. 80 */ 81 #ifndef CPU_MAXID 82 #define CPU_MAXID 4 /* number of valid machdep ids */ 83 84 #define CTL_MACHDEP_NAMES { \ 85 { 0, 0 }, \ 86 { "console_device", CTLTYPE_STRUCT }, \ 87 { "booted_kernel", CTLTYPE_STRING }, \ 88 { "root_device", CTLTYPE_STRING }, \ 89 } 90 #endif 91 92 #ifdef _KERNEL 93 #ifndef _LOCORE 94 extern struct cpu_info cpu_info_store; 95 96 #define curcpu() (&cpu_info_store) 97 #define cpu_number() (0) 98 #endif /* !_LOCORE */ 99 100 /* 101 * Macros to find the CPU architecture we're on at run-time, 102 * or if possible, at compile-time. 103 */ 104 105 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 106 #define CPU_ARCH_MIPS1 (1 << 0) 107 #define CPU_ARCH_MIPS2 (1 << 1) 108 #define CPU_ARCH_MIPS3 (1 << 2) 109 #define CPU_ARCH_MIPS4 (1 << 3) 110 #define CPU_ARCH_MIPS5 (1 << 4) 111 #define CPU_ARCH_MIPS32 (1 << 5) 112 #define CPU_ARCH_MIPS64 (1 << 6) 113 114 #ifndef _LOCORE 115 /* XXX simonb 116 * Should the following be in a cpu_info type structure? 117 * And how many of these are per-cpu vs. per-system? (Ie, 118 * we can assume that all cpus have the same mmu-type, but 119 * maybe not that all cpus run at the same clock speed. 120 * Some SGI's apparently support R12k and R14k in the same 121 * box.) 122 */ 123 extern int cpu_arch; 124 extern int mips_cpu_flags; 125 extern int mips_has_r4k_mmu; 126 extern int mips_has_llsc; 127 extern int mips3_pg_cached; 128 129 #define CPU_MIPS_R4K_MMU 0x0001 130 #define CPU_MIPS_NO_LLSC 0x0002 131 #define CPU_MIPS_CAUSE_IV 0x0004 132 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 133 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 134 #define CPU_MIPS_CACHED_CCA_SHIFT 4 135 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 136 #define MIPS_NOT_SUPP 0x8000 137 138 #ifdef _LKM 139 /* Assume all CPU architectures are valid for LKM's */ 140 #define MIPS1 1 141 #define MIPS3 1 142 #define MIPS4 1 143 #define MIPS32 1 144 #define MIPS64 1 145 #endif 146 147 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 148 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 149 #endif 150 151 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 152 #ifdef MIPS1 153 # define CPUISMIPS3 0 154 # define CPUIS64BITS 0 155 # define CPUISMIPS32 0 156 # define CPUISMIPS64 0 157 # define CPUISMIPSNN 0 158 # define MIPS_HAS_R4K_MMU 0 159 # define MIPS_HAS_CLOCK 0 160 # define MIPS_HAS_LLSC 0 161 #endif /* MIPS1 */ 162 163 #if defined(MIPS3) || defined(MIPS4) 164 # define CPUISMIPS3 1 165 # define CPUIS64BITS 1 166 # define CPUISMIPS32 0 167 # define CPUISMIPS64 0 168 # define CPUISMIPSNN 0 169 # define MIPS_HAS_R4K_MMU 1 170 # define MIPS_HAS_CLOCK 1 171 # define MIPS_HAS_LLSC (mips_has_llsc) 172 #endif /* MIPS3 || MIPS4 */ 173 174 #ifdef MIPS32 175 # define CPUISMIPS3 1 176 # define CPUIS64BITS 0 177 # define CPUISMIPS32 1 178 # define CPUISMIPS64 0 179 # define CPUISMIPSNN 1 180 # define MIPS_HAS_R4K_MMU 1 181 # define MIPS_HAS_CLOCK 1 182 # define MIPS_HAS_LLSC 1 183 #endif /* MIPS32 */ 184 185 #ifdef MIPS64 186 # define CPUISMIPS3 1 187 # define CPUIS64BITS 1 188 # define CPUISMIPS32 0 189 # define CPUISMIPS64 1 190 # define CPUISMIPSNN 1 191 # define MIPS_HAS_R4K_MMU 1 192 # define MIPS_HAS_CLOCK 1 193 # define MIPS_HAS_LLSC 1 194 #endif /* MIPS32 */ 195 196 #else /* run-time test */ 197 198 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 199 #define MIPS_HAS_LLSC (mips_has_llsc) 200 201 /* This test is ... rather bogus */ 202 #define CPUISMIPS3 ((cpu_arch & \ 203 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 204 205 /* And these aren't much better while the previous test exists as is... */ 206 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 207 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 208 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 209 #define CPUIS64BITS ((cpu_arch & \ 210 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 211 212 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 213 #endif /* run-time test */ 214 215 /* Shortcut for MIPS3 or above defined */ 216 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 217 #define MIPS3_PLUS 1 218 #else 219 #undef MIPS3_PLUS 220 #endif 221 222 223 /* 224 * definitions of cpu-dependent requirements 225 * referenced in generic code 226 */ 227 #define cpu_wait(p) /* nothing */ 228 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 229 230 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 231 232 /* 233 * Arguments to hardclock and gatherstats encapsulate the previous 234 * machine state in an opaque clockframe. 235 */ 236 struct clockframe { 237 int pc; /* program counter at time of interrupt */ 238 int sr; /* status register at time of interrupt */ 239 int ppl; /* previous priority level at time of interrupt */ 240 }; 241 242 /* 243 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 244 * in machine-independent code. These differ on r4000 and r3000 systems; 245 * provide them in the port-dependent file that includes this one, using 246 * the macros below. 247 */ 248 249 /* mips1 versions */ 250 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 251 #define MIPS1_CLKF_BASEPRI(framep) \ 252 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 253 254 /* mips3 versions */ 255 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 256 #define MIPS3_CLKF_BASEPRI(framep) \ 257 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 258 259 #ifdef IPL_ICU_MASK 260 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 261 #endif 262 263 #define CLKF_PC(framep) ((framep)->pc) 264 #define CLKF_INTR(framep) (0) 265 266 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 267 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 268 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 269 #endif 270 271 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 272 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 273 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 274 #endif 275 276 #ifdef IPL_ICU_MASK 277 #undef CLKF_BASEPRI 278 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 279 #endif 280 281 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 282 #define CLKF_USERMODE(framep) \ 283 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 284 #define CLKF_BASEPRI(framep) \ 285 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 286 #endif 287 288 /* 289 * This is used during profiling to integrate system time. It can safely 290 * assume that the process is resident. 291 */ 292 #define PROC_PC(p) \ 293 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 294 295 /* 296 * Preempt the current process if in interrupt from user mode, 297 * or after the current trap/syscall if in system mode. 298 */ 299 #define need_resched(ci) \ 300 do { \ 301 want_resched = 1; \ 302 if (curproc != NULL) \ 303 aston(curproc); \ 304 } while (/*CONSTCOND*/0) 305 306 /* 307 * Give a profiling tick to the current process when the user profiling 308 * buffer pages are invalid. On the MIPS, request an ast to send us 309 * through trap, marking the proc as needing a profiling tick. 310 */ 311 #define need_proftick(p) \ 312 do { \ 313 (p)->p_flag |= P_OWEUPC; \ 314 aston(p); \ 315 } while (/*CONSTCOND*/0) 316 317 /* 318 * Notify the current process (p) that it has a signal pending, 319 * process as soon as possible. 320 */ 321 #define signotify(p) aston(p) 322 323 #define aston(p) ((p)->p_md.md_astpending = 1) 324 325 extern int want_resched; /* resched() was called */ 326 327 /* 328 * Misc prototypes and variable declarations. 329 */ 330 struct proc; 331 struct user; 332 333 extern struct proc *fpcurproc; 334 335 /* trap.c */ 336 void netintr(void); 337 int kdbpeek(vaddr_t); 338 339 /* mips_machdep.c */ 340 void dumpsys(void); 341 int savectx(struct user *); 342 void mips_init_msgbuf(void); 343 void savefpregs(struct proc *); 344 void loadfpregs(struct proc *); 345 346 /* locore*.S */ 347 int badaddr(void *, size_t); 348 int badaddr64(uint64_t, size_t); 349 350 /* mips_machdep.c */ 351 void cpu_identify(void); 352 void mips_vector_init(void); 353 354 #endif /* ! _LOCORE */ 355 #endif /* _KERNEL */ 356 #endif /* _CPU_H_ */ 357
Indexes created Mon Sep 22 05:09:51 GMT 2025