cpu.h revision 1.63
1 /* $NetBSD: cpu.h,v 1.63 2002/06/01 12:10:45 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifndef _LOCORE 51 #include <sys/sched.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_lockdebug.h" 55 #endif 56 57 struct cpu_info { 58 struct schedstate_percpu ci_schedstate; /* scheduler state */ 59 u_long ci_cpu_freq; /* CPU frequency */ 60 u_long ci_cycles_per_hz; /* CPU freq / hz */ 61 u_long ci_divisor_delay; /* for delay/DELAY */ 62 u_long ci_divisor_recip; /* scaled reciprocal of previous */ 63 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 64 u_long ci_spin_locks; /* # of spin locks held */ 65 u_long ci_simple_locks; /* # of simple locks held */ 66 #endif 67 }; 68 #endif /* !defined(_LOCORE) */ 69 70 /* 71 * CTL_MACHDEP definitions. 72 */ 73 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 74 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 75 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 76 77 /* 78 * Platform can override, but note this breaks userland compatibility 79 * with other mips platforms. 80 */ 81 #ifndef CPU_MAXID 82 #define CPU_MAXID 4 /* number of valid machdep ids */ 83 84 #define CTL_MACHDEP_NAMES { \ 85 { 0, 0 }, \ 86 { "console_device", CTLTYPE_STRUCT }, \ 87 { "booted_kernel", CTLTYPE_STRING }, \ 88 { "root_device", CTLTYPE_STRING }, \ 89 } 90 #endif 91 92 #ifdef _KERNEL 93 #ifndef _LOCORE 94 extern struct cpu_info cpu_info_store; 95 96 #define curcpu() (&cpu_info_store) 97 #define cpu_number() (0) 98 #endif /* !_LOCORE */ 99 100 /* 101 * Macros to find the CPU architecture we're on at run-time, 102 * or if possible, at compile-time. 103 */ 104 105 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 106 #define CPU_ARCH_MIPS1 (1 << 0) 107 #define CPU_ARCH_MIPS2 (1 << 1) 108 #define CPU_ARCH_MIPS3 (1 << 2) 109 #define CPU_ARCH_MIPS4 (1 << 3) 110 #define CPU_ARCH_MIPS5 (1 << 4) 111 #define CPU_ARCH_MIPS32 (1 << 5) 112 #define CPU_ARCH_MIPS64 (1 << 6) 113 114 #ifndef _LOCORE 115 /* XXX simonb 116 * Should the following be in a cpu_info type structure? 117 * And how many of these are per-cpu vs. per-system? (Ie, 118 * we can assume that all cpus have the same mmu-type, but 119 * maybe not that all cpus run at the same clock speed. 120 * Some SGI's apparently support R12k and R14k in the same 121 * box.) 122 */ 123 extern int cpu_arch; 124 extern int mips_cpu_flags; 125 extern int mips_has_r4k_mmu; 126 extern int mips_has_llsc; 127 extern int mips3_pg_cached; 128 129 #define CPU_MIPS_R4K_MMU 0x0001 130 #define CPU_MIPS_NO_LLSC 0x0002 131 #define CPU_MIPS_CAUSE_IV 0x0004 132 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 133 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 134 #define CPU_MIPS_CACHED_CCA_SHIFT 4 135 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 136 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 137 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 138 #define MIPS_NOT_SUPP 0x8000 139 140 #ifdef _LKM 141 /* Assume all CPU architectures are valid for LKM's */ 142 #define MIPS1 1 143 #define MIPS3 1 144 #define MIPS4 1 145 #define MIPS32 1 146 #define MIPS64 1 147 #endif 148 149 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 150 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 151 #endif 152 153 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 154 #ifdef MIPS1 155 # define CPUISMIPS3 0 156 # define CPUIS64BITS 0 157 # define CPUISMIPS32 0 158 # define CPUISMIPS64 0 159 # define CPUISMIPSNN 0 160 # define MIPS_HAS_R4K_MMU 0 161 # define MIPS_HAS_CLOCK 0 162 # define MIPS_HAS_LLSC 0 163 #endif /* MIPS1 */ 164 165 #if defined(MIPS3) || defined(MIPS4) 166 # define CPUISMIPS3 1 167 # define CPUIS64BITS 1 168 # define CPUISMIPS32 0 169 # define CPUISMIPS64 0 170 # define CPUISMIPSNN 0 171 # define MIPS_HAS_R4K_MMU 1 172 # define MIPS_HAS_CLOCK 1 173 # define MIPS_HAS_LLSC (mips_has_llsc) 174 #endif /* MIPS3 || MIPS4 */ 175 176 #ifdef MIPS32 177 # define CPUISMIPS3 1 178 # define CPUIS64BITS 0 179 # define CPUISMIPS32 1 180 # define CPUISMIPS64 0 181 # define CPUISMIPSNN 1 182 # define MIPS_HAS_R4K_MMU 1 183 # define MIPS_HAS_CLOCK 1 184 # define MIPS_HAS_LLSC 1 185 #endif /* MIPS32 */ 186 187 #ifdef MIPS64 188 # define CPUISMIPS3 1 189 # define CPUIS64BITS 1 190 # define CPUISMIPS32 0 191 # define CPUISMIPS64 1 192 # define CPUISMIPSNN 1 193 # define MIPS_HAS_R4K_MMU 1 194 # define MIPS_HAS_CLOCK 1 195 # define MIPS_HAS_LLSC 1 196 #endif /* MIPS32 */ 197 198 #else /* run-time test */ 199 200 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 201 #define MIPS_HAS_LLSC (mips_has_llsc) 202 203 /* This test is ... rather bogus */ 204 #define CPUISMIPS3 ((cpu_arch & \ 205 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 206 207 /* And these aren't much better while the previous test exists as is... */ 208 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 209 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 210 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 211 #define CPUIS64BITS ((cpu_arch & \ 212 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 213 214 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 215 #endif /* run-time test */ 216 217 /* Shortcut for MIPS3 or above defined */ 218 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 219 #define MIPS3_PLUS 1 220 #else 221 #undef MIPS3_PLUS 222 #endif 223 224 225 /* 226 * definitions of cpu-dependent requirements 227 * referenced in generic code 228 */ 229 #define cpu_wait(p) /* nothing */ 230 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 231 232 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 233 234 /* 235 * Arguments to hardclock and gatherstats encapsulate the previous 236 * machine state in an opaque clockframe. 237 */ 238 struct clockframe { 239 int pc; /* program counter at time of interrupt */ 240 int sr; /* status register at time of interrupt */ 241 int ppl; /* previous priority level at time of interrupt */ 242 }; 243 244 /* 245 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 246 * in machine-independent code. These differ on r4000 and r3000 systems; 247 * provide them in the port-dependent file that includes this one, using 248 * the macros below. 249 */ 250 251 /* mips1 versions */ 252 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 253 #define MIPS1_CLKF_BASEPRI(framep) \ 254 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 255 256 /* mips3 versions */ 257 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 258 #define MIPS3_CLKF_BASEPRI(framep) \ 259 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 260 261 #ifdef IPL_ICU_MASK 262 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 263 #endif 264 265 #define CLKF_PC(framep) ((framep)->pc) 266 #define CLKF_INTR(framep) (0) 267 268 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 269 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 270 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 271 #endif 272 273 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 274 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 275 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 276 #endif 277 278 #ifdef IPL_ICU_MASK 279 #undef CLKF_BASEPRI 280 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 281 #endif 282 283 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 284 #define CLKF_USERMODE(framep) \ 285 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 286 #define CLKF_BASEPRI(framep) \ 287 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 288 #endif 289 290 /* 291 * This is used during profiling to integrate system time. It can safely 292 * assume that the process is resident. 293 */ 294 #define PROC_PC(p) \ 295 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 296 297 /* 298 * Preempt the current process if in interrupt from user mode, 299 * or after the current trap/syscall if in system mode. 300 */ 301 #define need_resched(ci) \ 302 do { \ 303 want_resched = 1; \ 304 if (curproc != NULL) \ 305 aston(curproc); \ 306 } while (/*CONSTCOND*/0) 307 308 /* 309 * Give a profiling tick to the current process when the user profiling 310 * buffer pages are invalid. On the MIPS, request an ast to send us 311 * through trap, marking the proc as needing a profiling tick. 312 */ 313 #define need_proftick(p) \ 314 do { \ 315 (p)->p_flag |= P_OWEUPC; \ 316 aston(p); \ 317 } while (/*CONSTCOND*/0) 318 319 /* 320 * Notify the current process (p) that it has a signal pending, 321 * process as soon as possible. 322 */ 323 #define signotify(p) aston(p) 324 325 #define aston(p) ((p)->p_md.md_astpending = 1) 326 327 extern int want_resched; /* resched() was called */ 328 329 /* 330 * Misc prototypes and variable declarations. 331 */ 332 struct proc; 333 struct user; 334 335 extern struct proc *fpcurproc; 336 337 /* trap.c */ 338 void netintr(void); 339 int kdbpeek(vaddr_t); 340 341 /* mips_machdep.c */ 342 void dumpsys(void); 343 int savectx(struct user *); 344 void mips_init_msgbuf(void); 345 void savefpregs(struct proc *); 346 void loadfpregs(struct proc *); 347 348 /* locore*.S */ 349 int badaddr(void *, size_t); 350 int badaddr64(uint64_t, size_t); 351 352 /* mips_machdep.c */ 353 void cpu_identify(void); 354 void mips_vector_init(void); 355 356 #endif /* ! _LOCORE */ 357 #endif /* _KERNEL */ 358 #endif /* _CPU_H_ */ 359
Indexes created Wed Sep 24 15:09:51 GMT 2025