cpu.h revision 1.65
1 /* $NetBSD: cpu.h,v 1.65 2002/06/23 20:36:36 manu Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifndef _LOCORE 51 #include <sys/sched.h> 52 53 #if defined(_KERNEL_OPT) 54 #include "opt_lockdebug.h" 55 #endif 56 57 struct cpu_info { 58 struct schedstate_percpu ci_schedstate; /* scheduler state */ 59 u_long ci_cpu_freq; /* CPU frequency */ 60 u_long ci_cycles_per_hz; /* CPU freq / hz */ 61 u_long ci_divisor_delay; /* for delay/DELAY */ 62 u_long ci_divisor_recip; /* scaled reciprocal of previous; 63 see below */ 64 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 65 u_long ci_spin_locks; /* # of spin locks held */ 66 u_long ci_simple_locks; /* # of simple locks held */ 67 #endif 68 }; 69 /* 70 * To implement a more accurate microtime using the CP0 COUNT register 71 * we need to divide that register by the number of cycles per MHz. 72 * But... 73 * 74 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 75 * and MULTU are only 12 clocks on the same CPU. 76 * 77 * The strategy we use is to calculate the reciprical of cycles per MHz, 78 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 79 * HI register and have the results of the division. 80 */ 81 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 82 do { \ 83 KASSERT((cpu)->ci_divisor_delay != 0); \ 84 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 85 } while (0) 86 87 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 88 asm volatile("multu %1,%2 ; mfhi %0" \ 89 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 90 #endif /* !defined(_LOCORE) */ 91 92 /* 93 * CTL_MACHDEP definitions. 94 */ 95 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 96 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 97 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 98 99 /* 100 * Platform can override, but note this breaks userland compatibility 101 * with other mips platforms. 102 */ 103 #ifndef CPU_MAXID 104 #define CPU_MAXID 4 /* number of valid machdep ids */ 105 106 #define CTL_MACHDEP_NAMES { \ 107 { 0, 0 }, \ 108 { "console_device", CTLTYPE_STRUCT }, \ 109 { "booted_kernel", CTLTYPE_STRING }, \ 110 { "root_device", CTLTYPE_STRING }, \ 111 } 112 #endif 113 114 #ifdef _KERNEL 115 #ifndef _LOCORE 116 extern struct cpu_info cpu_info_store; 117 118 #define curcpu() (&cpu_info_store) 119 #define cpu_number() (0) 120 #endif /* !_LOCORE */ 121 122 /* 123 * Macros to find the CPU architecture we're on at run-time, 124 * or if possible, at compile-time. 125 */ 126 127 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 128 #define CPU_ARCH_MIPS1 (1 << 0) 129 #define CPU_ARCH_MIPS2 (1 << 1) 130 #define CPU_ARCH_MIPS3 (1 << 2) 131 #define CPU_ARCH_MIPS4 (1 << 3) 132 #define CPU_ARCH_MIPS5 (1 << 4) 133 #define CPU_ARCH_MIPS32 (1 << 5) 134 #define CPU_ARCH_MIPS64 (1 << 6) 135 136 #ifndef _LOCORE 137 /* XXX simonb 138 * Should the following be in a cpu_info type structure? 139 * And how many of these are per-cpu vs. per-system? (Ie, 140 * we can assume that all cpus have the same mmu-type, but 141 * maybe not that all cpus run at the same clock speed. 142 * Some SGI's apparently support R12k and R14k in the same 143 * box.) 144 */ 145 extern int cpu_arch; 146 extern int mips_cpu_flags; 147 extern int mips_has_r4k_mmu; 148 extern int mips_has_llsc; 149 extern int mips3_pg_cached; 150 151 #define CPU_MIPS_R4K_MMU 0x0001 152 #define CPU_MIPS_NO_LLSC 0x0002 153 #define CPU_MIPS_CAUSE_IV 0x0004 154 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 155 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 156 #define CPU_MIPS_CACHED_CCA_SHIFT 4 157 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 158 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 159 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 160 #define MIPS_NOT_SUPP 0x8000 161 162 #ifdef _LKM 163 /* Assume all CPU architectures are valid for LKM's */ 164 #define MIPS1 1 165 #define MIPS3 1 166 #define MIPS4 1 167 #define MIPS32 1 168 #define MIPS64 1 169 #endif 170 171 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 172 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 173 #endif 174 175 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 176 #ifdef MIPS1 177 # define CPUISMIPS3 0 178 # define CPUIS64BITS 0 179 # define CPUISMIPS32 0 180 # define CPUISMIPS64 0 181 # define CPUISMIPSNN 0 182 # define MIPS_HAS_R4K_MMU 0 183 # define MIPS_HAS_CLOCK 0 184 # define MIPS_HAS_LLSC 0 185 #endif /* MIPS1 */ 186 187 #if defined(MIPS3) || defined(MIPS4) 188 # define CPUISMIPS3 1 189 # define CPUIS64BITS 1 190 # define CPUISMIPS32 0 191 # define CPUISMIPS64 0 192 # define CPUISMIPSNN 0 193 # define MIPS_HAS_R4K_MMU 1 194 # define MIPS_HAS_CLOCK 1 195 # define MIPS_HAS_LLSC (mips_has_llsc) 196 #endif /* MIPS3 || MIPS4 */ 197 198 #ifdef MIPS32 199 # define CPUISMIPS3 1 200 # define CPUIS64BITS 0 201 # define CPUISMIPS32 1 202 # define CPUISMIPS64 0 203 # define CPUISMIPSNN 1 204 # define MIPS_HAS_R4K_MMU 1 205 # define MIPS_HAS_CLOCK 1 206 # define MIPS_HAS_LLSC 1 207 #endif /* MIPS32 */ 208 209 #ifdef MIPS64 210 # define CPUISMIPS3 1 211 # define CPUIS64BITS 1 212 # define CPUISMIPS32 0 213 # define CPUISMIPS64 1 214 # define CPUISMIPSNN 1 215 # define MIPS_HAS_R4K_MMU 1 216 # define MIPS_HAS_CLOCK 1 217 # define MIPS_HAS_LLSC 1 218 #endif /* MIPS64 */ 219 220 #else /* run-time test */ 221 222 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 223 #define MIPS_HAS_LLSC (mips_has_llsc) 224 225 /* This test is ... rather bogus */ 226 #define CPUISMIPS3 ((cpu_arch & \ 227 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 228 229 /* And these aren't much better while the previous test exists as is... */ 230 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 231 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 232 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 233 #define CPUIS64BITS ((cpu_arch & \ 234 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 235 236 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 237 #endif /* run-time test */ 238 239 /* Shortcut for MIPS3 or above defined */ 240 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 241 #define MIPS3_PLUS 1 242 #else 243 #undef MIPS3_PLUS 244 #endif 245 246 247 /* 248 * definitions of cpu-dependent requirements 249 * referenced in generic code 250 */ 251 #define cpu_wait(p) /* nothing */ 252 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 253 254 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 255 256 /* 257 * Arguments to hardclock and gatherstats encapsulate the previous 258 * machine state in an opaque clockframe. 259 */ 260 struct clockframe { 261 int pc; /* program counter at time of interrupt */ 262 int sr; /* status register at time of interrupt */ 263 int ppl; /* previous priority level at time of interrupt */ 264 }; 265 266 /* 267 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 268 * in machine-independent code. These differ on r4000 and r3000 systems; 269 * provide them in the port-dependent file that includes this one, using 270 * the macros below. 271 */ 272 273 /* mips1 versions */ 274 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 275 #define MIPS1_CLKF_BASEPRI(framep) \ 276 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 277 278 /* mips3 versions */ 279 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 280 #define MIPS3_CLKF_BASEPRI(framep) \ 281 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 282 283 #ifdef IPL_ICU_MASK 284 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 285 #endif 286 287 #define CLKF_PC(framep) ((framep)->pc) 288 #define CLKF_INTR(framep) (0) 289 290 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 291 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 292 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 293 #endif 294 295 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 296 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 297 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 298 #endif 299 300 #ifdef IPL_ICU_MASK 301 #undef CLKF_BASEPRI 302 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 303 #endif 304 305 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 306 #define CLKF_USERMODE(framep) \ 307 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 308 #define CLKF_BASEPRI(framep) \ 309 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 310 #endif 311 312 /* 313 * This is used during profiling to integrate system time. It can safely 314 * assume that the process is resident. 315 */ 316 #define PROC_PC(p) \ 317 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 318 319 /* 320 * Preempt the current process if in interrupt from user mode, 321 * or after the current trap/syscall if in system mode. 322 */ 323 #define need_resched(ci) \ 324 do { \ 325 want_resched = 1; \ 326 if (curproc != NULL) \ 327 aston(curproc); \ 328 } while (/*CONSTCOND*/0) 329 330 /* 331 * Give a profiling tick to the current process when the user profiling 332 * buffer pages are invalid. On the MIPS, request an ast to send us 333 * through trap, marking the proc as needing a profiling tick. 334 */ 335 #define need_proftick(p) \ 336 do { \ 337 (p)->p_flag |= P_OWEUPC; \ 338 aston(p); \ 339 } while (/*CONSTCOND*/0) 340 341 /* 342 * Notify the current process (p) that it has a signal pending, 343 * process as soon as possible. 344 */ 345 #define signotify(p) aston(p) 346 347 #define aston(p) ((p)->p_md.md_astpending = 1) 348 349 extern int want_resched; /* resched() was called */ 350 351 /* 352 * Misc prototypes and variable declarations. 353 */ 354 struct proc; 355 struct user; 356 357 extern struct proc *fpcurproc; 358 359 /* trap.c */ 360 void netintr(void); 361 int kdbpeek(vaddr_t); 362 363 /* mips_machdep.c */ 364 void dumpsys(void); 365 int savectx(struct user *); 366 void mips_init_msgbuf(void); 367 void savefpregs(struct proc *); 368 void loadfpregs(struct proc *); 369 370 /* locore*.S */ 371 int badaddr(void *, size_t); 372 int badaddr64(uint64_t, size_t); 373 374 /* mips_machdep.c */ 375 void cpu_identify(void); 376 void mips_vector_init(void); 377 378 #endif /* ! _LOCORE */ 379 #endif /* _KERNEL */ 380 #endif /* _CPU_H_ */ 381
Indexes created Tue Sep 23 07:09:52 GMT 2025