cpu.h revision 1.68
1 /* $NetBSD: cpu.h,v 1.68 2002/11/24 07:26:04 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifdef _KERNEL 51 #ifndef _LOCORE 52 #include <sys/sched.h> 53 54 #if defined(_KERNEL_OPT) 55 #include "opt_lockdebug.h" 56 #endif 57 58 struct cpu_info { 59 struct schedstate_percpu ci_schedstate; /* scheduler state */ 60 u_long ci_cpu_freq; /* CPU frequency */ 61 u_long ci_cycles_per_hz; /* CPU freq / hz */ 62 u_long ci_divisor_delay; /* for delay/DELAY */ 63 u_long ci_divisor_recip; /* scaled reciprocal of previous; 64 see below */ 65 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 66 u_long ci_spin_locks; /* # of spin locks held */ 67 u_long ci_simple_locks; /* # of simple locks held */ 68 #endif 69 }; 70 71 /* 72 * To implement a more accurate microtime using the CP0 COUNT register 73 * we need to divide that register by the number of cycles per MHz. 74 * But... 75 * 76 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 77 * and MULTU are only 12 clocks on the same CPU. 78 * 79 * The strategy we use is to calculate the reciprical of cycles per MHz, 80 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 81 * HI register and have the results of the division. 82 */ 83 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 84 do { \ 85 KASSERT((cpu)->ci_divisor_delay != 0); \ 86 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 87 } while (0) 88 89 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 90 asm volatile("multu %1,%2 ; mfhi %0" \ 91 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 92 93 #endif /* !_LOCORE */ 94 #endif /* _KERNEL */ 95 96 /* 97 * CTL_MACHDEP definitions. 98 */ 99 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 100 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 101 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 102 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 103 104 /* 105 * Platform can override, but note this breaks userland compatibility 106 * with other mips platforms. 107 */ 108 #ifndef CPU_MAXID 109 #define CPU_MAXID 5 /* number of valid machdep ids */ 110 111 #define CTL_MACHDEP_NAMES { \ 112 { 0, 0 }, \ 113 { "console_device", CTLTYPE_STRUCT }, \ 114 { "booted_kernel", CTLTYPE_STRING }, \ 115 { "root_device", CTLTYPE_STRING }, \ 116 { "llsc", CTLTYPE_INT }, \ 117 } 118 #endif 119 120 #ifdef _KERNEL 121 #ifndef _LOCORE 122 extern struct cpu_info cpu_info_store; 123 124 #define curcpu() (&cpu_info_store) 125 #define cpu_number() (0) 126 #endif /* !_LOCORE */ 127 128 /* 129 * Macros to find the CPU architecture we're on at run-time, 130 * or if possible, at compile-time. 131 */ 132 133 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 134 #define CPU_ARCH_MIPS1 (1 << 0) 135 #define CPU_ARCH_MIPS2 (1 << 1) 136 #define CPU_ARCH_MIPS3 (1 << 2) 137 #define CPU_ARCH_MIPS4 (1 << 3) 138 #define CPU_ARCH_MIPS5 (1 << 4) 139 #define CPU_ARCH_MIPS32 (1 << 5) 140 #define CPU_ARCH_MIPS64 (1 << 6) 141 142 #ifndef _LOCORE 143 /* XXX simonb 144 * Should the following be in a cpu_info type structure? 145 * And how many of these are per-cpu vs. per-system? (Ie, 146 * we can assume that all cpus have the same mmu-type, but 147 * maybe not that all cpus run at the same clock speed. 148 * Some SGI's apparently support R12k and R14k in the same 149 * box.) 150 */ 151 extern int cpu_arch; 152 extern int mips_cpu_flags; 153 extern int mips_has_r4k_mmu; 154 extern int mips_has_llsc; 155 extern int mips3_pg_cached; 156 157 #define CPU_MIPS_R4K_MMU 0x0001 158 #define CPU_MIPS_NO_LLSC 0x0002 159 #define CPU_MIPS_CAUSE_IV 0x0004 160 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 161 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 162 #define CPU_MIPS_CACHED_CCA_SHIFT 4 163 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 164 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 165 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 166 #define MIPS_NOT_SUPP 0x8000 167 168 #ifdef _LKM 169 /* Assume all CPU architectures are valid for LKM's */ 170 #define MIPS1 1 171 #define MIPS3 1 172 #define MIPS4 1 173 #define MIPS32 1 174 #define MIPS64 1 175 #endif 176 177 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 178 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 179 #endif 180 181 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 182 #ifdef MIPS1 183 # define CPUISMIPS3 0 184 # define CPUIS64BITS 0 185 # define CPUISMIPS32 0 186 # define CPUISMIPS64 0 187 # define CPUISMIPSNN 0 188 # define MIPS_HAS_R4K_MMU 0 189 # define MIPS_HAS_CLOCK 0 190 # define MIPS_HAS_LLSC 0 191 #endif /* MIPS1 */ 192 193 #if defined(MIPS3) || defined(MIPS4) 194 # define CPUISMIPS3 1 195 # define CPUIS64BITS 1 196 # define CPUISMIPS32 0 197 # define CPUISMIPS64 0 198 # define CPUISMIPSNN 0 199 # define MIPS_HAS_R4K_MMU 1 200 # define MIPS_HAS_CLOCK 1 201 # define MIPS_HAS_LLSC (mips_has_llsc) 202 #endif /* MIPS3 || MIPS4 */ 203 204 #ifdef MIPS32 205 # define CPUISMIPS3 1 206 # define CPUIS64BITS 0 207 # define CPUISMIPS32 1 208 # define CPUISMIPS64 0 209 # define CPUISMIPSNN 1 210 # define MIPS_HAS_R4K_MMU 1 211 # define MIPS_HAS_CLOCK 1 212 # define MIPS_HAS_LLSC 1 213 #endif /* MIPS32 */ 214 215 #ifdef MIPS64 216 # define CPUISMIPS3 1 217 # define CPUIS64BITS 1 218 # define CPUISMIPS32 0 219 # define CPUISMIPS64 1 220 # define CPUISMIPSNN 1 221 # define MIPS_HAS_R4K_MMU 1 222 # define MIPS_HAS_CLOCK 1 223 # define MIPS_HAS_LLSC 1 224 #endif /* MIPS64 */ 225 226 #else /* run-time test */ 227 228 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 229 #define MIPS_HAS_LLSC (mips_has_llsc) 230 231 /* This test is ... rather bogus */ 232 #define CPUISMIPS3 ((cpu_arch & \ 233 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 234 235 /* And these aren't much better while the previous test exists as is... */ 236 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 237 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 238 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 239 #define CPUIS64BITS ((cpu_arch & \ 240 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 241 242 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 243 #endif /* run-time test */ 244 245 /* Shortcut for MIPS3 or above defined */ 246 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 247 #define MIPS3_PLUS 1 248 #else 249 #undef MIPS3_PLUS 250 #endif 251 252 253 /* 254 * definitions of cpu-dependent requirements 255 * referenced in generic code 256 */ 257 #define cpu_wait(p) /* nothing */ 258 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 259 260 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 261 262 /* 263 * Arguments to hardclock and gatherstats encapsulate the previous 264 * machine state in an opaque clockframe. 265 */ 266 struct clockframe { 267 int pc; /* program counter at time of interrupt */ 268 int sr; /* status register at time of interrupt */ 269 int ppl; /* previous priority level at time of interrupt */ 270 }; 271 272 /* 273 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 274 * in machine-independent code. These differ on r4000 and r3000 systems; 275 * provide them in the port-dependent file that includes this one, using 276 * the macros below. 277 */ 278 279 /* mips1 versions */ 280 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 281 #define MIPS1_CLKF_BASEPRI(framep) \ 282 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 283 284 /* mips3 versions */ 285 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 286 #define MIPS3_CLKF_BASEPRI(framep) \ 287 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 288 289 #ifdef IPL_ICU_MASK 290 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 291 #endif 292 293 #define CLKF_PC(framep) ((framep)->pc) 294 #define CLKF_INTR(framep) (0) 295 296 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 297 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 298 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 299 #endif 300 301 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 302 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 303 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 304 #endif 305 306 #ifdef IPL_ICU_MASK 307 #undef CLKF_BASEPRI 308 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 309 #endif 310 311 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 312 #define CLKF_USERMODE(framep) \ 313 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 314 #define CLKF_BASEPRI(framep) \ 315 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 316 #endif 317 318 /* 319 * This is used during profiling to integrate system time. It can safely 320 * assume that the process is resident. 321 */ 322 #define PROC_PC(p) \ 323 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 324 325 /* 326 * Preempt the current process if in interrupt from user mode, 327 * or after the current trap/syscall if in system mode. 328 */ 329 #define need_resched(ci) \ 330 do { \ 331 want_resched = 1; \ 332 if (curproc != NULL) \ 333 aston(curproc); \ 334 } while (/*CONSTCOND*/0) 335 336 /* 337 * Give a profiling tick to the current process when the user profiling 338 * buffer pages are invalid. On the MIPS, request an ast to send us 339 * through trap, marking the proc as needing a profiling tick. 340 */ 341 #define need_proftick(p) \ 342 do { \ 343 (p)->p_flag |= P_OWEUPC; \ 344 aston(p); \ 345 } while (/*CONSTCOND*/0) 346 347 /* 348 * Notify the current process (p) that it has a signal pending, 349 * process as soon as possible. 350 */ 351 #define signotify(p) aston(p) 352 353 #define aston(p) ((p)->p_md.md_astpending = 1) 354 355 extern int want_resched; /* resched() was called */ 356 357 /* 358 * Misc prototypes and variable declarations. 359 */ 360 struct proc; 361 struct user; 362 363 extern struct proc *fpcurproc; /* the current FPU owner */ 364 extern struct pcb *curpcb; /* the current running pcb */ 365 extern struct segtab *segbase; /* current segtab base */ 366 367 /* trap.c */ 368 void netintr(void); 369 int kdbpeek(vaddr_t); 370 371 /* mips_machdep.c */ 372 void dumpsys(void); 373 int savectx(struct user *); 374 void mips_init_msgbuf(void); 375 void savefpregs(struct proc *); 376 void loadfpregs(struct proc *); 377 378 /* locore*.S */ 379 int badaddr(void *, size_t); 380 int badaddr64(uint64_t, size_t); 381 382 /* mips_machdep.c */ 383 void cpu_identify(void); 384 void mips_vector_init(void); 385 386 #endif /* ! _LOCORE */ 387 #endif /* _KERNEL */ 388 #endif /* _CPU_H_ */ 389
Indexes created Sun Sep 21 19:09:51 GMT 2025